722ca45292abe5011e441adf5c2b1fa9e2b32921
1 // See LICENSE for license details.
22 processor_t::processor_t(const char* isa
, sim_t
* sim
, uint32_t id
,
24 : debug(false), halt_request(false), sim(sim
), ext(NULL
), id(id
),
25 halt_on_reset(halt_on_reset
), last_pc(1), executions(1)
27 parse_isa_string(isa
);
28 register_base_instructions();
30 mmu
= new mmu_t(sim
, this);
31 disassembler
= new disassembler_t(max_xlen
);
36 processor_t::~processor_t()
38 #ifdef RISCV_ENABLE_HISTOGRAM
39 if (histogram_enabled
)
41 fprintf(stderr
, "PC Histogram size:%zu\n", pc_histogram
.size());
42 for (auto it
: pc_histogram
)
43 fprintf(stderr
, "%0" PRIx64
" %" PRIu64
"\n", it
.first
, it
.second
);
51 static void bad_isa_string(const char* isa
)
53 fprintf(stderr
, "error: bad --isa option %s\n", isa
);
57 void processor_t::parse_isa_string(const char* str
)
59 std::string lowercase
, tmp
;
60 for (const char *r
= str
; *r
; r
++)
61 lowercase
+= std::tolower(*r
);
63 const char* p
= lowercase
.c_str();
64 const char* all_subsets
= "imafdqc";
69 if (strncmp(p
, "rv32", 4) == 0)
70 max_xlen
= 32, isa
= reg_t(1) << 30, p
+= 4;
71 else if (strncmp(p
, "rv64", 4) == 0)
73 else if (strncmp(p
, "rv", 2) == 0)
78 } else if (*p
== 'g') { // treat "G" as "IMAFD"
79 tmp
= std::string("imafd") + (p
+1);
81 } else if (*p
!= 'i') {
85 isa_string
= "rv" + std::to_string(max_xlen
) + p
;
86 isa
|= 1L << ('s' - 'a'); // advertise support for supervisor mode
87 isa
|= 1L << ('u' - 'a'); // advertise support for user mode
90 isa
|= 1L << (*p
- 'a');
92 if (auto next
= strchr(all_subsets
, *p
)) {
93 all_subsets
= next
+ 1;
95 } else if (*p
== 'x') {
96 const char* ext
= p
+1, *end
= ext
;
99 register_extension(find_extension(std::string(ext
, end
- ext
).c_str())());
106 if (supports_extension('D') && !supports_extension('F'))
109 if (supports_extension('Q') && !supports_extension('D'))
112 if (supports_extension('Q') && max_xlen
< 64)
118 void state_t::reset()
120 memset(this, 0, sizeof(*this));
123 load_reservation
= -1;
125 for (unsigned int i
= 0; i
< num_triggers
; i
++)
126 mcontrol
[i
].type
= 2;
129 void processor_t::set_debug(bool value
)
133 ext
->set_debug(value
);
136 void processor_t::set_histogram(bool value
)
138 histogram_enabled
= value
;
139 #ifndef RISCV_ENABLE_HISTOGRAM
141 fprintf(stderr
, "PC Histogram support has not been properly enabled;");
142 fprintf(stderr
, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
147 void processor_t::reset()
150 state
.dcsr
.halt
= halt_on_reset
;
151 halt_on_reset
= false;
152 set_csr(CSR_MSTATUS
, state
.mstatus
);
155 ext
->reset(); // reset the extension
158 // Count number of contiguous 0 bits starting from the LSB.
159 static int ctz(reg_t val
)
163 while ((val
& 1) == 0)
168 void processor_t::take_interrupt(reg_t pending_interrupts
)
170 reg_t mie
= get_field(state
.mstatus
, MSTATUS_MIE
);
171 reg_t m_enabled
= state
.prv
< PRV_M
|| (state
.prv
== PRV_M
&& mie
);
172 reg_t enabled_interrupts
= pending_interrupts
& ~state
.mideleg
& -m_enabled
;
174 reg_t sie
= get_field(state
.mstatus
, MSTATUS_SIE
);
175 reg_t s_enabled
= state
.prv
< PRV_S
|| (state
.prv
== PRV_S
&& sie
);
176 // M-ints have highest priority; consider S-ints only if no M-ints pending
177 if (enabled_interrupts
== 0)
178 enabled_interrupts
= pending_interrupts
& state
.mideleg
& -s_enabled
;
180 if (state
.dcsr
.cause
== 0 && enabled_interrupts
) {
181 // nonstandard interrupts have highest priority
182 if (enabled_interrupts
>> IRQ_M_EXT
)
183 enabled_interrupts
= enabled_interrupts
>> IRQ_M_EXT
<< IRQ_M_EXT
;
184 // external interrupts have next-highest priority
185 else if (enabled_interrupts
& (MIP_MEIP
| MIP_SEIP
))
186 enabled_interrupts
= enabled_interrupts
& (MIP_MEIP
| MIP_SEIP
);
187 // software interrupts have next-highest priority
188 else if (enabled_interrupts
& (MIP_MSIP
| MIP_SSIP
))
189 enabled_interrupts
= enabled_interrupts
& (MIP_MSIP
| MIP_SSIP
);
190 // timer interrupts have next-highest priority
191 else if (enabled_interrupts
& (MIP_MTIP
| MIP_STIP
))
192 enabled_interrupts
= enabled_interrupts
& (MIP_MTIP
| MIP_STIP
);
196 throw trap_t(((reg_t
)1 << (max_xlen
-1)) | ctz(enabled_interrupts
));
200 static int xlen_to_uxl(int xlen
)
209 reg_t
processor_t::legalize_privilege(reg_t prv
)
211 assert(prv
<= PRV_M
);
213 if (!supports_extension('U'))
216 if (prv
== PRV_H
|| !supports_extension('S'))
222 void processor_t::set_privilege(reg_t prv
)
225 state
.prv
= legalize_privilege(prv
);
228 void processor_t::enter_debug_mode(uint8_t cause
)
230 state
.dcsr
.cause
= cause
;
231 state
.dcsr
.prv
= state
.prv
;
232 set_privilege(PRV_M
);
233 state
.dpc
= state
.pc
;
234 state
.pc
= DEBUG_ROM_ENTRY
;
237 void processor_t::take_trap(trap_t
& t
, reg_t epc
)
240 fprintf(stderr
, "core %3d: exception %s, epc 0x%016" PRIx64
"\n",
243 fprintf(stderr
, "core %3d: badaddr 0x%016" PRIx64
"\n", id
,
247 if (state
.dcsr
.cause
) {
248 if (t
.cause() == CAUSE_BREAKPOINT
) {
249 state
.pc
= DEBUG_ROM_ENTRY
;
251 state
.pc
= DEBUG_ROM_TVEC
;
256 if (t
.cause() == CAUSE_BREAKPOINT
&& (
257 (state
.prv
== PRV_M
&& state
.dcsr
.ebreakm
) ||
258 (state
.prv
== PRV_S
&& state
.dcsr
.ebreaks
) ||
259 (state
.prv
== PRV_U
&& state
.dcsr
.ebreaku
))) {
260 enter_debug_mode(DCSR_CAUSE_SWBP
);
264 // by default, trap to M-mode, unless delegated to S-mode
265 reg_t bit
= t
.cause();
266 reg_t deleg
= state
.medeleg
;
267 bool interrupt
= (bit
& ((reg_t
)1 << (max_xlen
-1))) != 0;
269 deleg
= state
.mideleg
, bit
&= ~((reg_t
)1 << (max_xlen
-1));
270 if (state
.prv
<= PRV_S
&& bit
< max_xlen
&& ((deleg
>> bit
) & 1)) {
271 // handle the trap in S-mode
272 state
.pc
= state
.stvec
;
273 state
.scause
= t
.cause();
276 state
.sbadaddr
= t
.get_badaddr();
278 reg_t s
= state
.mstatus
;
279 s
= set_field(s
, MSTATUS_SPIE
, get_field(s
, MSTATUS_SIE
));
280 s
= set_field(s
, MSTATUS_SPP
, state
.prv
);
281 s
= set_field(s
, MSTATUS_SIE
, 0);
282 set_csr(CSR_MSTATUS
, s
);
283 set_privilege(PRV_S
);
285 reg_t vector
= (state
.mtvec
& 1) && interrupt
? 4*bit
: 0;
286 state
.pc
= (state
.mtvec
& ~(reg_t
)1) + vector
;
288 state
.mcause
= t
.cause();
290 state
.mbadaddr
= t
.get_badaddr();
292 reg_t s
= state
.mstatus
;
293 s
= set_field(s
, MSTATUS_MPIE
, get_field(s
, MSTATUS_MIE
));
294 s
= set_field(s
, MSTATUS_MPP
, state
.prv
);
295 s
= set_field(s
, MSTATUS_MIE
, 0);
296 set_csr(CSR_MSTATUS
, s
);
297 set_privilege(PRV_M
);
300 yield_load_reservation();
303 void processor_t::disasm(insn_t insn
)
305 uint64_t bits
= insn
.bits() & ((1ULL << (8 * insn_length(insn
.bits()))) - 1);
306 if (last_pc
!= state
.pc
|| last_bits
!= bits
) {
307 if (executions
!= 1) {
308 fprintf(stderr
, "core %3d: Executed %" PRIx64
" times\n", id
, executions
);
311 fprintf(stderr
, "core %3d: 0x%016" PRIx64
" (0x%08" PRIx64
") %s\n",
312 id
, state
.pc
, bits
, disassembler
->disassemble(insn
).c_str());
321 int processor_t::paddr_bits()
323 assert(xlen
== max_xlen
);
324 return max_xlen
== 64 ? 50 : 34;
327 void processor_t::set_csr(int which
, reg_t val
)
329 val
= zext_xlen(val
);
330 reg_t delegable_ints
= MIP_SSIP
| MIP_STIP
| MIP_SEIP
| (1 << IRQ_COP
);
331 reg_t all_ints
= delegable_ints
| MIP_MSIP
| MIP_MTIP
;
336 state
.fflags
= val
& (FSR_AEXC
>> FSR_AEXC_SHIFT
);
340 state
.frm
= val
& (FSR_RD
>> FSR_RD_SHIFT
);
344 state
.fflags
= (val
& FSR_AEXC
) >> FSR_AEXC_SHIFT
;
345 state
.frm
= (val
& FSR_RD
) >> FSR_RD_SHIFT
;
348 if ((val
^ state
.mstatus
) &
349 (MSTATUS_MPP
| MSTATUS_MPRV
| MSTATUS_SUM
| MSTATUS_MXR
))
352 reg_t mask
= MSTATUS_SIE
| MSTATUS_SPIE
| MSTATUS_MIE
| MSTATUS_MPIE
353 | MSTATUS_FS
| MSTATUS_MPRV
| MSTATUS_SUM
354 | MSTATUS_MXR
| MSTATUS_TW
| MSTATUS_TVM
355 | MSTATUS_TSR
| MSTATUS_UXL
| MSTATUS_SXL
|
356 (ext
? MSTATUS_XS
: 0);
358 reg_t requested_mpp
= legalize_privilege(get_field(val
, MSTATUS_MPP
));
359 state
.mstatus
= set_field(state
.mstatus
, MSTATUS_MPP
, requested_mpp
);
360 if (supports_extension('S'))
363 state
.mstatus
= (state
.mstatus
& ~mask
) | (val
& mask
);
365 bool dirty
= (state
.mstatus
& MSTATUS_FS
) == MSTATUS_FS
;
366 dirty
|= (state
.mstatus
& MSTATUS_XS
) == MSTATUS_XS
;
368 state
.mstatus
= set_field(state
.mstatus
, MSTATUS32_SD
, dirty
);
370 state
.mstatus
= set_field(state
.mstatus
, MSTATUS64_SD
, dirty
);
372 state
.mstatus
= set_field(state
.mstatus
, MSTATUS_UXL
, xlen_to_uxl(max_xlen
));
373 state
.mstatus
= set_field(state
.mstatus
, MSTATUS_UXL
, xlen_to_uxl(max_xlen
));
374 state
.mstatus
= set_field(state
.mstatus
, MSTATUS_SXL
, xlen_to_uxl(max_xlen
));
375 // U-XLEN == S-XLEN == M-XLEN
380 reg_t mask
= MIP_SSIP
| MIP_STIP
;
381 state
.mip
= (state
.mip
& ~mask
) | (val
& mask
);
385 state
.mie
= (state
.mie
& ~all_ints
) | (val
& all_ints
);
388 state
.mideleg
= (state
.mideleg
& ~delegable_ints
) | (val
& delegable_ints
);
392 (1 << CAUSE_MISALIGNED_FETCH
) |
393 (1 << CAUSE_BREAKPOINT
) |
394 (1 << CAUSE_USER_ECALL
) |
395 (1 << CAUSE_FETCH_PAGE_FAULT
) |
396 (1 << CAUSE_LOAD_PAGE_FAULT
) |
397 (1 << CAUSE_STORE_PAGE_FAULT
);
398 state
.medeleg
= (state
.medeleg
& ~mask
) | (val
& mask
);
404 state
.minstret
= (state
.minstret
>> 32 << 32) | (val
& 0xffffffffU
);
406 state
.minstret
= val
;
410 state
.minstret
= (val
<< 32) | (state
.minstret
<< 32 >> 32);
413 state
.scounteren
= val
;
416 state
.mcounteren
= val
;
419 reg_t mask
= SSTATUS_SIE
| SSTATUS_SPIE
| SSTATUS_SPP
| SSTATUS_FS
420 | SSTATUS_XS
| SSTATUS_SUM
| SSTATUS_MXR
;
421 return set_csr(CSR_MSTATUS
, (state
.mstatus
& ~mask
) | (val
& mask
));
424 reg_t mask
= MIP_SSIP
& state
.mideleg
;
425 return set_csr(CSR_MIP
, (state
.mip
& ~mask
) | (val
& mask
));
428 return set_csr(CSR_MIE
,
429 (state
.mie
& ~state
.mideleg
) | (val
& state
.mideleg
));
433 state
.sptbr
= val
& (SPTBR32_PPN
| SPTBR32_MODE
);
434 if (max_xlen
== 64 && (get_field(val
, SPTBR64_MODE
) == SPTBR_MODE_OFF
||
435 get_field(val
, SPTBR64_MODE
) == SPTBR_MODE_SV39
||
436 get_field(val
, SPTBR64_MODE
) == SPTBR_MODE_SV48
))
437 state
.sptbr
= val
& (SPTBR64_PPN
| SPTBR64_MODE
);
440 case CSR_SEPC
: state
.sepc
= val
; break;
441 case CSR_STVEC
: state
.stvec
= val
>> 2 << 2; break;
442 case CSR_SSCRATCH
: state
.sscratch
= val
; break;
443 case CSR_SCAUSE
: state
.scause
= val
; break;
444 case CSR_SBADADDR
: state
.sbadaddr
= val
; break;
445 case CSR_MEPC
: state
.mepc
= val
; break;
446 case CSR_MTVEC
: state
.mtvec
= val
& ~(reg_t
)2; break;
447 case CSR_MSCRATCH
: state
.mscratch
= val
; break;
448 case CSR_MCAUSE
: state
.mcause
= val
; break;
449 case CSR_MBADADDR
: state
.mbadaddr
= val
; break;
451 if (!(val
& (1L << ('F' - 'A'))))
452 val
&= ~(1L << ('D' - 'A'));
454 // allow MAFDC bits in MISA to be modified
456 mask
|= 1L << ('M' - 'A');
457 mask
|= 1L << ('A' - 'A');
458 mask
|= 1L << ('F' - 'A');
459 mask
|= 1L << ('D' - 'A');
460 mask
|= 1L << ('C' - 'A');
463 isa
= (val
& mask
) | (isa
& ~mask
);
467 if (val
< state
.num_triggers
) {
473 mcontrol_t
*mc
= &state
.mcontrol
[state
.tselect
];
474 if (mc
->dmode
&& !state
.dcsr
.cause
) {
477 mc
->dmode
= get_field(val
, MCONTROL_DMODE(xlen
));
478 mc
->select
= get_field(val
, MCONTROL_SELECT
);
479 mc
->timing
= get_field(val
, MCONTROL_TIMING
);
480 mc
->action
= (mcontrol_action_t
) get_field(val
, MCONTROL_ACTION
);
481 mc
->chain
= get_field(val
, MCONTROL_CHAIN
);
482 mc
->match
= (mcontrol_match_t
) get_field(val
, MCONTROL_MATCH
);
483 mc
->m
= get_field(val
, MCONTROL_M
);
484 mc
->h
= get_field(val
, MCONTROL_H
);
485 mc
->s
= get_field(val
, MCONTROL_S
);
486 mc
->u
= get_field(val
, MCONTROL_U
);
487 mc
->execute
= get_field(val
, MCONTROL_EXECUTE
);
488 mc
->store
= get_field(val
, MCONTROL_STORE
);
489 mc
->load
= get_field(val
, MCONTROL_LOAD
);
490 // Assume we're here because of csrw.
497 if (state
.mcontrol
[state
.tselect
].dmode
&& !state
.dcsr
.cause
) {
500 if (state
.tselect
< state
.num_triggers
) {
501 state
.tdata2
[state
.tselect
] = val
;
505 state
.dcsr
.prv
= get_field(val
, DCSR_PRV
);
506 state
.dcsr
.step
= get_field(val
, DCSR_STEP
);
507 // TODO: ndreset and fullreset
508 state
.dcsr
.ebreakm
= get_field(val
, DCSR_EBREAKM
);
509 state
.dcsr
.ebreakh
= get_field(val
, DCSR_EBREAKH
);
510 state
.dcsr
.ebreaks
= get_field(val
, DCSR_EBREAKS
);
511 state
.dcsr
.ebreaku
= get_field(val
, DCSR_EBREAKU
);
512 state
.dcsr
.halt
= get_field(val
, DCSR_HALT
);
518 state
.dscratch
= val
;
523 reg_t
processor_t::get_csr(int which
)
525 uint32_t ctr_en
= -1;
526 if (state
.prv
< PRV_M
)
527 ctr_en
&= state
.mcounteren
;
528 if (state
.prv
< PRV_S
)
529 ctr_en
&= state
.scounteren
;
530 bool ctr_ok
= (ctr_en
>> (which
& 31)) & 1;
533 if (which
>= CSR_HPMCOUNTER3
&& which
<= CSR_HPMCOUNTER31
)
535 if (xlen
== 32 && which
>= CSR_HPMCOUNTER3H
&& which
<= CSR_HPMCOUNTER31H
)
538 if (which
>= CSR_MHPMCOUNTER3
&& which
<= CSR_MHPMCOUNTER31
)
540 if (xlen
== 32 && which
>= CSR_MHPMCOUNTER3H
&& which
<= CSR_MHPMCOUNTER31H
)
542 if (which
>= CSR_MHPMEVENT3
&& which
<= CSR_MHPMEVENT31
)
549 if (!supports_extension('F'))
554 if (!supports_extension('F'))
559 if (!supports_extension('F'))
561 return (state
.fflags
<< FSR_AEXC_SHIFT
) | (state
.frm
<< FSR_RD_SHIFT
);
565 return state
.minstret
;
569 return state
.minstret
;
573 return state
.minstret
>> 32;
575 case CSR_SCOUNTEREN
: return state
.scounteren
;
576 case CSR_MCOUNTEREN
: return state
.mcounteren
;
578 reg_t mask
= SSTATUS_SIE
| SSTATUS_SPIE
| SSTATUS_SPP
| SSTATUS_FS
579 | SSTATUS_XS
| SSTATUS_SUM
| SSTATUS_UXL
;
580 reg_t sstatus
= state
.mstatus
& mask
;
581 if ((sstatus
& SSTATUS_FS
) == SSTATUS_FS
||
582 (sstatus
& SSTATUS_XS
) == SSTATUS_XS
)
583 sstatus
|= (xlen
== 32 ? SSTATUS32_SD
: SSTATUS64_SD
);
586 case CSR_SIP
: return state
.mip
& state
.mideleg
;
587 case CSR_SIE
: return state
.mie
& state
.mideleg
;
588 case CSR_SEPC
: return state
.sepc
;
589 case CSR_SBADADDR
: return state
.sbadaddr
;
590 case CSR_STVEC
: return state
.stvec
;
593 return state
.scause
| ((state
.scause
>> (max_xlen
-1)) << (xlen
-1));
596 if (get_field(state
.mstatus
, MSTATUS_TVM
))
597 require_privilege(PRV_M
);
599 case CSR_SSCRATCH
: return state
.sscratch
;
600 case CSR_MSTATUS
: return state
.mstatus
;
601 case CSR_MIP
: return state
.mip
;
602 case CSR_MIE
: return state
.mie
;
603 case CSR_MEPC
: return state
.mepc
;
604 case CSR_MSCRATCH
: return state
.mscratch
;
605 case CSR_MCAUSE
: return state
.mcause
;
606 case CSR_MBADADDR
: return state
.mbadaddr
;
607 case CSR_MISA
: return isa
;
608 case CSR_MARCHID
: return 0;
609 case CSR_MIMPID
: return 0;
610 case CSR_MVENDORID
: return 0;
611 case CSR_MHARTID
: return id
;
612 case CSR_MTVEC
: return state
.mtvec
;
613 case CSR_MEDELEG
: return state
.medeleg
;
614 case CSR_MIDELEG
: return state
.mideleg
;
615 case CSR_TSELECT
: return state
.tselect
;
617 if (state
.tselect
< state
.num_triggers
) {
619 mcontrol_t
*mc
= &state
.mcontrol
[state
.tselect
];
620 v
= set_field(v
, MCONTROL_TYPE(xlen
), mc
->type
);
621 v
= set_field(v
, MCONTROL_DMODE(xlen
), mc
->dmode
);
622 v
= set_field(v
, MCONTROL_MASKMAX(xlen
), mc
->maskmax
);
623 v
= set_field(v
, MCONTROL_SELECT
, mc
->select
);
624 v
= set_field(v
, MCONTROL_TIMING
, mc
->timing
);
625 v
= set_field(v
, MCONTROL_ACTION
, mc
->action
);
626 v
= set_field(v
, MCONTROL_CHAIN
, mc
->chain
);
627 v
= set_field(v
, MCONTROL_MATCH
, mc
->match
);
628 v
= set_field(v
, MCONTROL_M
, mc
->m
);
629 v
= set_field(v
, MCONTROL_H
, mc
->h
);
630 v
= set_field(v
, MCONTROL_S
, mc
->s
);
631 v
= set_field(v
, MCONTROL_U
, mc
->u
);
632 v
= set_field(v
, MCONTROL_EXECUTE
, mc
->execute
);
633 v
= set_field(v
, MCONTROL_STORE
, mc
->store
);
634 v
= set_field(v
, MCONTROL_LOAD
, mc
->load
);
641 if (state
.tselect
< state
.num_triggers
) {
642 return state
.tdata2
[state
.tselect
];
647 case CSR_TDATA3
: return 0;
651 v
= set_field(v
, DCSR_XDEBUGVER
, 1);
652 v
= set_field(v
, DCSR_EBREAKM
, state
.dcsr
.ebreakm
);
653 v
= set_field(v
, DCSR_EBREAKH
, state
.dcsr
.ebreakh
);
654 v
= set_field(v
, DCSR_EBREAKS
, state
.dcsr
.ebreaks
);
655 v
= set_field(v
, DCSR_EBREAKU
, state
.dcsr
.ebreaku
);
656 v
= set_field(v
, DCSR_STOPCYCLE
, 0);
657 v
= set_field(v
, DCSR_STOPTIME
, 0);
658 v
= set_field(v
, DCSR_CAUSE
, state
.dcsr
.cause
);
659 v
= set_field(v
, DCSR_STEP
, state
.dcsr
.step
);
660 v
= set_field(v
, DCSR_PRV
, state
.dcsr
.prv
);
666 return state
.dscratch
;
668 throw trap_illegal_instruction(0);
671 reg_t
illegal_instruction(processor_t
* p
, insn_t insn
, reg_t pc
)
673 throw trap_illegal_instruction(0);
676 insn_func_t
processor_t::decode_insn(insn_t insn
)
678 // look up opcode in hash table
679 size_t idx
= insn
.bits() % OPCODE_CACHE_SIZE
;
680 insn_desc_t desc
= opcode_cache
[idx
];
682 if (unlikely(insn
.bits() != desc
.match
)) {
683 // fall back to linear search
684 insn_desc_t
* p
= &instructions
[0];
685 while ((insn
.bits() & p
->mask
) != p
->match
)
689 if (p
->mask
!= 0 && p
> &instructions
[0]) {
690 if (p
->match
!= (p
-1)->match
&& p
->match
!= (p
+1)->match
) {
691 // move to front of opcode list to reduce miss penalty
692 while (--p
>= &instructions
[0])
694 instructions
[0] = desc
;
698 opcode_cache
[idx
] = desc
;
699 opcode_cache
[idx
].match
= insn
.bits();
702 return xlen
== 64 ? desc
.rv64
: desc
.rv32
;
705 void processor_t::register_insn(insn_desc_t desc
)
707 instructions
.push_back(desc
);
710 void processor_t::build_opcode_map()
713 bool operator()(const insn_desc_t
& lhs
, const insn_desc_t
& rhs
) {
714 if (lhs
.match
== rhs
.match
)
715 return lhs
.mask
> rhs
.mask
;
716 return lhs
.match
> rhs
.match
;
719 std::sort(instructions
.begin(), instructions
.end(), cmp());
721 for (size_t i
= 0; i
< OPCODE_CACHE_SIZE
; i
++)
722 opcode_cache
[i
] = {0, 0, &illegal_instruction
, &illegal_instruction
};
725 void processor_t::register_extension(extension_t
* x
)
727 for (auto insn
: x
->get_instructions())
730 for (auto disasm_insn
: x
->get_disasms())
731 disassembler
->add_insn(disasm_insn
);
733 throw std::logic_error("only one extension may be registered");
735 x
->set_processor(this);
738 void processor_t::register_base_instructions()
740 #define DECLARE_INSN(name, match, mask) \
741 insn_bits_t name##_match = (match), name##_mask = (mask);
742 #include "encoding.h"
745 #define DEFINE_INSN(name) \
746 REGISTER_INSN(this, name, name##_match, name##_mask)
747 #include "insn_list.h"
750 register_insn({0, 0, &illegal_instruction
, &illegal_instruction
});
754 bool processor_t::load(reg_t addr
, size_t len
, uint8_t* bytes
)
760 memset(bytes
, 0, len
);
761 bytes
[0] = get_field(state
.mip
, MIP_MSIP
);
770 bool processor_t::store(reg_t addr
, size_t len
, const uint8_t* bytes
)
776 state
.mip
= set_field(state
.mip
, MIP_MSIP
, bytes
[0]);
785 void processor_t::trigger_updated()
788 mmu
->check_triggers_fetch
= false;
789 mmu
->check_triggers_load
= false;
790 mmu
->check_triggers_store
= false;
792 for (unsigned i
= 0; i
< state
.num_triggers
; i
++) {
793 if (state
.mcontrol
[i
].execute
) {
794 mmu
->check_triggers_fetch
= true;
796 if (state
.mcontrol
[i
].load
) {
797 mmu
->check_triggers_load
= true;
799 if (state
.mcontrol
[i
].store
) {
800 mmu
->check_triggers_store
= true;