riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "simif.h"
   8 #include "mmu.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18
  19 #undef STATE
  20 #define STATE state
  21
  22 processor_t::processor_t(const char* isa, simif_t* sim, uint32_t id,
  23         bool halt_on_reset)
  24   : debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
  25   halt_on_reset(halt_on_reset), last_pc(1), executions(1)
  26 {
  27   parse_isa_string(isa);
  28   register_base_instructions();
  29
  30   mmu = new mmu_t(sim, this);
  31
  32   disassembler = new disassembler_t(max_xlen);
  33   if (ext)
  34     for (auto disasm_insn : ext->get_disasms())
  35       disassembler->add_insn(disasm_insn);
  36
  37   reset();
  38 }
  39
  40 processor_t::~processor_t()
  41 {
  42 #ifdef RISCV_ENABLE_HISTOGRAM
  43   if (histogram_enabled)
  44   {
  45     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  46     for (auto it : pc_histogram)
  47       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  48   }
  49 #endif
  50
  51   delete mmu;
  52   delete disassembler;
  53 }
  54
  55 static void bad_isa_string(const char* isa)
  56 {
  57   fprintf(stderr, "error: bad --isa option %s\n", isa);
  58   abort();
  59 }
  60
  61 void processor_t::parse_isa_string(const char* str)
  62 {
  63   std::string lowercase, tmp;
  64   for (const char *r = str; *r; r++)
  65     lowercase += std::tolower(*r);
  66
  67   const char* p = lowercase.c_str();
  68   const char* all_subsets = "imafdqc";
  69
  70   max_xlen = 64;
  71   state.misa = reg_t(2) << 62;
  72
  73   if (strncmp(p, "rv32", 4) == 0)
  74     max_xlen = 32, state.misa = reg_t(1) << 30, p += 4;
  75   else if (strncmp(p, "rv64", 4) == 0)
  76     p += 4;
  77   else if (strncmp(p, "rv", 2) == 0)
  78     p += 2;
  79
  80   if (!*p) {
  81     p = "imafdc";
  82   } else if (*p == 'g') { // treat "G" as "IMAFD"
  83     tmp = std::string("imafd") + (p+1);
  84     p = &tmp[0];
  85   } else if (*p != 'i') {
  86     bad_isa_string(str);
  87   }
  88
  89   isa_string = "rv" + std::to_string(max_xlen) + p;
  90   state.misa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  91   state.misa |= 1L << ('u' - 'a'); // advertise support for user mode
  92
  93   while (*p) {
  94     state.misa |= 1L << (*p - 'a');
  95
  96     if (auto next = strchr(all_subsets, *p)) {
  97       all_subsets = next + 1;
  98       p++;
  99     } else if (*p == 'x') {
 100       const char* ext = p+1, *end = ext;
 101       while (islower(*end))
 102         end++;
 103       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 104       p = end;
 105     } else {
 106       bad_isa_string(str);
 107     }
 108   }
 109
 110   if (supports_extension('D') && !supports_extension('F'))
 111     bad_isa_string(str);
 112
 113   if (supports_extension('Q') && !supports_extension('D'))
 114     bad_isa_string(str);
 115
 116   if (supports_extension('Q') && max_xlen < 64)
 117     bad_isa_string(str);
 118
 119   max_isa = state.misa;
 120 }
 121
 122 void state_t::reset(reg_t max_isa)
 123 {
 124   memset(this, 0, sizeof(*this));
 125   misa = max_isa;
 126   prv = PRV_M;
 127   pc = DEFAULT_RSTVEC;
 128   tselect = 0;
 129   for (unsigned int i = 0; i < num_triggers; i++)
 130     mcontrol[i].type = 2;
 131 }
 132
 133 void processor_t::set_debug(bool value)
 134 {
 135   debug = value;
 136   if (ext)
 137     ext->set_debug(value);
 138 }
 139
 140 void processor_t::set_histogram(bool value)
 141 {
 142   histogram_enabled = value;
 143 #ifndef RISCV_ENABLE_HISTOGRAM
 144   if (value) {
 145     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 146     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 147   }
 148 #endif
 149 }
 150
 151 void processor_t::reset()
 152 {
 153   state.reset(max_isa);
 154   state.dcsr.halt = halt_on_reset;
 155   halt_on_reset = false;
 156   set_csr(CSR_MSTATUS, state.mstatus);
 157
 158   if (ext)
 159     ext->reset(); // reset the extension
 160
 161   if (sim)
 162     sim->proc_reset(id);
 163 }
 164
 165 // Count number of contiguous 0 bits starting from the LSB.
 166 static int ctz(reg_t val)
 167 {
 168   int res = 0;
 169   if (val)
 170     while ((val & 1) == 0)
 171       val >>= 1, res++;
 172   return res;
 173 }
 174
 175 void processor_t::take_interrupt(reg_t pending_interrupts)
 176 {
 177   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 178   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 179   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 180
 181   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 182   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 183   // M-ints have highest priority; consider S-ints only if no M-ints pending
 184   if (enabled_interrupts == 0)
 185     enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled;
 186
 187   if (state.dcsr.cause == 0 && enabled_interrupts) {
 188     // nonstandard interrupts have highest priority
 189     if (enabled_interrupts >> IRQ_M_EXT)
 190       enabled_interrupts = enabled_interrupts >> IRQ_M_EXT << IRQ_M_EXT;
 191     // external interrupts have next-highest priority
 192     else if (enabled_interrupts & (MIP_MEIP | MIP_SEIP))
 193       enabled_interrupts = enabled_interrupts & (MIP_MEIP | MIP_SEIP);
 194     // software interrupts have next-highest priority
 195     else if (enabled_interrupts & (MIP_MSIP | MIP_SSIP))
 196       enabled_interrupts = enabled_interrupts & (MIP_MSIP | MIP_SSIP);
 197     // timer interrupts have next-highest priority
 198     else if (enabled_interrupts & (MIP_MTIP | MIP_STIP))
 199       enabled_interrupts = enabled_interrupts & (MIP_MTIP | MIP_STIP);
 200     else
 201       abort();
 202
 203     throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
 204   }
 205 }
 206
 207 static int xlen_to_uxl(int xlen)
 208 {
 209   if (xlen == 32)
 210     return 1;
 211   if (xlen == 64)
 212     return 2;
 213   abort();
 214 }
 215
 216 reg_t processor_t::legalize_privilege(reg_t prv)
 217 {
 218   assert(prv <= PRV_M);
 219
 220   if (!supports_extension('U'))
 221     return PRV_M;
 222
 223   if (prv == PRV_H || !supports_extension('S'))
 224     return PRV_U;
 225
 226   return prv;
 227 }
 228
 229 void processor_t::set_privilege(reg_t prv)
 230 {
 231   mmu->flush_tlb();
 232   state.prv = legalize_privilege(prv);
 233 }
 234
 235 void processor_t::enter_debug_mode(uint8_t cause)
 236 {
 237   state.dcsr.cause = cause;
 238   state.dcsr.prv = state.prv;
 239   set_privilege(PRV_M);
 240   state.dpc = state.pc;
 241   state.pc = DEBUG_ROM_ENTRY;
 242 }
 243
 244 void processor_t::take_trap(trap_t& t, reg_t epc)
 245 {
 246   if (debug) {
 247     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 248             id, t.name(), epc);
 249     if (t.has_tval())
 250       fprintf(stderr, "core %3d:           tval 0x%016" PRIx64 "\n", id,
 251           t.get_tval());
 252   }
 253
 254   if (state.dcsr.cause) {
 255     if (t.cause() == CAUSE_BREAKPOINT) {
 256       state.pc = DEBUG_ROM_ENTRY;
 257     } else {
 258       state.pc = DEBUG_ROM_TVEC;
 259     }
 260     return;
 261   }
 262
 263   if (t.cause() == CAUSE_BREAKPOINT && (
 264               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 265               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 266               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 267     enter_debug_mode(DCSR_CAUSE_SWBP);
 268     return;
 269   }
 270
 271   // by default, trap to M-mode, unless delegated to S-mode
 272   reg_t bit = t.cause();
 273   reg_t deleg = state.medeleg;
 274   bool interrupt = (bit & ((reg_t)1 << (max_xlen-1))) != 0;
 275   if (interrupt)
 276     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 277   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 278     // handle the trap in S-mode
 279     state.pc = state.stvec;
 280     state.scause = t.cause();
 281     state.sepc = epc;
 282     state.stval = t.get_tval();
 283
 284     reg_t s = state.mstatus;
 285     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
 286     s = set_field(s, MSTATUS_SPP, state.prv);
 287     s = set_field(s, MSTATUS_SIE, 0);
 288     set_csr(CSR_MSTATUS, s);
 289     set_privilege(PRV_S);
 290   } else {
 291     reg_t vector = (state.mtvec & 1) && interrupt ? 4*bit : 0;
 292     state.pc = (state.mtvec & ~(reg_t)1) + vector;
 293     state.mepc = epc;
 294     state.mcause = t.cause();
 295     state.mtval = t.get_tval();
 296
 297     reg_t s = state.mstatus;
 298     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
 299     s = set_field(s, MSTATUS_MPP, state.prv);
 300     s = set_field(s, MSTATUS_MIE, 0);
 301     set_csr(CSR_MSTATUS, s);
 302     set_privilege(PRV_M);
 303   }
 304 }
 305
 306 void processor_t::disasm(insn_t insn)
 307 {
 308   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 309   if (last_pc != state.pc || last_bits != bits) {
 310     if (executions != 1) {
 311       fprintf(stderr, "core %3d: Executed %" PRIx64 " times\n", id, executions);
 312     }
 313
 314     fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 315             id, state.pc, bits, disassembler->disassemble(insn).c_str());
 316     last_pc = state.pc;
 317     last_bits = bits;
 318     executions = 1;
 319   } else {
 320     executions++;
 321   }
 322 }
 323
 324 int processor_t::paddr_bits()
 325 {
 326   assert(xlen == max_xlen);
 327   return max_xlen == 64 ? 50 : 34;
 328 }
 329
 330 void processor_t::set_csr(int which, reg_t val)
 331 {
 332   val = zext_xlen(val);
 333   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 334   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 335   switch (which)
 336   {
 337     case CSR_FFLAGS:
 338       dirty_fp_state;
 339       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 340       break;
 341     case CSR_FRM:
 342       dirty_fp_state;
 343       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 344       break;
 345     case CSR_FCSR:
 346       dirty_fp_state;
 347       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 348       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 349       break;
 350     case CSR_MSTATUS: {
 351       if ((val ^ state.mstatus) &
 352           (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR))
 353         mmu->flush_tlb();
 354
 355       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 356                  | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM
 357                  | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM
 358                  | MSTATUS_TSR | MSTATUS_UXL | MSTATUS_SXL |
 359                  (ext ? MSTATUS_XS : 0);
 360
 361       reg_t requested_mpp = legalize_privilege(get_field(val, MSTATUS_MPP));
 362       state.mstatus = set_field(state.mstatus, MSTATUS_MPP, requested_mpp);
 363       if (supports_extension('S'))
 364         mask |= MSTATUS_SPP;
 365
 366       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 367
 368       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 369       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 370       if (max_xlen == 32)
 371         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 372       else
 373         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 374
 375       state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
 376       state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
 377       state.mstatus = set_field(state.mstatus, MSTATUS_SXL, xlen_to_uxl(max_xlen));
 378       // U-XLEN == S-XLEN == M-XLEN
 379       xlen = max_xlen;
 380       break;
 381     }
 382     case CSR_MIP: {
 383       reg_t mask = MIP_SSIP | MIP_STIP;
 384       state.mip = (state.mip & ~mask) | (val & mask);
 385       break;
 386     }
 387     case CSR_MIE:
 388       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 389       break;
 390     case CSR_MIDELEG:
 391       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 392       break;
 393     case CSR_MEDELEG: {
 394       reg_t mask =
 395         (1 << CAUSE_MISALIGNED_FETCH) |
 396         (1 << CAUSE_BREAKPOINT) |
 397         (1 << CAUSE_USER_ECALL) |
 398         (1 << CAUSE_FETCH_PAGE_FAULT) |
 399         (1 << CAUSE_LOAD_PAGE_FAULT) |
 400         (1 << CAUSE_STORE_PAGE_FAULT);
 401       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 402       break;
 403     }
 404     case CSR_MINSTRET:
 405     case CSR_MCYCLE:
 406       if (xlen == 32)
 407         state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
 408       else
 409         state.minstret = val;
 410       // The ISA mandates that if an instruction writes instret, the write
 411       // takes precedence over the increment to instret.  However, Spike
 412       // unconditionally increments instret after executing an instruction.
 413       // Correct for this artifact by decrementing instret here.
 414       state.minstret--;
 415       break;
 416     case CSR_MINSTRETH:
 417     case CSR_MCYCLEH:
 418       state.minstret = (val << 32) | (state.minstret << 32 >> 32);
 419       state.minstret--; // See comment above.
 420       break;
 421     case CSR_SCOUNTEREN:
 422       state.scounteren = val;
 423       break;
 424     case CSR_MCOUNTEREN:
 425       state.mcounteren = val;
 426       break;
 427     case CSR_SSTATUS: {
 428       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 429                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR;
 430       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 431     }
 432     case CSR_SIP: {
 433       reg_t mask = MIP_SSIP & state.mideleg;
 434       return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
 435     }
 436     case CSR_SIE:
 437       return set_csr(CSR_MIE,
 438                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 439     case CSR_SATP: {
 440       mmu->flush_tlb();
 441       if (max_xlen == 32)
 442         state.satp = val & (SATP32_PPN | SATP32_MODE);
 443       if (max_xlen == 64 && (get_field(val, SATP64_MODE) == SATP_MODE_OFF ||
 444                              get_field(val, SATP64_MODE) == SATP_MODE_SV39 ||
 445                              get_field(val, SATP64_MODE) == SATP_MODE_SV48))
 446         state.satp = val & (SATP64_PPN | SATP64_MODE);
 447       break;
 448     }
 449     case CSR_SEPC: state.sepc = val & ~(reg_t)1; break;
 450     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 451     case CSR_SSCRATCH: state.sscratch = val; break;
 452     case CSR_SCAUSE: state.scause = val; break;
 453     case CSR_STVAL: state.stval = val; break;
 454     case CSR_MEPC: state.mepc = val & ~(reg_t)1; break;
 455     case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break;
 456     case CSR_MSCRATCH: state.mscratch = val; break;
 457     case CSR_MCAUSE: state.mcause = val; break;
 458     case CSR_MTVAL: state.mtval = val; break;
 459     case CSR_MISA: {
 460       // the write is ignored if increasing IALIGN would misalign the PC
 461       if (!(val & (1L << ('C' - 'A'))) && (state.pc & 2))
 462         break;
 463
 464       if (!(val & (1L << ('F' - 'A'))))
 465         val &= ~(1L << ('D' - 'A'));
 466
 467       // allow MAFDC bits in MISA to be modified
 468       reg_t mask = 0;
 469       mask |= 1L << ('M' - 'A');
 470       mask |= 1L << ('A' - 'A');
 471       mask |= 1L << ('F' - 'A');
 472       mask |= 1L << ('D' - 'A');
 473       mask |= 1L << ('C' - 'A');
 474       mask &= max_isa;
 475
 476       state.misa = (val & mask) | (state.misa & ~mask);
 477       break;
 478     }
 479     case CSR_TSELECT:
 480       if (val < state.num_triggers) {
 481         state.tselect = val;
 482       }
 483       break;
 484     case CSR_TDATA1:
 485       {
 486         mcontrol_t *mc = &state.mcontrol[state.tselect];
 487         if (mc->dmode && !state.dcsr.cause) {
 488           break;
 489         }
 490         mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
 491         mc->select = get_field(val, MCONTROL_SELECT);
 492         mc->timing = get_field(val, MCONTROL_TIMING);
 493         mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
 494         mc->chain = get_field(val, MCONTROL_CHAIN);
 495         mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
 496         mc->m = get_field(val, MCONTROL_M);
 497         mc->h = get_field(val, MCONTROL_H);
 498         mc->s = get_field(val, MCONTROL_S);
 499         mc->u = get_field(val, MCONTROL_U);
 500         mc->execute = get_field(val, MCONTROL_EXECUTE);
 501         mc->store = get_field(val, MCONTROL_STORE);
 502         mc->load = get_field(val, MCONTROL_LOAD);
 503         // Assume we're here because of csrw.
 504         if (mc->execute)
 505           mc->timing = 0;
 506         trigger_updated();
 507       }
 508       break;
 509     case CSR_TDATA2:
 510       if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) {
 511         break;
 512       }
 513       if (state.tselect < state.num_triggers) {
 514         state.tdata2[state.tselect] = val;
 515       }
 516       break;
 517     case CSR_DCSR:
 518       state.dcsr.prv = get_field(val, DCSR_PRV);
 519       state.dcsr.step = get_field(val, DCSR_STEP);
 520       // TODO: ndreset and fullreset
 521       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 522       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 523       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 524       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 525       state.dcsr.halt = get_field(val, DCSR_HALT);
 526       break;
 527     case CSR_DPC:
 528       state.dpc = val & ~(reg_t)1;
 529       break;
 530     case CSR_DSCRATCH:
 531       state.dscratch = val;
 532       break;
 533   }
 534 }
 535
 536 reg_t processor_t::get_csr(int which)
 537 {
 538   uint32_t ctr_en = -1;
 539   if (state.prv < PRV_M)
 540     ctr_en &= state.mcounteren;
 541   if (state.prv < PRV_S)
 542     ctr_en &= state.scounteren;
 543   bool ctr_ok = (ctr_en >> (which & 31)) & 1;
 544
 545   if (ctr_ok) {
 546     if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31)
 547       return 0;
 548     if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H)
 549       return 0;
 550   }
 551   if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
 552     return 0;
 553   if (xlen == 32 && which >= CSR_MHPMCOUNTER3H && which <= CSR_MHPMCOUNTER31H)
 554     return 0;
 555   if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31)
 556     return 0;
 557
 558   switch (which)
 559   {
 560     case CSR_FFLAGS:
 561       require_fp;
 562       if (!supports_extension('F'))
 563         break;
 564       return state.fflags;
 565     case CSR_FRM:
 566       require_fp;
 567       if (!supports_extension('F'))
 568         break;
 569       return state.frm;
 570     case CSR_FCSR:
 571       require_fp;
 572       if (!supports_extension('F'))
 573         break;
 574       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 575     case CSR_INSTRET:
 576     case CSR_CYCLE:
 577       if (ctr_ok)
 578         return state.minstret;
 579       break;
 580     case CSR_MINSTRET:
 581     case CSR_MCYCLE:
 582       return state.minstret;
 583     case CSR_INSTRETH:
 584     case CSR_CYCLEH:
 585       if (ctr_ok && xlen == 32)
 586         return state.minstret >> 32;
 587       break;
 588     case CSR_MINSTRETH:
 589     case CSR_MCYCLEH:
 590       if (xlen == 32)
 591         return state.minstret >> 32;
 592       break;
 593     case CSR_SCOUNTEREN: return state.scounteren;
 594     case CSR_MCOUNTEREN: return state.mcounteren;
 595     case CSR_SSTATUS: {
 596       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 597                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_UXL;
 598       reg_t sstatus = state.mstatus & mask;
 599       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 600           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 601         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 602       return sstatus;
 603     }
 604     case CSR_SIP: return state.mip & state.mideleg;
 605     case CSR_SIE: return state.mie & state.mideleg;
 606     case CSR_SEPC: return state.sepc & pc_alignment_mask();
 607     case CSR_STVAL: return state.stval;
 608     case CSR_STVEC: return state.stvec;
 609     case CSR_SCAUSE:
 610       if (max_xlen > xlen)
 611         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 612       return state.scause;
 613     case CSR_SATP:
 614       if (get_field(state.mstatus, MSTATUS_TVM))
 615         require_privilege(PRV_M);
 616       return state.satp;
 617     case CSR_SSCRATCH: return state.sscratch;
 618     case CSR_MSTATUS: return state.mstatus;
 619     case CSR_MIP: return state.mip;
 620     case CSR_MIE: return state.mie;
 621     case CSR_MEPC: return state.mepc & pc_alignment_mask();
 622     case CSR_MSCRATCH: return state.mscratch;
 623     case CSR_MCAUSE: return state.mcause;
 624     case CSR_MTVAL: return state.mtval;
 625     case CSR_MISA: return state.misa;
 626     case CSR_MARCHID: return 0;
 627     case CSR_MIMPID: return 0;
 628     case CSR_MVENDORID: return 0;
 629     case CSR_MHARTID: return id;
 630     case CSR_MTVEC: return state.mtvec;
 631     case CSR_MEDELEG: return state.medeleg;
 632     case CSR_MIDELEG: return state.mideleg;
 633     case CSR_TSELECT: return state.tselect;
 634     case CSR_TDATA1:
 635       if (state.tselect < state.num_triggers) {
 636         reg_t v = 0;
 637         mcontrol_t *mc = &state.mcontrol[state.tselect];
 638         v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
 639         v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
 640         v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
 641         v = set_field(v, MCONTROL_SELECT, mc->select);
 642         v = set_field(v, MCONTROL_TIMING, mc->timing);
 643         v = set_field(v, MCONTROL_ACTION, mc->action);
 644         v = set_field(v, MCONTROL_CHAIN, mc->chain);
 645         v = set_field(v, MCONTROL_MATCH, mc->match);
 646         v = set_field(v, MCONTROL_M, mc->m);
 647         v = set_field(v, MCONTROL_H, mc->h);
 648         v = set_field(v, MCONTROL_S, mc->s);
 649         v = set_field(v, MCONTROL_U, mc->u);
 650         v = set_field(v, MCONTROL_EXECUTE, mc->execute);
 651         v = set_field(v, MCONTROL_STORE, mc->store);
 652         v = set_field(v, MCONTROL_LOAD, mc->load);
 653         return v;
 654       } else {
 655         return 0;
 656       }
 657       break;
 658     case CSR_TDATA2:
 659       if (state.tselect < state.num_triggers) {
 660         return state.tdata2[state.tselect];
 661       } else {
 662         return 0;
 663       }
 664       break;
 665     case CSR_TDATA3: return 0;
 666     case CSR_DCSR:
 667       {
 668         uint32_t v = 0;
 669         v = set_field(v, DCSR_XDEBUGVER, 1);
 670         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 671         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 672         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 673         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 674         v = set_field(v, DCSR_STOPCYCLE, 0);
 675         v = set_field(v, DCSR_STOPTIME, 0);
 676         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 677         v = set_field(v, DCSR_STEP, state.dcsr.step);
 678         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 679         return v;
 680       }
 681     case CSR_DPC:
 682       return state.dpc & pc_alignment_mask();
 683     case CSR_DSCRATCH:
 684       return state.dscratch;
 685   }
 686   throw trap_illegal_instruction(0);
 687 }
 688
 689 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 690 {
 691   throw trap_illegal_instruction(0);
 692 }
 693
 694 insn_func_t processor_t::decode_insn(insn_t insn)
 695 {
 696   // look up opcode in hash table
 697   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 698   insn_desc_t desc = opcode_cache[idx];
 699
 700   if (unlikely(insn.bits() != desc.match)) {
 701     // fall back to linear search
 702     insn_desc_t* p = &instructions[0];
 703     while ((insn.bits() & p->mask) != p->match)
 704       p++;
 705     desc = *p;
 706
 707     if (p->mask != 0 && p > &instructions[0]) {
 708       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 709         // move to front of opcode list to reduce miss penalty
 710         while (--p >= &instructions[0])
 711           *(p+1) = *p;
 712         instructions[0] = desc;
 713       }
 714     }
 715
 716     opcode_cache[idx] = desc;
 717     opcode_cache[idx].match = insn.bits();
 718   }
 719
 720   return xlen == 64 ? desc.rv64 : desc.rv32;
 721 }
 722
 723 void processor_t::register_insn(insn_desc_t desc)
 724 {
 725   instructions.push_back(desc);
 726 }
 727
 728 void processor_t::build_opcode_map()
 729 {
 730   struct cmp {
 731     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 732       if (lhs.match == rhs.match)
 733         return lhs.mask > rhs.mask;
 734       return lhs.match > rhs.match;
 735     }
 736   };
 737   std::sort(instructions.begin(), instructions.end(), cmp());
 738
 739   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 740     opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
 741 }
 742
 743 void processor_t::register_extension(extension_t* x)
 744 {
 745   for (auto insn : x->get_instructions())
 746     register_insn(insn);
 747   build_opcode_map();
 748   for (auto disasm_insn : x->get_disasms())
 749     disassembler->add_insn(disasm_insn);
 750   if (ext != NULL)
 751     throw std::logic_error("only one extension may be registered");
 752   ext = x;
 753   x->set_processor(this);
 754 }
 755
 756 void processor_t::register_base_instructions()
 757 {
 758   #define DECLARE_INSN(name, match, mask) \
 759     insn_bits_t name##_match = (match), name##_mask = (mask);
 760   #include "encoding.h"
 761   #undef DECLARE_INSN
 762
 763   #define DEFINE_INSN(name) \
 764     REGISTER_INSN(this, name, name##_match, name##_mask)
 765   #include "insn_list.h"
 766   #undef DEFINE_INSN
 767
 768   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 769   build_opcode_map();
 770 }
 771
 772 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 773 {
 774   switch (addr)
 775   {
 776     case 0:
 777       if (len <= 4) {
 778         memset(bytes, 0, len);
 779         bytes[0] = get_field(state.mip, MIP_MSIP);
 780         return true;
 781       }
 782       break;
 783   }
 784
 785   return false;
 786 }
 787
 788 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 789 {
 790   switch (addr)
 791   {
 792     case 0:
 793       if (len <= 4) {
 794         state.mip = set_field(state.mip, MIP_MSIP, bytes[0]);
 795         return true;
 796       }
 797       break;
 798   }
 799
 800   return false;
 801 }
 802
 803 void processor_t::trigger_updated()
 804 {
 805   mmu->flush_tlb();
 806   mmu->check_triggers_fetch = false;
 807   mmu->check_triggers_load = false;
 808   mmu->check_triggers_store = false;
 809
 810   for (unsigned i = 0; i < state.num_triggers; i++) {
 811     if (state.mcontrol[i].execute) {
 812       mmu->check_triggers_fetch = true;
 813     }
 814     if (state.mcontrol[i].load) {
 815       mmu->check_triggers_load = true;
 816     }
 817     if (state.mcontrol[i].store) {
 818       mmu->check_triggers_store = true;
 819     }
 820   }
 821 }