e2f44b5a43d0a2e3202bd5e71a01492b8924b3bf
1 // See LICENSE for license details.
11 #include "gdbserver.h"
24 processor_t::processor_t(const char* isa
, sim_t
* sim
, uint32_t id
,
26 : debug(false), sim(sim
), ext(NULL
), disassembler(new disassembler_t
),
27 id(id
), run(false), halt_on_reset(halt_on_reset
)
29 parse_isa_string(isa
);
31 mmu
= new mmu_t(sim
, this);
35 register_base_instructions();
38 processor_t::~processor_t()
40 #ifdef RISCV_ENABLE_HISTOGRAM
41 if (histogram_enabled
)
43 fprintf(stderr
, "PC Histogram size:%zu\n", pc_histogram
.size());
44 for (auto it
: pc_histogram
)
45 fprintf(stderr
, "%0" PRIx64
" %" PRIu64
"\n", it
.first
, it
.second
);
53 static void bad_isa_string(const char* isa
)
55 fprintf(stderr
, "error: bad --isa option %s\n", isa
);
59 void processor_t::parse_isa_string(const char* str
)
61 std::string lowercase
, tmp
;
62 for (const char *r
= str
; *r
; r
++)
63 lowercase
+= std::tolower(*r
);
65 const char* p
= lowercase
.c_str();
66 const char* all_subsets
= "imafdc";
71 if (strncmp(p
, "rv32", 4) == 0)
72 max_xlen
= 32, isa
= reg_t(1) << 30, p
+= 4;
73 else if (strncmp(p
, "rv64", 4) == 0)
75 else if (strncmp(p
, "rv", 2) == 0)
80 } else if (*p
== 'g') { // treat "G" as "IMAFD"
81 tmp
= std::string("imafd") + (p
+1);
83 } else if (*p
!= 'i') {
87 isa_string
= "rv" + std::to_string(max_xlen
) + p
;
88 isa
|= 1L << ('s' - 'a'); // advertise support for supervisor mode
91 isa
|= 1L << (*p
- 'a');
93 if (auto next
= strchr(all_subsets
, *p
)) {
94 all_subsets
= next
+ 1;
96 } else if (*p
== 'x') {
97 const char* ext
= p
+1, *end
= ext
;
100 register_extension(find_extension(std::string(ext
, end
- ext
).c_str())());
107 if (supports_extension('D') && !supports_extension('F'))
110 // advertise support for supervisor and user modes
111 isa
|= 1L << ('s' - 'a');
112 isa
|= 1L << ('u' - 'a');
115 void state_t::reset()
117 memset(this, 0, sizeof(*this));
120 mtvec
= DEFAULT_MTVEC
;
121 load_reservation
= -1;
124 void processor_t::set_debug(bool value
)
128 ext
->set_debug(value
);
131 void processor_t::set_histogram(bool value
)
133 histogram_enabled
= value
;
134 #ifndef RISCV_ENABLE_HISTOGRAM
136 fprintf(stderr
, "PC Histogram support has not been properly enabled;");
137 fprintf(stderr
, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
142 void processor_t::reset(bool value
)
149 state
.dcsr
.halt
= halt_on_reset
;
150 halt_on_reset
= false;
151 set_csr(CSR_MSTATUS
, state
.mstatus
);
154 ext
->reset(); // reset the extension
157 void processor_t::raise_interrupt(reg_t which
)
159 throw trap_t(((reg_t
)1 << (max_xlen
-1)) | which
);
162 static int ctz(reg_t val
)
166 while ((val
& 1) == 0)
171 void processor_t::take_interrupt()
173 reg_t pending_interrupts
= state
.mip
& state
.mie
;
175 reg_t mie
= get_field(state
.mstatus
, MSTATUS_MIE
);
176 reg_t m_enabled
= state
.prv
< PRV_M
|| (state
.prv
== PRV_M
&& mie
);
177 reg_t enabled_interrupts
= pending_interrupts
& ~state
.mideleg
& -m_enabled
;
179 reg_t sie
= get_field(state
.mstatus
, MSTATUS_SIE
);
180 reg_t s_enabled
= state
.prv
< PRV_S
|| (state
.prv
== PRV_S
&& sie
);
181 enabled_interrupts
|= pending_interrupts
& state
.mideleg
& -s_enabled
;
183 if (enabled_interrupts
)
184 raise_interrupt(ctz(enabled_interrupts
));
187 static bool validate_priv(reg_t priv
)
189 return priv
== PRV_U
|| priv
== PRV_S
|| priv
== PRV_M
;
192 void processor_t::set_privilege(reg_t prv
)
194 assert(validate_priv(prv
));
199 void processor_t::enter_debug_mode(uint8_t cause
)
201 state
.dcsr
.cause
= cause
;
202 state
.dcsr
.prv
= state
.prv
;
203 set_privilege(PRV_M
);
204 state
.dpc
= state
.pc
;
205 state
.pc
= DEBUG_ROM_START
;
206 //debug = true; // TODO
209 void processor_t::take_trap(trap_t
& t
, reg_t epc
)
212 fprintf(stderr
, "core %3d: exception %s, epc 0x%016" PRIx64
"\n",
215 fprintf(stderr
, "core %3d: badaddr 0x%016" PRIx64
"\n", id
,
219 if (t
.cause() == CAUSE_BREAKPOINT
&& (
220 (state
.prv
== PRV_M
&& state
.dcsr
.ebreakm
) ||
221 (state
.prv
== PRV_H
&& state
.dcsr
.ebreakh
) ||
222 (state
.prv
== PRV_S
&& state
.dcsr
.ebreaks
) ||
223 (state
.prv
== PRV_U
&& state
.dcsr
.ebreaku
))) {
224 enter_debug_mode(DCSR_CAUSE_SWBP
);
228 if (state
.dcsr
.cause
) {
229 state
.pc
= DEBUG_ROM_EXCEPTION
;
233 // by default, trap to M-mode, unless delegated to S-mode
234 reg_t bit
= t
.cause();
235 reg_t deleg
= state
.medeleg
;
236 if (bit
& ((reg_t
)1 << (max_xlen
-1)))
237 deleg
= state
.mideleg
, bit
&= ~((reg_t
)1 << (max_xlen
-1));
238 if (state
.prv
<= PRV_S
&& bit
< max_xlen
&& ((deleg
>> bit
) & 1)) {
239 // handle the trap in S-mode
240 state
.pc
= state
.stvec
;
241 state
.scause
= t
.cause();
244 state
.sbadaddr
= t
.get_badaddr();
246 reg_t s
= state
.mstatus
;
247 s
= set_field(s
, MSTATUS_SPIE
, get_field(s
, MSTATUS_UIE
<< state
.prv
));
248 s
= set_field(s
, MSTATUS_SPP
, state
.prv
);
249 s
= set_field(s
, MSTATUS_SIE
, 0);
250 set_csr(CSR_MSTATUS
, s
);
251 set_privilege(PRV_S
);
253 state
.pc
= state
.mtvec
;
255 state
.mcause
= t
.cause();
257 state
.mbadaddr
= t
.get_badaddr();
259 reg_t s
= state
.mstatus
;
260 s
= set_field(s
, MSTATUS_MPIE
, get_field(s
, MSTATUS_UIE
<< state
.prv
));
261 s
= set_field(s
, MSTATUS_MPP
, state
.prv
);
262 s
= set_field(s
, MSTATUS_MIE
, 0);
263 set_csr(CSR_MSTATUS
, s
);
264 set_privilege(PRV_M
);
267 yield_load_reservation();
270 void processor_t::disasm(insn_t insn
)
272 uint64_t bits
= insn
.bits() & ((1ULL << (8 * insn_length(insn
.bits()))) - 1);
273 fprintf(stderr
, "core %3d: 0x%016" PRIx64
" (0x%08" PRIx64
") %s\n",
274 id
, state
.pc
, bits
, disassembler
->disassemble(insn
).c_str());
277 static bool validate_vm(int max_xlen
, reg_t vm
)
279 if (max_xlen
== 64 && (vm
== VM_SV39
|| vm
== VM_SV48
))
281 if (max_xlen
== 32 && vm
== VM_SV32
)
283 return vm
== VM_MBARE
;
286 int processor_t::paddr_bits()
288 assert(xlen
== max_xlen
);
289 return max_xlen
== 64 ? 50 : 34;
292 void processor_t::set_csr(int which
, reg_t val
)
294 val
= zext_xlen(val
);
295 reg_t delegable_ints
= MIP_SSIP
| MIP_STIP
| MIP_SEIP
| (1 << IRQ_COP
);
296 reg_t all_ints
= delegable_ints
| MIP_MSIP
| MIP_MTIP
;
301 state
.fflags
= val
& (FSR_AEXC
>> FSR_AEXC_SHIFT
);
305 state
.frm
= val
& (FSR_RD
>> FSR_RD_SHIFT
);
309 state
.fflags
= (val
& FSR_AEXC
) >> FSR_AEXC_SHIFT
;
310 state
.frm
= (val
& FSR_RD
) >> FSR_RD_SHIFT
;
313 if ((val
^ state
.mstatus
) &
314 (MSTATUS_VM
| MSTATUS_MPP
| MSTATUS_MPRV
| MSTATUS_PUM
))
317 reg_t mask
= MSTATUS_SIE
| MSTATUS_SPIE
| MSTATUS_MIE
| MSTATUS_MPIE
318 | MSTATUS_SPP
| MSTATUS_FS
| MSTATUS_MPRV
| MSTATUS_PUM
319 | (ext
? MSTATUS_XS
: 0);
321 if (validate_vm(max_xlen
, get_field(val
, MSTATUS_VM
)))
323 if (validate_priv(get_field(val
, MSTATUS_MPP
)))
326 state
.mstatus
= (state
.mstatus
& ~mask
) | (val
& mask
);
328 bool dirty
= (state
.mstatus
& MSTATUS_FS
) == MSTATUS_FS
;
329 dirty
|= (state
.mstatus
& MSTATUS_XS
) == MSTATUS_XS
;
331 state
.mstatus
= set_field(state
.mstatus
, MSTATUS32_SD
, dirty
);
333 state
.mstatus
= set_field(state
.mstatus
, MSTATUS64_SD
, dirty
);
335 // spike supports the notion of xlen < max_xlen, but current priv spec
336 // doesn't provide a mechanism to run RV32 software on an RV64 machine
341 reg_t mask
= MIP_SSIP
| MIP_STIP
;
342 state
.mip
= (state
.mip
& ~mask
) | (val
& mask
);
346 state
.mie
= (state
.mie
& ~all_ints
) | (val
& all_ints
);
349 state
.mideleg
= (state
.mideleg
& ~delegable_ints
) | (val
& delegable_ints
);
353 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
354 #include "encoding.h"
356 state
.medeleg
= (state
.medeleg
& ~mask
) | (val
& mask
);
359 case CSR_MUCOUNTEREN
:
360 state
.mucounteren
= val
& 7;
362 case CSR_MSCOUNTEREN
:
363 state
.mscounteren
= val
& 7;
366 reg_t mask
= SSTATUS_SIE
| SSTATUS_SPIE
| SSTATUS_SPP
| SSTATUS_FS
367 | SSTATUS_XS
| SSTATUS_PUM
;
368 return set_csr(CSR_MSTATUS
, (state
.mstatus
& ~mask
) | (val
& mask
));
371 return set_csr(CSR_MIP
,
372 (state
.mip
& ~state
.mideleg
) | (val
& state
.mideleg
));
374 return set_csr(CSR_MIE
,
375 (state
.mie
& ~state
.mideleg
) | (val
& state
.mideleg
));
377 // upper bits of sptbr are the ASID; we only support ASID = 0
378 state
.sptbr
= val
& (((reg_t
)1 << (paddr_bits() - PGSHIFT
)) - 1);
381 case CSR_SEPC
: state
.sepc
= val
; break;
382 case CSR_STVEC
: state
.stvec
= val
>> 2 << 2; break;
383 case CSR_SSCRATCH
: state
.sscratch
= val
; break;
384 case CSR_SCAUSE
: state
.scause
= val
; break;
385 case CSR_SBADADDR
: state
.sbadaddr
= val
; break;
386 case CSR_MEPC
: state
.mepc
= val
; break;
387 case CSR_MTVEC
: state
.mtvec
= val
>> 2 << 2; break;
388 case CSR_MSCRATCH
: state
.mscratch
= val
; break;
389 case CSR_MCAUSE
: state
.mcause
= val
; break;
390 case CSR_MBADADDR
: state
.mbadaddr
= val
; break;
392 state
.dcsr
.prv
= get_field(val
, DCSR_PRV
);
393 state
.dcsr
.step
= get_field(val
, DCSR_STEP
);
394 // TODO: ndreset and fullreset
395 state
.dcsr
.ebreakm
= get_field(val
, DCSR_EBREAKM
);
396 state
.dcsr
.ebreakh
= get_field(val
, DCSR_EBREAKH
);
397 state
.dcsr
.ebreaks
= get_field(val
, DCSR_EBREAKS
);
398 state
.dcsr
.ebreaku
= get_field(val
, DCSR_EBREAKU
);
399 state
.dcsr
.halt
= get_field(val
, DCSR_HALT
);
405 state
.dscratch
= val
;
410 reg_t
processor_t::get_csr(int which
)
416 if (!supports_extension('F'))
421 if (!supports_extension('F'))
426 if (!supports_extension('F'))
428 return (state
.fflags
<< FSR_AEXC_SHIFT
) | (state
.frm
<< FSR_RD_SHIFT
);
432 if ((state
.mucounteren
>> (which
& (xlen
-1))) & 1)
433 return get_csr(which
+ (CSR_MCYCLE
- CSR_CYCLE
));
438 if ((state
.mscounteren
>> (which
& (xlen
-1))) & 1)
439 return get_csr(which
+ (CSR_MCYCLE
- CSR_SCYCLE
));
441 case CSR_MUCOUNTEREN
: return state
.mucounteren
;
442 case CSR_MSCOUNTEREN
: return state
.mscounteren
;
443 case CSR_MUCYCLE_DELTA
: return 0;
444 case CSR_MUTIME_DELTA
: return 0;
445 case CSR_MUINSTRET_DELTA
: return 0;
446 case CSR_MSCYCLE_DELTA
: return 0;
447 case CSR_MSTIME_DELTA
: return 0;
448 case CSR_MSINSTRET_DELTA
: return 0;
449 case CSR_MUCYCLE_DELTAH
: if (xlen
> 32) break; else return 0;
450 case CSR_MUTIME_DELTAH
: if (xlen
> 32) break; else return 0;
451 case CSR_MUINSTRET_DELTAH
: if (xlen
> 32) break; else return 0;
452 case CSR_MSCYCLE_DELTAH
: if (xlen
> 32) break; else return 0;
453 case CSR_MSTIME_DELTAH
: if (xlen
> 32) break; else return 0;
454 case CSR_MSINSTRET_DELTAH
: if (xlen
> 32) break; else return 0;
455 case CSR_MCYCLE
: return state
.minstret
;
456 case CSR_MINSTRET
: return state
.minstret
;
457 case CSR_MCYCLEH
: if (xlen
> 32) break; else return state
.minstret
>> 32;
458 case CSR_MINSTRETH
: if (xlen
> 32) break; else return state
.minstret
>> 32;
460 reg_t mask
= SSTATUS_SIE
| SSTATUS_SPIE
| SSTATUS_SPP
| SSTATUS_FS
461 | SSTATUS_XS
| SSTATUS_PUM
;
462 reg_t sstatus
= state
.mstatus
& mask
;
463 if ((sstatus
& SSTATUS_FS
) == SSTATUS_FS
||
464 (sstatus
& SSTATUS_XS
) == SSTATUS_XS
)
465 sstatus
|= (xlen
== 32 ? SSTATUS32_SD
: SSTATUS64_SD
);
468 case CSR_SIP
: return state
.mip
& state
.mideleg
;
469 case CSR_SIE
: return state
.mie
& state
.mideleg
;
470 case CSR_SEPC
: return state
.sepc
;
471 case CSR_SBADADDR
: return state
.sbadaddr
;
472 case CSR_STVEC
: return state
.stvec
;
475 return state
.scause
| ((state
.scause
>> (max_xlen
-1)) << (xlen
-1));
477 case CSR_SPTBR
: return state
.sptbr
;
478 case CSR_SSCRATCH
: return state
.sscratch
;
479 case CSR_MSTATUS
: return state
.mstatus
;
480 case CSR_MIP
: return state
.mip
;
481 case CSR_MIE
: return state
.mie
;
482 case CSR_MEPC
: return state
.mepc
;
483 case CSR_MSCRATCH
: return state
.mscratch
;
484 case CSR_MCAUSE
: return state
.mcause
;
485 case CSR_MBADADDR
: return state
.mbadaddr
;
486 case CSR_MISA
: return isa
;
487 case CSR_MARCHID
: return 0;
488 case CSR_MIMPID
: return 0;
489 case CSR_MVENDORID
: return 0;
490 case CSR_MHARTID
: return id
;
491 case CSR_MTVEC
: return state
.mtvec
;
492 case CSR_MEDELEG
: return state
.medeleg
;
493 case CSR_MIDELEG
: return state
.mideleg
;
494 case CSR_TDRSELECT
: return 0;
498 v
= set_field(v
, DCSR_XDEBUGVER
, 1);
499 v
= set_field(v
, DCSR_HWBPCOUNT
, 0);
500 v
= set_field(v
, DCSR_NDRESET
, 0);
501 v
= set_field(v
, DCSR_FULLRESET
, 0);
502 v
= set_field(v
, DCSR_PRV
, state
.dcsr
.prv
);
503 v
= set_field(v
, DCSR_STEP
, state
.dcsr
.step
);
504 v
= set_field(v
, DCSR_DEBUGINT
, sim
->debug_module
.get_interrupt(id
));
505 v
= set_field(v
, DCSR_STOPCYCLE
, 0);
506 v
= set_field(v
, DCSR_STOPTIME
, 0);
507 v
= set_field(v
, DCSR_EBREAKM
, state
.dcsr
.ebreakm
);
508 v
= set_field(v
, DCSR_EBREAKH
, state
.dcsr
.ebreakh
);
509 v
= set_field(v
, DCSR_EBREAKS
, state
.dcsr
.ebreaks
);
510 v
= set_field(v
, DCSR_EBREAKU
, state
.dcsr
.ebreaku
);
511 v
= set_field(v
, DCSR_HALT
, state
.dcsr
.halt
);
512 v
= set_field(v
, DCSR_CAUSE
, state
.dcsr
.cause
);
518 return state
.dscratch
;
520 throw trap_illegal_instruction();
523 reg_t
illegal_instruction(processor_t
* p
, insn_t insn
, reg_t pc
)
525 throw trap_illegal_instruction();
528 insn_func_t
processor_t::decode_insn(insn_t insn
)
530 // look up opcode in hash table
531 size_t idx
= insn
.bits() % OPCODE_CACHE_SIZE
;
532 insn_desc_t desc
= opcode_cache
[idx
];
534 if (unlikely(insn
.bits() != desc
.match
)) {
535 // fall back to linear search
536 insn_desc_t
* p
= &instructions
[0];
537 while ((insn
.bits() & p
->mask
) != p
->match
)
541 if (p
->mask
!= 0 && p
> &instructions
[0]) {
542 if (p
->match
!= (p
-1)->match
&& p
->match
!= (p
+1)->match
) {
543 // move to front of opcode list to reduce miss penalty
544 while (--p
>= &instructions
[0])
546 instructions
[0] = desc
;
550 opcode_cache
[idx
] = desc
;
551 opcode_cache
[idx
].match
= insn
.bits();
554 return xlen
== 64 ? desc
.rv64
: desc
.rv32
;
557 void processor_t::register_insn(insn_desc_t desc
)
559 instructions
.push_back(desc
);
562 void processor_t::build_opcode_map()
565 bool operator()(const insn_desc_t
& lhs
, const insn_desc_t
& rhs
) {
566 if (lhs
.match
== rhs
.match
)
567 return lhs
.mask
> rhs
.mask
;
568 return lhs
.match
> rhs
.match
;
571 std::sort(instructions
.begin(), instructions
.end(), cmp());
573 for (size_t i
= 0; i
< OPCODE_CACHE_SIZE
; i
++)
574 opcode_cache
[i
] = {1, 0, &illegal_instruction
, &illegal_instruction
};
577 void processor_t::register_extension(extension_t
* x
)
579 for (auto insn
: x
->get_instructions())
582 for (auto disasm_insn
: x
->get_disasms())
583 disassembler
->add_insn(disasm_insn
);
585 throw std::logic_error("only one extension may be registered");
587 x
->set_processor(this);
590 void processor_t::register_base_instructions()
592 #define DECLARE_INSN(name, match, mask) \
593 insn_bits_t name##_match = (match), name##_mask = (mask);
594 #include "encoding.h"
597 #define DEFINE_INSN(name) \
598 REGISTER_INSN(this, name, name##_match, name##_mask)
599 #include "insn_list.h"
602 register_insn({0, 0, &illegal_instruction
, &illegal_instruction
});
606 bool processor_t::load(reg_t addr
, size_t len
, uint8_t* bytes
)
611 bool processor_t::store(reg_t addr
, size_t len
, const uint8_t* bytes
)
616 state
.mip
&= ~MIP_MSIP
;
618 state
.mip
|= MIP_MSIP
;