12 processor_t::processor_t(sim_t
* _sim
, mmu_t
* _mmu
)
13 : sim(_sim
), mmu(*_mmu
)
15 // a few assumptions about endianness, including freg_t union
16 static_assert(BYTE_ORDER
== LITTLE_ENDIAN
);
17 static_assert(sizeof(freg_t
) == 8);
18 static_assert(sizeof(reg_t
) == 8);
20 static_assert(sizeof(insn_t
) == 4);
21 static_assert(sizeof(uint128_t
) == 16 && sizeof(int128_t
) == 16);
31 processor_t::~processor_t()
38 itlbsim
->print_stats();
46 dtlbsim
->print_stats();
50 void processor_t::init(uint32_t _id
, icsim_t
* default_icache
,
51 icsim_t
* default_dcache
)
55 for (int i
=0; i
<MAX_UTS
; i
++)
57 uts
[i
] = new processor_t(sim
, &mmu
);
59 uts
[i
]->set_sr(uts
[i
]->sr
| SR_EF
);
60 uts
[i
]->set_sr(uts
[i
]->sr
| SR_EV
);
64 #ifdef RISCV_ENABLE_ICSIM
65 icsim
= new icsim_t(*default_icache
);
67 itlbsim
= new icsim_t(1, 8, 4096, "ITLB");
68 mmu
.set_itlbsim(itlbsim
);
70 #ifdef RISCV_ENABLE_ICSIM
71 dcsim
= new icsim_t(*default_dcache
);
73 dtlbsim
= new icsim_t(1, 8, 4096, "DTLB");
74 mmu
.set_dtlbsim(dtlbsim
);
78 void processor_t::reset()
82 memset(XPR
,0,sizeof(XPR
));
83 memset(FPR
,0,sizeof(FPR
));
97 set_sr(SR_S
| SR_SX
); // SX ignored if 64b mode not supported
109 for (int i
=0; i
<MAX_UTS
; i
++)
113 void processor_t::set_sr(uint32_t val
)
116 #ifndef RISCV_ENABLE_64BIT
117 sr
&= ~(SR_SX
| SR_UX
);
119 #ifndef RISCV_ENABLE_FPU
122 #ifndef RISCV_ENABLE_RVC
125 #ifndef RISCV_ENABLE_VEC
129 mmu
.set_vm_enabled(sr
& SR_VM
);
130 mmu
.set_supervisor(sr
& SR_S
);
133 xprlen
= ((sr
& SR_S
) ? (sr
& SR_SX
) : (sr
& SR_UX
)) ? 64 : 32;
136 void processor_t::set_fsr(uint32_t val
)
138 fsr
= val
& ~FSR_ZERO
;
141 void processor_t::vcfg()
143 if (nxpr_use
+ nfpr_use
< 2)
144 vlmax
= nxfpr_bank
* vecbanks_count
;
146 vlmax
= (nxfpr_bank
/ (nxpr_use
+ nfpr_use
- 1)) * vecbanks_count
;
148 vlmax
= std::min(vlmax
, MAX_UTS
);
151 void processor_t::setvl(int vlapp
)
153 vl
= std::min(vlmax
, vlapp
);
156 void processor_t::take_interrupt()
158 uint32_t interrupts
= (cause
& CAUSE_IP
) >> CAUSE_IP_SHIFT
;
159 interrupts
&= (sr
& SR_IM
) >> SR_IM_SHIFT
;
161 if(interrupts
&& (sr
& SR_ET
))
162 throw trap_interrupt
;
165 void processor_t::step(size_t n
, bool noisy
)
179 #define execute_insn(noisy) \
181 insn = _mmu.load_insn(npc, sr & SR_EC, &func); \
182 if(noisy) disasm(insn,pc); \
183 npc = func(this, insn, npc); \
187 if(noisy
) for( ; i
< n
; i
++)
191 for( ; n
> 3 && i
< n
-3; i
+=4)
209 catch(vt_command_t cmd
)
212 if (cmd
== vt_command_stop
)
223 typeof(count
) old_count
= count
;
224 typeof(count
) max_count
= -1;
226 if(old_count
< compare
&& (count
>= compare
|| old_count
> max_count
-i
))
227 cause
|= 1 << (TIMER_IRQ
+CAUSE_IP_SHIFT
);
230 void processor_t::take_trap(trap_t t
, bool noisy
)
232 demand(t
< NUM_TRAPS
, "internal error: bad trap number %d", int(t
));
233 demand(sr
& SR_ET
, "error mode on core %d!\ntrap %s, pc 0x%016llx",
234 id
, trap_name(t
), (unsigned long long)pc
);
236 printf("core %3d: trap %s, pc 0x%016llx\n",
237 id
, trap_name(t
), (unsigned long long)pc
);
239 set_sr((((sr
& ~SR_ET
) | SR_S
) & ~SR_PS
) | ((sr
& SR_S
) ? SR_PS
: 0));
240 cause
= (cause
& ~CAUSE_EXCCODE
) | (t
<< CAUSE_EXCCODE_SHIFT
);
243 badvaddr
= mmu
.get_badvaddr();
246 void processor_t::deliver_ipi()
248 cause
|= 1 << (IPI_IRQ
+CAUSE_IP_SHIFT
);
252 void processor_t::disasm(insn_t insn
, reg_t pc
)
254 printf("core %3d: 0x%016llx (0x%08x) ",id
,(unsigned long long)pc
,insn
.bits
);
256 #ifdef RISCV_HAVE_LIBOPCODES
257 disassemble_info info
;
258 INIT_DISASSEMBLE_INFO(info
, stdout
, fprintf
);
259 info
.flavour
= bfd_target_unknown_flavour
;
260 info
.arch
= bfd_arch_mips
;
261 info
.mach
= 101; // XXX bfd_mach_mips_riscv requires modified bfd.h
262 info
.endian
= BFD_ENDIAN_LITTLE
;
263 info
.buffer
= (bfd_byte
*)&insn
;
264 info
.buffer_length
= sizeof(insn
);
265 info
.buffer_vma
= pc
;
267 int ret
= print_insn_little_mips(pc
, &info
);
268 demand(ret
== insn_length(insn
.bits
), "disasm bug!");