riscv/processor.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "extension.h"
   5 #include "common.h"
   6 #include "config.h"
   7 #include "simif.h"
   8 #include "mmu.h"
   9 #include "disasm.h"
  10 #include <cinttypes>
  11 #include <cmath>
  12 #include <cstdlib>
  13 #include <iostream>
  14 #include <assert.h>
  15 #include <limits.h>
  16 #include <stdexcept>
  17 #include <algorithm>
  18
  19 #undef STATE
  20 #define STATE state
  21
  22 processor_t::processor_t(const char* isa, simif_t* sim, uint32_t id,
  23         bool halt_on_reset)
  24   : debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
  25   halt_on_reset(halt_on_reset), last_pc(1), executions(1)
  26 {
  27   disassembler = new disassembler_t(max_xlen);
  28   parse_isa_string(isa);
  29   register_base_instructions();
  30
  31   mmu = new mmu_t(sim, this);
  32
  33   reset();
  34 }
  35
  36 processor_t::~processor_t()
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   if (histogram_enabled)
  40   {
  41     fprintf(stderr, "PC Histogram size:%zu\n", pc_histogram.size());
  42     for (auto it : pc_histogram)
  43       fprintf(stderr, "%0" PRIx64 " %" PRIu64 "\n", it.first, it.second);
  44   }
  45 #endif
  46
  47   delete mmu;
  48   delete disassembler;
  49 }
  50
  51 static void bad_isa_string(const char* isa)
  52 {
  53   fprintf(stderr, "error: bad --isa option %s\n", isa);
  54   abort();
  55 }
  56
  57 void processor_t::parse_isa_string(const char* str)
  58 {
  59   std::string lowercase, tmp;
  60   for (const char *r = str; *r; r++)
  61     lowercase += std::tolower(*r);
  62
  63   const char* p = lowercase.c_str();
  64   const char* all_subsets = "imafdqc";
  65
  66   max_xlen = 64;
  67   state.misa = reg_t(2) << 62;
  68
  69   if (strncmp(p, "rv32", 4) == 0)
  70     max_xlen = 32, state.misa = reg_t(1) << 30, p += 4;
  71   else if (strncmp(p, "rv64", 4) == 0)
  72     p += 4;
  73   else if (strncmp(p, "rv", 2) == 0)
  74     p += 2;
  75
  76   if (!*p) {
  77     p = "imafdc";
  78   } else if (*p == 'g') { // treat "G" as "IMAFD"
  79     tmp = std::string("imafd") + (p+1);
  80     p = &tmp[0];
  81   } else if (*p != 'i') {
  82     bad_isa_string(str);
  83   }
  84
  85   isa_string = "rv" + std::to_string(max_xlen) + p;
  86   state.misa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
  87   state.misa |= 1L << ('u' - 'a'); // advertise support for user mode
  88
  89   while (*p) {
  90     state.misa |= 1L << (*p - 'a');
  91
  92     if (auto next = strchr(all_subsets, *p)) {
  93       all_subsets = next + 1;
  94       p++;
  95     } else if (*p == 'x') {
  96       const char* ext = p+1, *end = ext;
  97       while (islower(*end))
  98         end++;
  99       register_extension(find_extension(std::string(ext, end - ext).c_str())());
 100       p = end;
 101     } else {
 102       bad_isa_string(str);
 103     }
 104   }
 105
 106   if (supports_extension('D') && !supports_extension('F'))
 107     bad_isa_string(str);
 108
 109   if (supports_extension('Q') && !supports_extension('D'))
 110     bad_isa_string(str);
 111
 112   if (supports_extension('Q') && max_xlen < 64)
 113     bad_isa_string(str);
 114
 115   max_isa = state.misa;
 116 }
 117
 118 void state_t::reset(reg_t max_isa)
 119 {
 120   memset(this, 0, sizeof(*this));
 121   misa = max_isa;
 122   prv = PRV_M;
 123   pc = DEFAULT_RSTVEC;
 124   tselect = 0;
 125   for (unsigned int i = 0; i < num_triggers; i++)
 126     mcontrol[i].type = 2;
 127 }
 128
 129 void processor_t::set_debug(bool value)
 130 {
 131   debug = value;
 132   if (ext)
 133     ext->set_debug(value);
 134 }
 135
 136 void processor_t::set_histogram(bool value)
 137 {
 138   histogram_enabled = value;
 139 #ifndef RISCV_ENABLE_HISTOGRAM
 140   if (value) {
 141     fprintf(stderr, "PC Histogram support has not been properly enabled;");
 142     fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
 143   }
 144 #endif
 145 }
 146
 147 void processor_t::reset()
 148 {
 149   state.reset(max_isa);
 150   state.dcsr.halt = halt_on_reset;
 151   halt_on_reset = false;
 152   set_csr(CSR_MSTATUS, state.mstatus);
 153
 154   if (ext)
 155     ext->reset(); // reset the extension
 156
 157   if (sim)
 158     sim->proc_reset(id);
 159 }
 160
 161 // Count number of contiguous 0 bits starting from the LSB.
 162 static int ctz(reg_t val)
 163 {
 164   int res = 0;
 165   if (val)
 166     while ((val & 1) == 0)
 167       val >>= 1, res++;
 168   return res;
 169 }
 170
 171 void processor_t::take_interrupt(reg_t pending_interrupts)
 172 {
 173   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
 174   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
 175   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
 176
 177   reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
 178   reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
 179   // M-ints have highest priority; consider S-ints only if no M-ints pending
 180   if (enabled_interrupts == 0)
 181     enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled;
 182
 183   if (state.dcsr.cause == 0 && enabled_interrupts) {
 184     // nonstandard interrupts have highest priority
 185     if (enabled_interrupts >> IRQ_M_EXT)
 186       enabled_interrupts = enabled_interrupts >> IRQ_M_EXT << IRQ_M_EXT;
 187     // external interrupts have next-highest priority
 188     else if (enabled_interrupts & (MIP_MEIP | MIP_SEIP))
 189       enabled_interrupts = enabled_interrupts & (MIP_MEIP | MIP_SEIP);
 190     // software interrupts have next-highest priority
 191     else if (enabled_interrupts & (MIP_MSIP | MIP_SSIP))
 192       enabled_interrupts = enabled_interrupts & (MIP_MSIP | MIP_SSIP);
 193     // timer interrupts have next-highest priority
 194     else if (enabled_interrupts & (MIP_MTIP | MIP_STIP))
 195       enabled_interrupts = enabled_interrupts & (MIP_MTIP | MIP_STIP);
 196     else
 197       abort();
 198
 199     throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
 200   }
 201 }
 202
 203 static int xlen_to_uxl(int xlen)
 204 {
 205   if (xlen == 32)
 206     return 1;
 207   if (xlen == 64)
 208     return 2;
 209   abort();
 210 }
 211
 212 reg_t processor_t::legalize_privilege(reg_t prv)
 213 {
 214   assert(prv <= PRV_M);
 215
 216   if (!supports_extension('U'))
 217     return PRV_M;
 218
 219   if (prv == PRV_H || !supports_extension('S'))
 220     return PRV_U;
 221
 222   return prv;
 223 }
 224
 225 void processor_t::set_privilege(reg_t prv)
 226 {
 227   mmu->flush_tlb();
 228   state.prv = legalize_privilege(prv);
 229 }
 230
 231 void processor_t::enter_debug_mode(uint8_t cause)
 232 {
 233   state.dcsr.cause = cause;
 234   state.dcsr.prv = state.prv;
 235   set_privilege(PRV_M);
 236   state.dpc = state.pc;
 237   state.pc = DEBUG_ROM_ENTRY;
 238 }
 239
 240 void processor_t::take_trap(trap_t& t, reg_t epc)
 241 {
 242   if (debug) {
 243     fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
 244             id, t.name(), epc);
 245     if (t.has_tval())
 246       fprintf(stderr, "core %3d:           tval 0x%016" PRIx64 "\n", id,
 247           t.get_tval());
 248   }
 249
 250   if (state.dcsr.cause) {
 251     if (t.cause() == CAUSE_BREAKPOINT) {
 252       state.pc = DEBUG_ROM_ENTRY;
 253     } else {
 254       state.pc = DEBUG_ROM_TVEC;
 255     }
 256     return;
 257   }
 258
 259   if (t.cause() == CAUSE_BREAKPOINT && (
 260               (state.prv == PRV_M && state.dcsr.ebreakm) ||
 261               (state.prv == PRV_S && state.dcsr.ebreaks) ||
 262               (state.prv == PRV_U && state.dcsr.ebreaku))) {
 263     enter_debug_mode(DCSR_CAUSE_SWBP);
 264     return;
 265   }
 266
 267   // by default, trap to M-mode, unless delegated to S-mode
 268   reg_t bit = t.cause();
 269   reg_t deleg = state.medeleg;
 270   bool interrupt = (bit & ((reg_t)1 << (max_xlen-1))) != 0;
 271   if (interrupt)
 272     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
 273   if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
 274     // handle the trap in S-mode
 275     state.pc = state.stvec;
 276     state.scause = t.cause();
 277     state.sepc = epc;
 278     state.stval = t.get_tval();
 279
 280     reg_t s = state.mstatus;
 281     s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
 282     s = set_field(s, MSTATUS_SPP, state.prv);
 283     s = set_field(s, MSTATUS_SIE, 0);
 284     set_csr(CSR_MSTATUS, s);
 285     set_privilege(PRV_S);
 286   } else {
 287     reg_t vector = (state.mtvec & 1) && interrupt ? 4*bit : 0;
 288     state.pc = (state.mtvec & ~(reg_t)1) + vector;
 289     state.mepc = epc;
 290     state.mcause = t.cause();
 291     state.mtval = t.get_tval();
 292
 293     reg_t s = state.mstatus;
 294     s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
 295     s = set_field(s, MSTATUS_MPP, state.prv);
 296     s = set_field(s, MSTATUS_MIE, 0);
 297     set_csr(CSR_MSTATUS, s);
 298     set_privilege(PRV_M);
 299   }
 300 }
 301
 302 void processor_t::disasm(insn_t insn)
 303 {
 304   uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
 305   if (last_pc != state.pc || last_bits != bits) {
 306     if (executions != 1) {
 307       fprintf(stderr, "core %3d: Executed %" PRIx64 " times\n", id, executions);
 308     }
 309
 310     fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
 311             id, state.pc, bits, disassembler->disassemble(insn).c_str());
 312     last_pc = state.pc;
 313     last_bits = bits;
 314     executions = 1;
 315   } else {
 316     executions++;
 317   }
 318 }
 319
 320 int processor_t::paddr_bits()
 321 {
 322   assert(xlen == max_xlen);
 323   return max_xlen == 64 ? 50 : 34;
 324 }
 325
 326 void processor_t::set_csr(int which, reg_t val)
 327 {
 328   val = zext_xlen(val);
 329   reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
 330   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
 331   switch (which)
 332   {
 333     case CSR_FFLAGS:
 334       dirty_fp_state;
 335       state.fflags = val & (FSR_AEXC >> FSR_AEXC_SHIFT);
 336       break;
 337     case CSR_FRM:
 338       dirty_fp_state;
 339       state.frm = val & (FSR_RD >> FSR_RD_SHIFT);
 340       break;
 341     case CSR_FCSR:
 342       dirty_fp_state;
 343       state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
 344       state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 345       break;
 346     case CSR_MSTATUS: {
 347       if ((val ^ state.mstatus) &
 348           (MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR))
 349         mmu->flush_tlb();
 350
 351       reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
 352                  | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM
 353                  | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM
 354                  | MSTATUS_TSR | MSTATUS_UXL | MSTATUS_SXL |
 355                  (ext ? MSTATUS_XS : 0);
 356
 357       reg_t requested_mpp = legalize_privilege(get_field(val, MSTATUS_MPP));
 358       state.mstatus = set_field(state.mstatus, MSTATUS_MPP, requested_mpp);
 359       if (supports_extension('S'))
 360         mask |= MSTATUS_SPP;
 361
 362       state.mstatus = (state.mstatus & ~mask) | (val & mask);
 363
 364       bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
 365       dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
 366       if (max_xlen == 32)
 367         state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
 368       else
 369         state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
 370
 371       state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
 372       state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
 373       state.mstatus = set_field(state.mstatus, MSTATUS_SXL, xlen_to_uxl(max_xlen));
 374       // U-XLEN == S-XLEN == M-XLEN
 375       xlen = max_xlen;
 376       break;
 377     }
 378     case CSR_MIP: {
 379       reg_t mask = MIP_SSIP | MIP_STIP;
 380       state.mip = (state.mip & ~mask) | (val & mask);
 381       break;
 382     }
 383     case CSR_MIE:
 384       state.mie = (state.mie & ~all_ints) | (val & all_ints);
 385       break;
 386     case CSR_MIDELEG:
 387       state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
 388       break;
 389     case CSR_MEDELEG: {
 390       reg_t mask =
 391         (1 << CAUSE_MISALIGNED_FETCH) |
 392         (1 << CAUSE_BREAKPOINT) |
 393         (1 << CAUSE_USER_ECALL) |
 394         (1 << CAUSE_FETCH_PAGE_FAULT) |
 395         (1 << CAUSE_LOAD_PAGE_FAULT) |
 396         (1 << CAUSE_STORE_PAGE_FAULT);
 397       state.medeleg = (state.medeleg & ~mask) | (val & mask);
 398       break;
 399     }
 400     case CSR_MINSTRET:
 401     case CSR_MCYCLE:
 402       if (xlen == 32)
 403         state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
 404       else
 405         state.minstret = val;
 406       // The ISA mandates that if an instruction writes instret, the write
 407       // takes precedence over the increment to instret.  However, Spike
 408       // unconditionally increments instret after executing an instruction.
 409       // Correct for this artifact by decrementing instret here.
 410       state.minstret--;
 411       break;
 412     case CSR_MINSTRETH:
 413     case CSR_MCYCLEH:
 414       state.minstret = (val << 32) | (state.minstret << 32 >> 32);
 415       state.minstret--; // See comment above.
 416       break;
 417     case CSR_SCOUNTEREN:
 418       state.scounteren = val;
 419       break;
 420     case CSR_MCOUNTEREN:
 421       state.mcounteren = val;
 422       break;
 423     case CSR_SSTATUS: {
 424       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 425                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR;
 426       return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
 427     }
 428     case CSR_SIP: {
 429       reg_t mask = MIP_SSIP & state.mideleg;
 430       return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask));
 431     }
 432     case CSR_SIE:
 433       return set_csr(CSR_MIE,
 434                      (state.mie & ~state.mideleg) | (val & state.mideleg));
 435     case CSR_SATP: {
 436       mmu->flush_tlb();
 437       if (max_xlen == 32)
 438         state.satp = val & (SATP32_PPN | SATP32_MODE);
 439       if (max_xlen == 64 && (get_field(val, SATP64_MODE) == SATP_MODE_OFF ||
 440                              get_field(val, SATP64_MODE) == SATP_MODE_SV39 ||
 441                              get_field(val, SATP64_MODE) == SATP_MODE_SV48))
 442         state.satp = val & (SATP64_PPN | SATP64_MODE);
 443       break;
 444     }
 445     case CSR_SEPC: state.sepc = val & ~(reg_t)1; break;
 446     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
 447     case CSR_SSCRATCH: state.sscratch = val; break;
 448     case CSR_SCAUSE: state.scause = val; break;
 449     case CSR_STVAL: state.stval = val; break;
 450     case CSR_MEPC: state.mepc = val & ~(reg_t)1; break;
 451     case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break;
 452     case CSR_MSCRATCH: state.mscratch = val; break;
 453     case CSR_MCAUSE: state.mcause = val; break;
 454     case CSR_MTVAL: state.mtval = val; break;
 455     case CSR_MISA: {
 456       // the write is ignored if increasing IALIGN would misalign the PC
 457       if (!(val & (1L << ('C' - 'A'))) && (state.pc & 2))
 458         break;
 459
 460       if (!(val & (1L << ('F' - 'A'))))
 461         val &= ~(1L << ('D' - 'A'));
 462
 463       // allow MAFDC bits in MISA to be modified
 464       reg_t mask = 0;
 465       mask |= 1L << ('M' - 'A');
 466       mask |= 1L << ('A' - 'A');
 467       mask |= 1L << ('F' - 'A');
 468       mask |= 1L << ('D' - 'A');
 469       mask |= 1L << ('C' - 'A');
 470       mask &= max_isa;
 471
 472       state.misa = (val & mask) | (state.misa & ~mask);
 473       break;
 474     }
 475     case CSR_TSELECT:
 476       if (val < state.num_triggers) {
 477         state.tselect = val;
 478       }
 479       break;
 480     case CSR_TDATA1:
 481       {
 482         mcontrol_t *mc = &state.mcontrol[state.tselect];
 483         if (mc->dmode && !state.dcsr.cause) {
 484           break;
 485         }
 486         mc->dmode = get_field(val, MCONTROL_DMODE(xlen));
 487         mc->select = get_field(val, MCONTROL_SELECT);
 488         mc->timing = get_field(val, MCONTROL_TIMING);
 489         mc->action = (mcontrol_action_t) get_field(val, MCONTROL_ACTION);
 490         mc->chain = get_field(val, MCONTROL_CHAIN);
 491         mc->match = (mcontrol_match_t) get_field(val, MCONTROL_MATCH);
 492         mc->m = get_field(val, MCONTROL_M);
 493         mc->h = get_field(val, MCONTROL_H);
 494         mc->s = get_field(val, MCONTROL_S);
 495         mc->u = get_field(val, MCONTROL_U);
 496         mc->execute = get_field(val, MCONTROL_EXECUTE);
 497         mc->store = get_field(val, MCONTROL_STORE);
 498         mc->load = get_field(val, MCONTROL_LOAD);
 499         // Assume we're here because of csrw.
 500         if (mc->execute)
 501           mc->timing = 0;
 502         trigger_updated();
 503       }
 504       break;
 505     case CSR_TDATA2:
 506       if (state.mcontrol[state.tselect].dmode && !state.dcsr.cause) {
 507         break;
 508       }
 509       if (state.tselect < state.num_triggers) {
 510         state.tdata2[state.tselect] = val;
 511       }
 512       break;
 513     case CSR_DCSR:
 514       state.dcsr.prv = get_field(val, DCSR_PRV);
 515       state.dcsr.step = get_field(val, DCSR_STEP);
 516       // TODO: ndreset and fullreset
 517       state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
 518       state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
 519       state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
 520       state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
 521       state.dcsr.halt = get_field(val, DCSR_HALT);
 522       break;
 523     case CSR_DPC:
 524       state.dpc = val & ~(reg_t)1;
 525       break;
 526     case CSR_DSCRATCH:
 527       state.dscratch = val;
 528       break;
 529   }
 530 }
 531
 532 reg_t processor_t::get_csr(int which)
 533 {
 534   uint32_t ctr_en = -1;
 535   if (state.prv < PRV_M)
 536     ctr_en &= state.mcounteren;
 537   if (state.prv < PRV_S)
 538     ctr_en &= state.scounteren;
 539   bool ctr_ok = (ctr_en >> (which & 31)) & 1;
 540
 541   if (ctr_ok) {
 542     if (which >= CSR_HPMCOUNTER3 && which <= CSR_HPMCOUNTER31)
 543       return 0;
 544     if (xlen == 32 && which >= CSR_HPMCOUNTER3H && which <= CSR_HPMCOUNTER31H)
 545       return 0;
 546   }
 547   if (which >= CSR_MHPMCOUNTER3 && which <= CSR_MHPMCOUNTER31)
 548     return 0;
 549   if (xlen == 32 && which >= CSR_MHPMCOUNTER3H && which <= CSR_MHPMCOUNTER31H)
 550     return 0;
 551   if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31)
 552     return 0;
 553
 554   switch (which)
 555   {
 556     case CSR_FFLAGS:
 557       require_fp;
 558       if (!supports_extension('F'))
 559         break;
 560       return state.fflags;
 561     case CSR_FRM:
 562       require_fp;
 563       if (!supports_extension('F'))
 564         break;
 565       return state.frm;
 566     case CSR_FCSR:
 567       require_fp;
 568       if (!supports_extension('F'))
 569         break;
 570       return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
 571     case CSR_INSTRET:
 572     case CSR_CYCLE:
 573       if (ctr_ok)
 574         return state.minstret;
 575       break;
 576     case CSR_MINSTRET:
 577     case CSR_MCYCLE:
 578       return state.minstret;
 579     case CSR_INSTRETH:
 580     case CSR_CYCLEH:
 581       if (ctr_ok && xlen == 32)
 582         return state.minstret >> 32;
 583       break;
 584     case CSR_MINSTRETH:
 585     case CSR_MCYCLEH:
 586       if (xlen == 32)
 587         return state.minstret >> 32;
 588       break;
 589     case CSR_SCOUNTEREN: return state.scounteren;
 590     case CSR_MCOUNTEREN: return state.mcounteren;
 591     case CSR_SSTATUS: {
 592       reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
 593                  | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_UXL;
 594       reg_t sstatus = state.mstatus & mask;
 595       if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
 596           (sstatus & SSTATUS_XS) == SSTATUS_XS)
 597         sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
 598       return sstatus;
 599     }
 600     case CSR_SIP: return state.mip & state.mideleg;
 601     case CSR_SIE: return state.mie & state.mideleg;
 602     case CSR_SEPC: return state.sepc & pc_alignment_mask();
 603     case CSR_STVAL: return state.stval;
 604     case CSR_STVEC: return state.stvec;
 605     case CSR_SCAUSE:
 606       if (max_xlen > xlen)
 607         return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
 608       return state.scause;
 609     case CSR_SATP:
 610       if (get_field(state.mstatus, MSTATUS_TVM))
 611         require_privilege(PRV_M);
 612       return state.satp;
 613     case CSR_SSCRATCH: return state.sscratch;
 614     case CSR_MSTATUS: return state.mstatus;
 615     case CSR_MIP: return state.mip;
 616     case CSR_MIE: return state.mie;
 617     case CSR_MEPC: return state.mepc & pc_alignment_mask();
 618     case CSR_MSCRATCH: return state.mscratch;
 619     case CSR_MCAUSE: return state.mcause;
 620     case CSR_MTVAL: return state.mtval;
 621     case CSR_MISA: return state.misa;
 622     case CSR_MARCHID: return 0;
 623     case CSR_MIMPID: return 0;
 624     case CSR_MVENDORID: return 0;
 625     case CSR_MHARTID: return id;
 626     case CSR_MTVEC: return state.mtvec;
 627     case CSR_MEDELEG: return state.medeleg;
 628     case CSR_MIDELEG: return state.mideleg;
 629     case CSR_TSELECT: return state.tselect;
 630     case CSR_TDATA1:
 631       if (state.tselect < state.num_triggers) {
 632         reg_t v = 0;
 633         mcontrol_t *mc = &state.mcontrol[state.tselect];
 634         v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
 635         v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
 636         v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
 637         v = set_field(v, MCONTROL_SELECT, mc->select);
 638         v = set_field(v, MCONTROL_TIMING, mc->timing);
 639         v = set_field(v, MCONTROL_ACTION, mc->action);
 640         v = set_field(v, MCONTROL_CHAIN, mc->chain);
 641         v = set_field(v, MCONTROL_MATCH, mc->match);
 642         v = set_field(v, MCONTROL_M, mc->m);
 643         v = set_field(v, MCONTROL_H, mc->h);
 644         v = set_field(v, MCONTROL_S, mc->s);
 645         v = set_field(v, MCONTROL_U, mc->u);
 646         v = set_field(v, MCONTROL_EXECUTE, mc->execute);
 647         v = set_field(v, MCONTROL_STORE, mc->store);
 648         v = set_field(v, MCONTROL_LOAD, mc->load);
 649         return v;
 650       } else {
 651         return 0;
 652       }
 653       break;
 654     case CSR_TDATA2:
 655       if (state.tselect < state.num_triggers) {
 656         return state.tdata2[state.tselect];
 657       } else {
 658         return 0;
 659       }
 660       break;
 661     case CSR_TDATA3: return 0;
 662     case CSR_DCSR:
 663       {
 664         uint32_t v = 0;
 665         v = set_field(v, DCSR_XDEBUGVER, 1);
 666         v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
 667         v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
 668         v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
 669         v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
 670         v = set_field(v, DCSR_STOPCYCLE, 0);
 671         v = set_field(v, DCSR_STOPTIME, 0);
 672         v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
 673         v = set_field(v, DCSR_STEP, state.dcsr.step);
 674         v = set_field(v, DCSR_PRV, state.dcsr.prv);
 675         return v;
 676       }
 677     case CSR_DPC:
 678       return state.dpc & pc_alignment_mask();
 679     case CSR_DSCRATCH:
 680       return state.dscratch;
 681   }
 682   throw trap_illegal_instruction(0);
 683 }
 684
 685 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 686 {
 687   throw trap_illegal_instruction(0);
 688 }
 689
 690 insn_func_t processor_t::decode_insn(insn_t insn)
 691 {
 692   // look up opcode in hash table
 693   size_t idx = insn.bits() % OPCODE_CACHE_SIZE;
 694   insn_desc_t desc = opcode_cache[idx];
 695
 696   if (unlikely(insn.bits() != desc.match)) {
 697     // fall back to linear search
 698     insn_desc_t* p = &instructions[0];
 699     while ((insn.bits() & p->mask) != p->match)
 700       p++;
 701     desc = *p;
 702
 703     if (p->mask != 0 && p > &instructions[0]) {
 704       if (p->match != (p-1)->match && p->match != (p+1)->match) {
 705         // move to front of opcode list to reduce miss penalty
 706         while (--p >= &instructions[0])
 707           *(p+1) = *p;
 708         instructions[0] = desc;
 709       }
 710     }
 711
 712     opcode_cache[idx] = desc;
 713     opcode_cache[idx].match = insn.bits();
 714   }
 715
 716   return xlen == 64 ? desc.rv64 : desc.rv32;
 717 }
 718
 719 void processor_t::register_insn(insn_desc_t desc)
 720 {
 721   instructions.push_back(desc);
 722 }
 723
 724 void processor_t::build_opcode_map()
 725 {
 726   struct cmp {
 727     bool operator()(const insn_desc_t& lhs, const insn_desc_t& rhs) {
 728       if (lhs.match == rhs.match)
 729         return lhs.mask > rhs.mask;
 730       return lhs.match > rhs.match;
 731     }
 732   };
 733   std::sort(instructions.begin(), instructions.end(), cmp());
 734
 735   for (size_t i = 0; i < OPCODE_CACHE_SIZE; i++)
 736     opcode_cache[i] = {0, 0, &illegal_instruction, &illegal_instruction};
 737 }
 738
 739 void processor_t::register_extension(extension_t* x)
 740 {
 741   for (auto insn : x->get_instructions())
 742     register_insn(insn);
 743   build_opcode_map();
 744   for (auto disasm_insn : x->get_disasms())
 745     disassembler->add_insn(disasm_insn);
 746   if (ext != NULL)
 747     throw std::logic_error("only one extension may be registered");
 748   ext = x;
 749   x->set_processor(this);
 750 }
 751
 752 void processor_t::register_base_instructions()
 753 {
 754   #define DECLARE_INSN(name, match, mask) \
 755     insn_bits_t name##_match = (match), name##_mask = (mask);
 756   #include "encoding.h"
 757   #undef DECLARE_INSN
 758
 759   #define DEFINE_INSN(name) \
 760     REGISTER_INSN(this, name, name##_match, name##_mask)
 761   #include "insn_list.h"
 762   #undef DEFINE_INSN
 763
 764   register_insn({0, 0, &illegal_instruction, &illegal_instruction});
 765   build_opcode_map();
 766 }
 767
 768 bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
 769 {
 770   switch (addr)
 771   {
 772     case 0:
 773       if (len <= 4) {
 774         memset(bytes, 0, len);
 775         bytes[0] = get_field(state.mip, MIP_MSIP);
 776         return true;
 777       }
 778       break;
 779   }
 780
 781   return false;
 782 }
 783
 784 bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
 785 {
 786   switch (addr)
 787   {
 788     case 0:
 789       if (len <= 4) {
 790         state.mip = set_field(state.mip, MIP_MSIP, bytes[0]);
 791         return true;
 792       }
 793       break;
 794   }
 795
 796   return false;
 797 }
 798
 799 void processor_t::trigger_updated()
 800 {
 801   mmu->flush_tlb();
 802   mmu->check_triggers_fetch = false;
 803   mmu->check_triggers_load = false;
 804   mmu->check_triggers_store = false;
 805
 806   for (unsigned i = 0; i < state.num_triggers; i++) {
 807     if (state.mcontrol[i].execute) {
 808       mmu->check_triggers_fetch = true;
 809     }
 810     if (state.mcontrol[i].load) {
 811       mmu->check_triggers_load = true;
 812     }
 813     if (state.mcontrol[i].store) {
 814       mmu->check_triggers_store = true;
 815     }
 816   }
 817 }