08c367298738151e95822b0c15aecf1e194d5e43
1 // See LICENSE for license details.
3 #ifndef _RISCV_PROCESSOR_H
4 #define _RISCV_PROCESSOR_H
16 typedef reg_t (*insn_func_t
)(processor_t
*, insn_t
, reg_t
);
19 // this class represents one processor in a RISC-V machine.
23 processor_t(sim_t
* _sim
, mmu_t
* _mmu
, uint32_t _id
);
26 void reset(bool value
);
27 void step(size_t n
, bool noisy
); // run for n cycles
28 void deliver_ipi(); // register an interprocessor interrupt
29 bool running() { return run
; }
30 void set_pcr(int which
, reg_t val
);
31 void set_interrupt(int which
, bool on
);
32 reg_t
get_pcr(int which
);
33 mmu_t
* get_mmu() { return &mmu
; }
35 void register_insn(uint32_t match
, uint32_t mask
, insn_func_t rv32
, insn_func_t rv64
);
39 mmu_t
& mmu
; // main memory is always accessed via the mmu
41 // user-visible architected state
43 regfile_t
<reg_t
, NXPR
, true> XPR
;
44 regfile_t
<freg_t
, NFPR
, false> FPR
;
47 // privileged control registers
57 uint32_t sr
; // only modify the status register using set_pcr()
64 struct opcode_map_entry_t
72 std::multimap
<uint32_t, opcode_map_entry_t
> opcode_map
;
74 void take_interrupt(); // take a trap if any interrupts are pending
75 void set_fsr(uint32_t val
); // set the floating-point status register
76 void take_trap(reg_t t
, bool noisy
); // take an exception
77 void disasm(insn_t insn
, reg_t pc
); // disassemble and print an instruction
81 void setvl(int vlapp
);
84 uint32_t vecbanks_count
;
93 processor_t
* uts
[MAX_UTS
];
95 // this constructor is used for each of the uts
96 processor_t(sim_t
* _sim
, mmu_t
* _mmu
, uint32_t _id
, uint32_t _utidx
);
100 friend class htif_isasim_t
;
102 #define DECLARE_INSN(name, match, mask) \
103 reg_t rv32_ ## name(insn_t insn, reg_t pc); \
104 reg_t rv64_ ## name(insn_t insn, reg_t pc);
108 insn_func_t
decode_insn(insn_t insn
);
109 reg_t
illegal_instruction(insn_t insn
, reg_t pc
);