1 // See LICENSE for license details.
2 #ifndef _RISCV_PROCESSOR_H
3 #define _RISCV_PROCESSOR_H
12 #include "debug_rom_defines.h"
14 #include "sv_decode.h"
19 typedef reg_t (*insn_func_t
)(processor_t
*, insn_t
, reg_t
);
33 struct commit_log_reg_t
53 ACTION_DEBUG_EXCEPTION
= MCONTROL_ACTION_DEBUG_EXCEPTION
,
54 ACTION_DEBUG_MODE
= MCONTROL_ACTION_DEBUG_MODE
,
55 ACTION_TRACE_START
= MCONTROL_ACTION_TRACE_START
,
56 ACTION_TRACE_STOP
= MCONTROL_ACTION_TRACE_STOP
,
57 ACTION_TRACE_EMIT
= MCONTROL_ACTION_TRACE_EMIT
62 MATCH_EQUAL
= MCONTROL_MATCH_EQUAL
,
63 MATCH_NAPOT
= MCONTROL_MATCH_NAPOT
,
64 MATCH_GE
= MCONTROL_MATCH_GE
,
65 MATCH_LT
= MCONTROL_MATCH_LT
,
66 MATCH_MASK_LOW
= MCONTROL_MATCH_MASK_LOW
,
67 MATCH_MASK_HIGH
= MCONTROL_MATCH_MASK_HIGH
77 mcontrol_action_t action
;
79 mcontrol_match_t match
;
89 // architectural state of a RISC-V hart
92 void reset(reg_t max_isa
);
94 static const int num_triggers
= 4;
97 regfile_t
<reg_t
, NXPR
, true> XPR
;
98 regfile_t
<freg_t
, NFPR
, false> FPR
;
100 // control and status registers
101 reg_t prv
; // TODO: Can this be an enum instead?
126 mcontrol_t mcontrol
[num_triggers
];
127 reg_t tdata2
[num_triggers
];
132 sv_reg_csr_entry sv_csrs
[SV_CSR_SZ
];
133 sv_reg_entry sv_int_tb
[NXPR
];
134 sv_reg_entry sv_fp_tb
[NFPR
];
135 sv_pred_csr_entry sv_pred_csrs
[SV_CSR_SZ
];
136 sv_pred_entry sv_pred_int_tb
[NXPR
];
137 sv_pred_entry sv_pred_fp_tb
[NFPR
];
142 bool serialized
; // whether timer CSRs are in a well-defined state
144 // When true, execute a single instruction and then enter debug mode. This
145 // can only be set by executing dret.
152 #ifdef RISCV_ENABLE_COMMITLOG
153 commit_log_reg_t log_reg_write
;
154 reg_t last_inst_priv
;
164 } trigger_operation_t
;
166 // Count number of contiguous 1 bits starting from the LSB.
167 static int cto(reg_t val
)
170 while ((val
& 1) == 1)
175 // this class represents one processor in a RISC-V machine.
176 class processor_t
: public abstract_device_t
179 processor_t(const char* isa
, simif_t
* sim
, uint32_t id
, bool halt_on_reset
=false);
182 void set_debug(bool value
);
183 void set_histogram(bool value
);
185 void step(size_t n
); // run for n cycles
186 void set_csr(int which
, reg_t val
);
187 reg_t
get_csr(int which
);
188 mmu_t
* get_mmu() { return mmu
; }
189 state_t
* get_state() { return &state
; }
190 unsigned get_xlen() { return xlen
; }
191 unsigned get_max_xlen() { return max_xlen
; }
192 std::string
get_isa_string() { return isa_string
; }
193 unsigned get_flen() {
194 return supports_extension('Q') ? 128 :
195 supports_extension('D') ? 64 :
196 supports_extension('F') ? 32 : 0;
198 extension_t
* get_extension() { return ext
; }
199 bool supports_extension(unsigned char ext
) {
200 if (ext
>= 'a' && ext
<= 'z') ext
+= 'A' - 'a';
201 return ext
>= 'A' && ext
<= 'Z' && ((state
.misa
>> (ext
- 'A')) & 1);
203 reg_t
pc_alignment_mask() {
204 return ~(reg_t
)(supports_extension('C') ? 0 : 2);
206 void check_pc_alignment(reg_t pc
) {
207 if (unlikely(pc
& ~pc_alignment_mask()))
208 throw trap_instruction_address_misaligned(pc
);
210 reg_t
legalize_privilege(reg_t
);
211 void set_privilege(reg_t
);
212 void update_histogram(reg_t pc
);
213 const disassembler_t
* get_disassembler() { return disassembler
; }
215 void register_insn(insn_desc_t
);
216 void register_extension(extension_t
*);
218 // MMIO slave interface
219 bool load(reg_t addr
, size_t len
, uint8_t* bytes
);
220 bool store(reg_t addr
, size_t len
, const uint8_t* bytes
);
222 // When true, display disassembly of each instruction that's executed.
224 // When true, take the slow simulation path.
226 bool halted() { return state
.dcsr
.cause
? true : false; }
229 // Return the index of a trigger that matched, or -1.
230 inline int trigger_match(trigger_operation_t operation
, reg_t address
, reg_t data
)
232 if (state
.dcsr
.cause
)
235 bool chain_ok
= true;
237 for (unsigned int i
= 0; i
< state
.num_triggers
; i
++) {
239 chain_ok
|= !state
.mcontrol
[i
].chain
;
243 if ((operation
== OPERATION_EXECUTE
&& !state
.mcontrol
[i
].execute
) ||
244 (operation
== OPERATION_STORE
&& !state
.mcontrol
[i
].store
) ||
245 (operation
== OPERATION_LOAD
&& !state
.mcontrol
[i
].load
) ||
246 (state
.prv
== PRV_M
&& !state
.mcontrol
[i
].m
) ||
247 (state
.prv
== PRV_S
&& !state
.mcontrol
[i
].s
) ||
248 (state
.prv
== PRV_U
&& !state
.mcontrol
[i
].u
)) {
253 if (state
.mcontrol
[i
].select
) {
259 // We need this because in 32-bit mode sometimes the PC bits get sign
265 switch (state
.mcontrol
[i
].match
) {
267 if (value
!= state
.tdata2
[i
])
272 reg_t mask
= ~((1 << cto(state
.tdata2
[i
])) - 1);
273 if ((value
& mask
) != (state
.tdata2
[i
] & mask
))
278 if (value
< state
.tdata2
[i
])
282 if (value
>= state
.tdata2
[i
])
287 reg_t mask
= state
.tdata2
[i
] >> (xlen
/2);
288 if ((value
& mask
) != (state
.tdata2
[i
] & mask
))
292 case MATCH_MASK_HIGH
:
294 reg_t mask
= state
.tdata2
[i
] >> (xlen
/2);
295 if (((value
>> (xlen
/2)) & mask
) != (state
.tdata2
[i
] & mask
))
301 if (!state
.mcontrol
[i
].chain
) {
309 void trigger_updated();
313 mmu_t
* mmu
; // main memory is always accessed via the mmu
315 disassembler_t
* disassembler
;
321 std::string isa_string
;
322 bool histogram_enabled
;
325 std::vector
<insn_desc_t
> instructions
;
326 std::map
<reg_t
,uint64_t> pc_histogram
;
328 static const size_t OPCODE_CACHE_SIZE
= 8191;
329 insn_desc_t opcode_cache
[OPCODE_CACHE_SIZE
];
331 void take_pending_interrupt() { take_interrupt(state
.mip
& state
.mie
); }
332 void take_interrupt(reg_t mask
); // take first enabled interrupt in mask
333 void take_trap(trap_t
& t
, reg_t epc
); // take an exception
334 void disasm(insn_t insn
); // disassemble and print an instruction
337 void enter_debug_mode(uint8_t cause
);
340 friend class clint_t
;
341 friend class extension_t
;
343 void parse_isa_string(const char* isa
);
344 void build_opcode_map();
345 void register_base_instructions();
346 insn_func_t
decode_insn(insn_t insn
);
348 // Track repeated executions for processor_t::disasm()
349 uint64_t last_pc
, last_bits
, executions
;
352 reg_t
illegal_instruction(processor_t
* p
, insn_t insn
, reg_t pc
);
354 #define REGISTER_INSN(proc, name, match, mask) \
355 extern reg_t rv32_##name(processor_t*, insn_t, reg_t); \
356 extern reg_t rv64_##name(processor_t*, insn_t, reg_t); \
357 proc->register_insn((insn_desc_t){match, mask, rv32_##name, rv64_##name});