1e007a8fbdbb1829bdfbb673feaa4687578dbbb4
1 #ifndef _RISCV_PROCESSOR_H
2 #define _RISCV_PROCESSOR_H
13 typedef reg_t (*insn_func_t
)(processor_t
*, insn_t
, reg_t
);
16 // this class represents one processor in a RISC-V machine.
20 processor_t(sim_t
* _sim
, mmu_t
* _mmu
, uint32_t _id
);
23 void step(size_t n
, bool noisy
); // run for n cycles
24 void deliver_ipi(); // register an interprocessor interrupt
28 mmu_t
& mmu
; // main memory is always accessed via the mmu
30 // user-visible architected state
38 // privileged control registers
45 uint32_t interrupts_pending
;
47 uint32_t sr
; // only modify the status register using set_sr()
52 // # of bits in an XPR (32 or 64). (redundant with sr)
55 // is this processor running? (deliver_ipi() sets this)
59 void reset(); // resets architected state; halts processor if it was running
60 void take_interrupt(); // take a trap if any interrupts are pending
61 void set_sr(uint32_t val
); // set the status register
62 void set_fsr(uint32_t val
); // set the floating-point status register
63 void take_trap(trap_t t
, bool noisy
); // take an exception
64 void disasm(insn_t insn
, reg_t pc
); // disassemble and print an instruction
68 void setvl(int vlapp
);
71 uint32_t vecbanks_count
;
80 processor_t
* uts
[MAX_UTS
];
82 // this constructor is used for each of the uts
83 processor_t(sim_t
* _sim
, mmu_t
* _mmu
, uint32_t _id
, uint32_t _utidx
);
91 #ifndef RISCV_ENABLE_RVC
93 do { if((x) & (sizeof(insn_t)-1)) \
94 { badvaddr = (x); throw trap_instruction_address_misaligned; } \
99 do { if((x) & ((sr & SR_EC) ? 1 : 3)) \
100 { badvaddr = (x); throw trap_instruction_address_misaligned; } \