1 // See LICENSE for license details.
2 #ifndef _RISCV_PROCESSOR_H
3 #define _RISCV_PROCESSOR_H
14 typedef reg_t (*insn_func_t
)(processor_t
*, insn_t
, reg_t
);
28 struct commit_log_reg_t
46 // architectural state of a RISC-V hart
52 regfile_t
<reg_t
, NXPR
, true> XPR
;
53 regfile_t
<freg_t
, NFPR
, false> FPR
;
55 // control and status registers
82 bool serialized
; // whether timer CSRs are in a well-defined state
84 reg_t load_reservation
;
86 #ifdef RISCV_ENABLE_COMMITLOG
87 commit_log_reg_t log_reg_write
;
92 // this class represents one processor in a RISC-V machine.
93 class processor_t
: public abstract_device_t
96 processor_t(const char* isa
, sim_t
* sim
, uint32_t id
);
99 void set_debug(bool value
);
100 void set_histogram(bool value
);
101 void reset(bool value
);
102 void step(size_t n
); // run for n cycles
103 bool running() { return run
; }
104 void set_csr(int which
, reg_t val
);
105 void raise_interrupt(reg_t which
);
106 reg_t
get_csr(int which
);
107 mmu_t
* get_mmu() { return mmu
; }
108 state_t
* get_state() { return &state
; }
109 extension_t
* get_extension() { return ext
; }
110 bool supports_extension(unsigned char ext
) {
111 if (ext
>= 'a' && ext
<= 'z') ext
+= 'A' - 'a';
112 return ext
>= 'A' && ext
<= 'Z' && ((isa
>> (ext
- 'A')) & 1);
114 void set_privilege(reg_t
);
115 void yield_load_reservation() { state
.load_reservation
= (reg_t
)-1; }
116 void update_histogram(reg_t pc
);
118 void register_insn(insn_desc_t
);
119 void register_extension(extension_t
*);
121 // MMIO slave interface
122 bool load(reg_t addr
, size_t len
, uint8_t* bytes
);
123 bool store(reg_t addr
, size_t len
, const uint8_t* bytes
);
125 // When true, display disassembly of each instruction that's executed.
130 mmu_t
* mmu
; // main memory is always accessed via the mmu
132 disassembler_t
* disassembler
;
138 std::string isa_string
;
140 bool histogram_enabled
;
142 std::vector
<insn_desc_t
> instructions
;
143 std::map
<reg_t
,uint64_t> pc_histogram
;
145 static const size_t OPCODE_CACHE_SIZE
= 8191;
146 insn_desc_t opcode_cache
[OPCODE_CACHE_SIZE
];
149 void take_interrupt(); // take a trap if any interrupts are pending
150 void take_trap(trap_t
& t
, reg_t epc
); // take an exception
151 void disasm(insn_t insn
); // disassemble and print an instruction
153 void enter_debug_mode(uint8_t cause
);
158 friend class extension_t
;
160 void parse_isa_string(const char* isa
);
161 void build_opcode_map();
162 void register_base_instructions();
163 insn_func_t
decode_insn(insn_t insn
);
166 reg_t
illegal_instruction(processor_t
* p
, insn_t insn
, reg_t pc
);
168 #define REGISTER_INSN(proc, name, match, mask) \
169 extern reg_t rv32_##name(processor_t*, insn_t, reg_t); \
170 extern reg_t rv64_##name(processor_t*, insn_t, reg_t); \
171 proc->register_insn((insn_desc_t){match, mask, rv32_##name, rv64_##name});