e2847faefaf1ff60ff890d95ad0521502f8f00a3
1 // See LICENSE for license details.
2 #ifndef _RISCV_PROCESSOR_H
3 #define _RISCV_PROCESSOR_H
12 typedef reg_t (*insn_func_t
)(processor_t
*, insn_t
, reg_t
);
26 // architectural state of a RISC-V hart
32 regfile_t
<reg_t
, NXPR
, true> XPR
;
33 regfile_t
<freg_t
, NFPR
, false> FPR
;
35 // control and status registers
47 uint32_t sr
; // only modify the status register using set_pcr()
51 reg_t load_reservation
;
54 // this class represents one processor in a RISC-V machine.
58 processor_t(sim_t
* _sim
, mmu_t
* _mmu
, uint32_t _id
);
61 void set_debug(bool value
);
62 void reset(bool value
);
63 void step(size_t n
); // run for n cycles
64 void deliver_ipi(); // register an interprocessor interrupt
65 bool running() { return run
; }
66 reg_t
set_pcr(int which
, reg_t val
);
67 void set_fromhost(reg_t val
);
68 void set_interrupt(int which
, bool on
);
69 reg_t
get_pcr(int which
);
70 mmu_t
* get_mmu() { return mmu
; }
71 state_t
* get_state() { return &state
; }
72 extension_t
* get_extension() { return ext
; }
73 void yield_load_reservation() { state
.load_reservation
= (reg_t
)-1; }
75 void register_insn(insn_desc_t
);
76 void register_extension(extension_t
*);
80 mmu_t
* mmu
; // main memory is always accessed via the mmu
82 disassembler_t
* disassembler
;
89 std::vector
<insn_desc_t
> instructions
;
90 std::vector
<insn_desc_t
*> opcode_map
;
91 std::vector
<insn_desc_t
> opcode_store
;
93 void take_interrupt(); // take a trap if any interrupts are pending
94 void take_trap(trap_t
& t
); // take an exception
95 void disasm(insn_t insn
); // disassemble and print an instruction
99 friend class extension_t
;
101 void build_opcode_map();
102 insn_func_t
decode_insn(insn_t insn
);
105 reg_t
illegal_instruction(processor_t
* p
, insn_t insn
, reg_t pc
);
107 #define REGISTER_INSN(proc, name, match, mask) \
108 extern reg_t rv32_##name(processor_t*, insn_t, reg_t); \
109 extern reg_t rv64_##name(processor_t*, insn_t, reg_t); \
110 proc->register_insn((insn_desc_t){match, mask, rv32_##name, rv64_##name});