e9c8be32850bdcfee6451a613dd1fbc6eb6ad0d8
1 #ifndef _RISCV_PROCESSOR_H
2 #define _RISCV_PROCESSOR_H
13 typedef reg_t (*insn_func_t
)(processor_t
*, insn_t
, reg_t
);
16 // this class represents one processor in a RISC-V machine.
20 processor_t(sim_t
* _sim
, mmu_t
* _mmu
, uint32_t _id
);
23 void reset(bool value
);
24 void step(size_t n
, bool noisy
); // run for n cycles
25 void deliver_ipi(); // register an interprocessor interrupt
26 bool running() { return run
; }
27 void set_pcr(int which
, reg_t val
);
28 reg_t
get_pcr(int which
);
32 mmu_t
& mmu
; // main memory is always accessed via the mmu
34 // user-visible architected state
35 regfile_t
<reg_t
, NXPR
, true> XPR
;
36 regfile_t
<freg_t
, NFPR
, false> FPR
;
42 // privileged control registers
51 uint32_t interrupts_pending
;
53 uint32_t sr
; // only modify the status register using set_pcr()
58 // # of bits in an XPR (32 or 64). (redundant with sr)
64 void take_interrupt(); // take a trap if any interrupts are pending
65 void set_fsr(uint32_t val
); // set the floating-point status register
66 void take_trap(reg_t t
, bool noisy
); // take an exception
67 void disasm(insn_t insn
, reg_t pc
); // disassemble and print an instruction
71 void setvl(int vlapp
);
74 uint32_t vecbanks_count
;
83 processor_t
* uts
[MAX_UTS
];
85 // this constructor is used for each of the uts
86 processor_t(sim_t
* _sim
, mmu_t
* _mmu
, uint32_t _id
, uint32_t _utidx
);
95 #ifndef RISCV_ENABLE_RVC
97 do { if((x) & (sizeof(insn_t)-1)) \
98 { badvaddr = (x); throw trap_instruction_address_misaligned; } \
103 do { if((x) & ((sr & SR_EC) ? 1 : 3)) \
104 { badvaddr = (x); throw trap_instruction_address_misaligned; } \