f3b2f62cd69443d1eaa0c3cfd1fbb351143ebb3c
1 // See LICENSE for license details.
3 #ifndef _RISCV_PROCESSOR_H
4 #define _RISCV_PROCESSOR_H
15 typedef reg_t (*insn_func_t
)(processor_t
*, insn_t
, reg_t
);
18 // this class represents one processor in a RISC-V machine.
22 processor_t(sim_t
* _sim
, mmu_t
* _mmu
, uint32_t _id
);
25 void reset(bool value
);
26 void step(size_t n
, bool noisy
); // run for n cycles
27 void deliver_ipi(); // register an interprocessor interrupt
28 bool running() { return run
; }
29 void set_pcr(int which
, reg_t val
);
30 void set_interrupt(int which
, bool on
);
31 reg_t
get_pcr(int which
);
32 mmu_t
* get_mmu() { return &mmu
; }
36 mmu_t
& mmu
; // main memory is always accessed via the mmu
38 // user-visible architected state
39 regfile_t
<reg_t
, NXPR
, true> XPR
;
40 regfile_t
<freg_t
, NFPR
, false> FPR
;
44 // privileged control registers
54 uint32_t sr
; // only modify the status register using set_pcr()
62 void take_interrupt(); // take a trap if any interrupts are pending
63 void set_fsr(uint32_t val
); // set the floating-point status register
64 void take_trap(reg_t t
, bool noisy
); // take an exception
65 void disasm(insn_t insn
, reg_t pc
); // disassemble and print an instruction
69 void setvl(int vlapp
);
72 uint32_t vecbanks_count
;
81 processor_t
* uts
[MAX_UTS
];
83 // this constructor is used for each of the uts
84 processor_t(sim_t
* _sim
, mmu_t
* _mmu
, uint32_t _id
, uint32_t _utidx
);
88 friend class htif_isasim_t
;
93 #ifndef RISCV_ENABLE_RVC
95 do { if((x) & (sizeof(insn_t)-1)) \
96 { badvaddr = (x); throw trap_instruction_address_misaligned; } \
101 do { if((x) & ((sr & SR_EC) ? 1 : 3)) \
102 { badvaddr = (x); throw trap_instruction_address_misaligned; } \