445c17ab2206b5cc7e30af66e4e79fe432728b39
1 // See LICENSE for license details.
15 #include <sys/types.h>
17 volatile bool ctrlc_pressed
= false;
18 static void handle_signal(int sig
)
23 signal(sig
, &handle_signal
);
26 sim_t::sim_t(const char* isa
, size_t nprocs
, size_t mem_mb
, bool halted
,
27 const std::vector
<std::string
>& args
)
28 : htif_t(args
), procs(std::max(nprocs
, size_t(1))),
29 current_step(0), current_proc(0), debug(false), gdbserver(NULL
)
31 signal(SIGINT
, &handle_signal
);
32 // allocate target machine's memory, shrinking it as necessary
33 // until the allocation succeeds
34 size_t memsz0
= (size_t)mem_mb
<< 20;
35 size_t quantum
= 1L << 20;
37 memsz0
= (size_t)((sizeof(size_t) == 8 ? 4096 : 2048) - 256) << 20;
40 while ((mem
= (char*)calloc(1, memsz
)) == NULL
)
41 memsz
= (size_t)(memsz
*0.9)/quantum
*quantum
;
44 fprintf(stderr
, "warning: only got %zu bytes of target mem (wanted %zu)\n",
47 bus
.add_device(DEBUG_START
, &debug_module
);
49 debug_mmu
= new mmu_t(this, NULL
);
51 for (size_t i
= 0; i
< procs
.size(); i
++) {
52 procs
[i
] = new processor_t(isa
, this, i
, halted
);
55 rtc
.reset(new rtc_t(procs
));
61 for (size_t i
= 0; i
< procs
.size(); i
++)
67 void sim_thread_main(void* arg
)
69 ((sim_t
*)arg
)->main();
75 set_procs_debug(true);
79 if (debug
|| ctrlc_pressed
)
91 host
= context_t::current();
92 target
.init(sim_thread_main
, this);
96 void sim_t::step(size_t n
)
98 for (size_t i
= 0, steps
= 0; i
< n
; i
+= steps
)
100 steps
= std::min(n
- i
, INTERLEAVE
- current_step
);
101 procs
[current_proc
]->step(steps
);
103 current_step
+= steps
;
104 if (current_step
== INTERLEAVE
)
107 procs
[current_proc
]->yield_load_reservation();
108 if (++current_proc
== procs
.size()) {
110 rtc
->increment(INTERLEAVE
/ INSNS_PER_RTC_TICK
);
118 void sim_t::set_debug(bool value
)
123 void sim_t::set_log(bool value
)
128 void sim_t::set_histogram(bool value
)
130 histogram_enabled
= value
;
131 for (size_t i
= 0; i
< procs
.size(); i
++) {
132 procs
[i
]->set_histogram(histogram_enabled
);
136 void sim_t::set_procs_debug(bool value
)
138 for (size_t i
=0; i
< procs
.size(); i
++)
139 procs
[i
]->set_debug(value
);
142 bool sim_t::mmio_load(reg_t addr
, size_t len
, uint8_t* bytes
)
144 if (addr
+ len
< addr
)
146 return bus
.load(addr
, len
, bytes
);
149 bool sim_t::mmio_store(reg_t addr
, size_t len
, const uint8_t* bytes
)
151 if (addr
+ len
< addr
)
153 return bus
.store(addr
, len
, bytes
);
156 static std::string
dts_compile(const std::string
& dts
)
158 // Convert the DTS to DTB
162 if (pipe(dts_pipe
) != 0 || (dts_pid
= fork()) < 0) {
163 std::cerr
<< "Failed to fork dts child: " << strerror(errno
) << std::endl
;
167 // Child process to output dts
170 int step
, len
= dts
.length();
171 const char *buf
= dts
.c_str();
172 for (int done
= 0; done
< len
; done
+= step
) {
173 step
= write(dts_pipe
[1], buf
+done
, len
-done
);
175 std::cerr
<< "Failed to write dts: " << strerror(errno
) << std::endl
;
185 if (pipe(dtb_pipe
) != 0 || (dtb_pid
= fork()) < 0) {
186 std::cerr
<< "Failed to fork dtb child: " << strerror(errno
) << std::endl
;
190 // Child process to output dtb
192 dup2(dts_pipe
[0], 0);
193 dup2(dtb_pipe
[1], 1);
198 execl(DTC
, DTC
, "-O", "dtb", 0);
199 std::cerr
<< "Failed to run " DTC
": " << strerror(errno
) << std::endl
;
208 std::stringstream dtb
;
212 while ((got
= read(dtb_pipe
[0], buf
, sizeof(buf
))) > 0) {
216 std::cerr
<< "Failed to read dtb: " << strerror(errno
) << std::endl
;
223 waitpid(dts_pid
, &status
, 0);
224 if (!WIFEXITED(status
) || WEXITSTATUS(status
) != 0) {
225 std::cerr
<< "Child dts process failed" << std::endl
;
228 waitpid(dtb_pid
, &status
, 0);
229 if (!WIFEXITED(status
) || WEXITSTATUS(status
) != 0) {
230 std::cerr
<< "Child dtb process failed" << std::endl
;
237 void sim_t::make_dtb()
239 reg_t rtc_addr
= EXT_IO_BASE
;
240 bus
.add_device(rtc_addr
, rtc
.get());
242 const int align
= 0x1000;
243 reg_t cpu_addr
= rtc_addr
+ ((rtc
->size() - 1) / align
+ 1) * align
;
244 reg_t cpu_size
= align
;
246 uint32_t reset_vec
[8] = {
247 0x297 + DRAM_BASE
- DEFAULT_RSTVEC
, // reset vector
248 0x00028067, // jump straight to DRAM_BASE
249 0x00000000, // reserved
250 0, // config string pointer
251 0, 0, 0, 0 // trap vector
253 reset_vec
[3] = DEFAULT_RSTVEC
+ sizeof(reset_vec
); // config string pointer
255 std::vector
<char> rom((char*)reset_vec
, (char*)reset_vec
+ sizeof(reset_vec
));
262 " #address-cells = <2>;\n"
263 " #size-cells = <2>;\n"
264 " compatible = \"ucbbar,spike-bare-dev\";\n"
265 " model = \"ucbbar,spike-bare\";\n"
267 " #address-cells = <1>;\n"
268 " #size-cells = <0>;\n"
269 " timebase-frequency = <" << (CPU_HZ
/INSNS_PER_RTC_TICK
) << ">;\n";
270 for (size_t i
= 0; i
< procs
.size(); i
++) {
271 s
<< " CPU" << i
<< ": cpu@" << i
<< " {\n"
272 " device_type = \"cpu\";\n"
273 " reg = <" << i
<< ">;\n"
274 " status = \"okay\";\n"
275 " compatible = \"riscv\";\n"
276 " riscv,isa = \"" << procs
[i
]->isa_string
<< "\";\n"
277 " mmu-type = \"riscv," << (procs
[i
]->max_xlen
<= 32 ? "sv32" : "sv48") << "\";\n"
278 " clock-frequency = <" << CPU_HZ
<< ">;\n"
281 reg_t membs
= DRAM_BASE
;
284 " memory@" << DRAM_BASE
<< " {\n"
285 " device_type = \"memory\";\n"
286 " reg = <0x" << (membs
>> 32) << " 0x" << (membs
& (uint32_t)-1) <<
287 " 0x" << (memsz
>> 32) << " 0x" << (memsz
& (uint32_t)-1) << ">;\n"
290 " #address-cells = <2>;\n"
291 " #size-cells = <2>;\n"
292 " compatible = \"ucbbar,spike-bare-soc\";\n"
294 " clint@" << rtc_addr
<< " {\n"
295 " compatible = \"riscv,clint0\";\n"
296 " interrupts-extended = <" << std::dec
;
297 for (size_t i
= 0; i
< procs
.size(); i
++)
298 s
<< "&CPU" << i
<< " 3 &CPU" << i
<< " 7 ";
299 s
<< std::hex
<< ">;\n"
300 " reg = <0x" << (rtc_addr
>> 32) << " 0x" << (rtc_addr
& (uint32_t)-1) <<
307 std::string dtb
= dts_compile(dts
);
309 rom
.insert(rom
.end(), dtb
.begin(), dtb
.end());
310 rom
.resize((rom
.size() / align
+ 1) * align
);
312 boot_rom
.reset(new rom_device_t(rom
));
313 bus
.add_device(DEFAULT_RSTVEC
, boot_rom
.get());
323 void sim_t::read_chunk(addr_t taddr
, size_t len
, void* dst
)
326 auto data
= debug_mmu
->load_uint64(taddr
);
327 memcpy(dst
, &data
, sizeof data
);
330 void sim_t::write_chunk(addr_t taddr
, size_t len
, const void* src
)
334 memcpy(&data
, src
, sizeof data
);
335 debug_mmu
->store_uint64(taddr
, data
);