1 // See LICENSE for license details.
12 volatile bool ctrlc_pressed
= false;
13 static void handle_signal(int sig
)
18 signal(sig
, &handle_signal
);
21 sim_t::sim_t(size_t nprocs
, size_t mem_mb
, const std::vector
<std::string
>& args
)
22 : htif(new htif_isasim_t(this, args
)), procs(std::max(nprocs
, size_t(1))),
23 current_step(0), current_proc(0), debug(false)
25 signal(SIGINT
, &handle_signal
);
26 // allocate target machine's memory, shrinking it as necessary
27 // until the allocation succeeds
28 size_t memsz0
= (size_t)mem_mb
<< 20;
29 size_t quantum
= 1L << 20;
31 memsz0
= 1L << (sizeof(size_t) == 8 ? 32 : 30);
34 while ((mem
= (char*)calloc(1, memsz
)) == NULL
)
35 memsz
= memsz
*10/11/quantum
*quantum
;
38 fprintf(stderr
, "warning: only got %lu bytes of target mem (wanted %lu)\n",
39 (unsigned long)memsz
, (unsigned long)memsz0
);
41 debug_mmu
= new mmu_t(mem
, memsz
);
43 for (size_t i
= 0; i
< procs
.size(); i
++)
44 procs
[i
] = new processor_t(this, new mmu_t(mem
, memsz
), i
);
49 for (size_t i
= 0; i
< procs
.size(); i
++)
51 mmu_t
* pmmu
= procs
[i
]->get_mmu();
59 void sim_t::send_ipi(reg_t who
)
61 if (who
< procs
.size())
62 procs
[who
]->deliver_ipi();
65 reg_t
sim_t::get_scr(int which
)
69 case 0: return procs
.size();
70 case 1: return memsz
>> 20;
79 if (debug
|| ctrlc_pressed
)
84 return htif
->exit_code();
87 void sim_t::step(size_t n
)
89 for (size_t i
= 0, steps
= 0; i
< n
; i
+= steps
)
91 steps
= std::min(n
- i
, INTERLEAVE
- current_step
);
92 procs
[current_proc
]->step(steps
);
94 current_step
+= steps
;
95 if (current_step
== INTERLEAVE
)
98 procs
[current_proc
]->yield_load_reservation();
99 if (++current_proc
== procs
.size())
107 bool sim_t::running()
109 for (size_t i
= 0; i
< procs
.size(); i
++)
110 if (procs
[i
]->running())
117 procs
[0]->state
.tohost
= 1;
122 void sim_t::set_debug(bool value
)
127 void sim_t::set_procs_debug(bool value
)
129 for (size_t i
=0; i
< procs
.size(); i
++)
130 procs
[i
]->set_debug(value
);