7a10c9b4d2c9a4705cf726c0bd638e242950f7b4
1 // See LICENSE for license details.
15 #include <sys/types.h>
17 volatile bool ctrlc_pressed
= false;
18 static void handle_signal(int sig
)
23 signal(sig
, &handle_signal
);
26 sim_t::sim_t(const char* isa
, size_t nprocs
, size_t mem_mb
, bool halted
,
27 const std::vector
<std::string
>& args
)
28 : htif_t(args
), procs(std::max(nprocs
, size_t(1))),
29 current_step(0), current_proc(0), debug(false), gdbserver(NULL
)
31 signal(SIGINT
, &handle_signal
);
32 // allocate target machine's memory, shrinking it as necessary
33 // until the allocation succeeds
34 size_t memsz0
= (size_t)mem_mb
<< 20;
35 size_t quantum
= 1L << 20;
37 memsz0
= (size_t)2048 << 20;
40 while ((mem
= (char*)calloc(1, memsz
)) == NULL
)
41 memsz
= (size_t)(memsz
*0.9)/quantum
*quantum
;
44 fprintf(stderr
, "warning: only got %zu bytes of target mem (wanted %zu)\n",
47 bus
.add_device(DEBUG_START
, &debug_module
);
49 debug_mmu
= new mmu_t(this, NULL
);
51 for (size_t i
= 0; i
< procs
.size(); i
++) {
52 procs
[i
] = new processor_t(isa
, this, i
, halted
);
55 clint
.reset(new clint_t(procs
));
56 bus
.add_device(CLINT_BASE
, clint
.get());
63 for (size_t i
= 0; i
< procs
.size(); i
++)
69 void sim_thread_main(void* arg
)
71 ((sim_t
*)arg
)->main();
77 set_procs_debug(true);
81 if (debug
|| ctrlc_pressed
)
93 host
= context_t::current();
94 target
.init(sim_thread_main
, this);
98 void sim_t::step(size_t n
)
100 for (size_t i
= 0, steps
= 0; i
< n
; i
+= steps
)
102 steps
= std::min(n
- i
, INTERLEAVE
- current_step
);
103 procs
[current_proc
]->step(steps
);
105 current_step
+= steps
;
106 if (current_step
== INTERLEAVE
)
109 procs
[current_proc
]->yield_load_reservation();
110 if (++current_proc
== procs
.size()) {
112 clint
->increment(INTERLEAVE
/ INSNS_PER_RTC_TICK
);
120 void sim_t::set_debug(bool value
)
125 void sim_t::set_log(bool value
)
130 void sim_t::set_histogram(bool value
)
132 histogram_enabled
= value
;
133 for (size_t i
= 0; i
< procs
.size(); i
++) {
134 procs
[i
]->set_histogram(histogram_enabled
);
138 void sim_t::set_procs_debug(bool value
)
140 for (size_t i
=0; i
< procs
.size(); i
++)
141 procs
[i
]->set_debug(value
);
144 bool sim_t::mmio_load(reg_t addr
, size_t len
, uint8_t* bytes
)
146 if (addr
+ len
< addr
)
148 return bus
.load(addr
, len
, bytes
);
151 bool sim_t::mmio_store(reg_t addr
, size_t len
, const uint8_t* bytes
)
153 if (addr
+ len
< addr
)
155 return bus
.store(addr
, len
, bytes
);
158 static std::string
dts_compile(const std::string
& dts
)
160 // Convert the DTS to DTB
164 if (pipe(dts_pipe
) != 0 || (dts_pid
= fork()) < 0) {
165 std::cerr
<< "Failed to fork dts child: " << strerror(errno
) << std::endl
;
169 // Child process to output dts
172 int step
, len
= dts
.length();
173 const char *buf
= dts
.c_str();
174 for (int done
= 0; done
< len
; done
+= step
) {
175 step
= write(dts_pipe
[1], buf
+done
, len
-done
);
177 std::cerr
<< "Failed to write dts: " << strerror(errno
) << std::endl
;
187 if (pipe(dtb_pipe
) != 0 || (dtb_pid
= fork()) < 0) {
188 std::cerr
<< "Failed to fork dtb child: " << strerror(errno
) << std::endl
;
192 // Child process to output dtb
194 dup2(dts_pipe
[0], 0);
195 dup2(dtb_pipe
[1], 1);
200 execl(DTC
, DTC
, "-O", "dtb", 0);
201 std::cerr
<< "Failed to run " DTC
": " << strerror(errno
) << std::endl
;
210 std::stringstream dtb
;
214 while ((got
= read(dtb_pipe
[0], buf
, sizeof(buf
))) > 0) {
218 std::cerr
<< "Failed to read dtb: " << strerror(errno
) << std::endl
;
225 waitpid(dts_pid
, &status
, 0);
226 if (!WIFEXITED(status
) || WEXITSTATUS(status
) != 0) {
227 std::cerr
<< "Child dts process failed" << std::endl
;
230 waitpid(dtb_pid
, &status
, 0);
231 if (!WIFEXITED(status
) || WEXITSTATUS(status
) != 0) {
232 std::cerr
<< "Child dtb process failed" << std::endl
;
239 void sim_t::make_dtb()
241 uint32_t reset_vec
[] = {
242 0x297 + DRAM_BASE
- DEFAULT_RSTVEC
, // auipc t0, DRAM_BASE
243 0x597, // auipc a1, 0
244 0x58593, // addi a1, a1, 0
245 0xf1402573, // csrr a0,mhartid
246 0x00028067 // jalr zero, t0, 0 (jump straight to DRAM_BASE)
248 reset_vec
[2] += (sizeof(reset_vec
) - 4) << 20; // addi a1, a1, sizeof(reset_vec) - 4 = DTB start
250 std::vector
<char> rom((char*)reset_vec
, (char*)reset_vec
+ sizeof(reset_vec
));
257 " #address-cells = <2>;\n"
258 " #size-cells = <2>;\n"
259 " compatible = \"ucbbar,spike-bare-dev\";\n"
260 " model = \"ucbbar,spike-bare\";\n"
262 " #address-cells = <1>;\n"
263 " #size-cells = <0>;\n"
264 " timebase-frequency = <" << (CPU_HZ
/INSNS_PER_RTC_TICK
) << ">;\n";
265 for (size_t i
= 0; i
< procs
.size(); i
++) {
266 s
<< " CPU" << i
<< ": cpu@" << i
<< " {\n"
267 " device_type = \"cpu\";\n"
268 " reg = <" << i
<< ">;\n"
269 " status = \"okay\";\n"
270 " compatible = \"riscv\";\n"
271 " riscv,isa = \"" << procs
[i
]->isa_string
<< "\";\n"
272 " mmu-type = \"riscv," << (procs
[i
]->max_xlen
<= 32 ? "sv32" : "sv48") << "\";\n"
273 " clock-frequency = <" << CPU_HZ
<< ">;\n"
274 " CPU" << i
<< "_intc: interrupt-controller {\n"
275 " #interrupt-cells = <1>;\n"
276 " interrupt-controller;\n"
277 " compatible = \"riscv,cpu-intc\";\n"
281 reg_t membs
= DRAM_BASE
;
284 " memory@" << DRAM_BASE
<< " {\n"
285 " device_type = \"memory\";\n"
286 " reg = <0x" << (membs
>> 32) << " 0x" << (membs
& (uint32_t)-1) <<
287 " 0x" << (memsz
>> 32) << " 0x" << (memsz
& (uint32_t)-1) << ">;\n"
290 " #address-cells = <2>;\n"
291 " #size-cells = <2>;\n"
292 " compatible = \"ucbbar,spike-bare-soc\", \"simple-bus\";\n"
294 " clint@" << CLINT_BASE
<< " {\n"
295 " compatible = \"riscv,clint0\";\n"
296 " interrupts-extended = <" << std::dec
;
297 for (size_t i
= 0; i
< procs
.size(); i
++)
298 s
<< "&CPU" << i
<< "_intc 3 &CPU" << i
<< "_intc 7 ";
299 reg_t clintbs
= CLINT_BASE
;
300 reg_t clintsz
= CLINT_SIZE
;
301 s
<< std::hex
<< ">;\n"
302 " reg = <0x" << (clintbs
>> 32) << " 0x" << (clintbs
& (uint32_t)-1) <<
303 " 0x" << (clintsz
>> 32) << " 0x" << (clintsz
& (uint32_t)-1) << ">;\n"
309 std::string dtb
= dts_compile(dts
);
311 rom
.insert(rom
.end(), dtb
.begin(), dtb
.end());
312 const int align
= 0x1000;
313 rom
.resize((rom
.size() + align
- 1) / align
* align
);
315 boot_rom
.reset(new rom_device_t(rom
));
316 bus
.add_device(DEFAULT_RSTVEC
, boot_rom
.get());
326 void sim_t::read_chunk(addr_t taddr
, size_t len
, void* dst
)
329 auto data
= debug_mmu
->load_uint64(taddr
);
330 memcpy(dst
, &data
, sizeof data
);
333 void sim_t::write_chunk(addr_t taddr
, size_t len
, const void* src
)
337 memcpy(&data
, src
, sizeof data
);
338 debug_mmu
->store_uint64(taddr
, data
);