b09e7208433675f832919ce31030114a257dca5b
1 // See LICENSE for license details.
15 volatile bool ctrlc_pressed
= false;
16 static void handle_signal(int sig
)
21 signal(sig
, &handle_signal
);
24 sim_t::sim_t(const char* isa
, size_t nprocs
, size_t mem_mb
, bool halted
,
25 const std::vector
<std::string
>& args
)
26 : htif(new htif_isasim_t(this, args
)), procs(std::max(nprocs
, size_t(1))),
27 current_step(0), current_proc(0), debug(false), gdbserver(NULL
)
29 signal(SIGINT
, &handle_signal
);
30 // allocate target machine's memory, shrinking it as necessary
31 // until the allocation succeeds
32 size_t memsz0
= (size_t)mem_mb
<< 20;
33 size_t quantum
= 1L << 20;
35 memsz0
= (size_t)((sizeof(size_t) == 8 ? 4096 : 2048) - 256) << 20;
38 while ((mem
= (char*)calloc(1, memsz
)) == NULL
)
39 memsz
= (size_t)(memsz
*0.9)/quantum
*quantum
;
42 fprintf(stderr
, "warning: only got %lu bytes of target mem (wanted %lu)\n",
43 (unsigned long)memsz
, (unsigned long)memsz0
);
45 debug_mmu
= new mmu_t(this, NULL
);
47 for (size_t i
= 0; i
< procs
.size(); i
++) {
48 procs
[i
] = new processor_t(isa
, this, i
);
50 procs
[i
]->enter_debug_mode(DCSR_CAUSE_HALT
);
53 rtc
.reset(new rtc_t(procs
));
56 bus
.add_device(DEBUG_START
, &debug_module
);
61 for (size_t i
= 0; i
< procs
.size(); i
++)
70 set_procs_debug(true);
73 if (debug
|| ctrlc_pressed
)
81 return htif
->exit_code();
84 void sim_t::step(size_t n
)
86 for (size_t i
= 0, steps
= 0; i
< n
; i
+= steps
)
88 steps
= std::min(n
- i
, INTERLEAVE
- current_step
);
89 procs
[current_proc
]->step(steps
);
91 current_step
+= steps
;
92 if (current_step
== INTERLEAVE
)
95 procs
[current_proc
]->yield_load_reservation();
96 if (++current_proc
== procs
.size()) {
98 rtc
->increment(INTERLEAVE
/ INSNS_PER_RTC_TICK
);
106 bool sim_t::running()
108 for (size_t i
= 0; i
< procs
.size(); i
++)
109 if (procs
[i
]->running())
114 void sim_t::set_debug(bool value
)
119 void sim_t::set_log(bool value
)
124 void sim_t::set_histogram(bool value
)
126 histogram_enabled
= value
;
127 for (size_t i
= 0; i
< procs
.size(); i
++) {
128 procs
[i
]->set_histogram(histogram_enabled
);
132 void sim_t::set_procs_debug(bool value
)
134 for (size_t i
=0; i
< procs
.size(); i
++)
135 procs
[i
]->set_debug(value
);
138 bool sim_t::mmio_load(reg_t addr
, size_t len
, uint8_t* bytes
)
140 if (addr
+ len
< addr
)
142 return bus
.load(addr
, len
, bytes
);
145 bool sim_t::mmio_store(reg_t addr
, size_t len
, const uint8_t* bytes
)
147 if (addr
+ len
< addr
)
149 return bus
.store(addr
, len
, bytes
);
152 char* sim_t::mmio_page(reg_t addr
)
154 return bus
.page(addr
);
157 void sim_t::make_config_string()
159 reg_t rtc_addr
= EXT_IO_BASE
;
160 bus
.add_device(rtc_addr
, rtc
.get());
162 const int align
= 0x1000;
163 reg_t cpu_addr
= rtc_addr
+ ((rtc
->size() - 1) / align
+ 1) * align
;
164 reg_t cpu_size
= align
;
166 uint32_t reset_vec
[8] = {
167 0x297 + DRAM_BASE
- DEFAULT_RSTVEC
, // reset vector
168 0x00028067, // jump straight to DRAM_BASE
169 0x00000000, // reserved
170 0, // config string pointer
171 0, 0, 0, 0 // trap vector
173 reset_vec
[3] = DEFAULT_RSTVEC
+ sizeof(reset_vec
); // config string pointer
175 std::vector
<char> rom((char*)reset_vec
, (char*)reset_vec
+ sizeof(reset_vec
));
184 " addr 0x" << rtc_addr
<< ";\n"
188 " addr 0x" << DRAM_BASE
<< ";\n"
189 " size 0x" << memsz
<< ";\n"
193 for (size_t i
= 0; i
< procs
.size(); i
++) {
196 " " << "0 {\n" << // hart 0 on core i
197 " isa " << procs
[i
]->isa_string
<< ";\n"
198 " timecmp 0x" << (rtc_addr
+ 8*(1+i
)) << ";\n"
199 " ipi 0x" << cpu_addr
<< ";\n"
202 bus
.add_device(cpu_addr
, procs
[i
]);
203 cpu_addr
+= cpu_size
;
207 config_string
= s
.str();
208 rom
.insert(rom
.end(), config_string
.begin(), config_string
.end());
209 rom
.resize((rom
.size() / align
+ 1) * align
);
211 boot_rom
.reset(new rom_device_t(rom
));
212 bus
.add_device(DEFAULT_RSTVEC
, boot_rom
.get());