eb31f12d3b3a288c2311987959fecc1f550132aa
1 // See LICENSE for license details.
12 volatile bool ctrlc_pressed
= false;
13 static void handle_signal(int sig
)
18 signal(sig
, &handle_signal
);
21 sim_t::sim_t(const char* isa
, size_t nprocs
, size_t mem_mb
,
22 const std::vector
<std::string
>& args
)
23 : htif(new htif_isasim_t(this, args
)), procs(std::max(nprocs
, size_t(1))),
24 rtc(0), current_step(0), current_proc(0), debug(false)
26 signal(SIGINT
, &handle_signal
);
27 // allocate target machine's memory, shrinking it as necessary
28 // until the allocation succeeds
29 size_t memsz0
= (size_t)mem_mb
<< 20;
30 size_t quantum
= 1L << 20;
32 memsz0
= 1L << (sizeof(size_t) == 8 ? 32 : 30);
35 while ((mem
= (char*)calloc(1, memsz
)) == NULL
)
36 memsz
= memsz
*10/11/quantum
*quantum
;
39 fprintf(stderr
, "warning: only got %lu bytes of target mem (wanted %lu)\n",
40 (unsigned long)memsz
, (unsigned long)memsz0
);
42 debug_mmu
= new mmu_t(mem
, memsz
);
44 for (size_t i
= 0; i
< procs
.size(); i
++)
45 procs
[i
] = new processor_t(isa
, this, i
);
50 for (size_t i
= 0; i
< procs
.size(); i
++)
56 void sim_t::send_ipi(reg_t who
)
58 if (who
< procs
.size())
59 procs
[who
]->deliver_ipi();
62 reg_t
sim_t::get_scr(int which
)
66 case 0: return procs
.size();
67 case 1: return memsz
>> 20;
76 if (debug
|| ctrlc_pressed
)
81 return htif
->exit_code();
84 void sim_t::step(size_t n
)
86 for (size_t i
= 0, steps
= 0; i
< n
; i
+= steps
)
88 steps
= std::min(n
- i
, INTERLEAVE
- current_step
);
89 procs
[current_proc
]->step(steps
);
91 current_step
+= steps
;
92 if (current_step
== INTERLEAVE
)
95 procs
[current_proc
]->yield_load_reservation();
96 if (++current_proc
== procs
.size()) {
98 rtc
+= INTERLEAVE
/ INSNS_PER_RTC_TICK
;
106 bool sim_t::running()
108 for (size_t i
= 0; i
< procs
.size(); i
++)
109 if (procs
[i
]->running())
116 procs
[0]->state
.tohost
= 1;
121 void sim_t::set_debug(bool value
)
126 void sim_t::set_histogram(bool value
)
128 histogram_enabled
= value
;
129 for (size_t i
= 0; i
< procs
.size(); i
++) {
130 procs
[i
]->set_histogram(histogram_enabled
);
134 void sim_t::set_procs_debug(bool value
)
136 for (size_t i
=0; i
< procs
.size(); i
++)
137 procs
[i
]->set_debug(value
);