1 // See LICENSE for license details.
8 #include "debug_module.h"
9 #include <fesvr/htif.h>
10 #include <fesvr/context.h>
18 // this class encapsulates the processors and memory in a RISC-V machine.
19 class sim_t
: public htif_t
22 sim_t(const char* isa
, size_t _nprocs
, size_t mem_mb
, bool halted
,
23 const std::vector
<std::string
>& args
);
26 // run the simulation to completion
28 void set_debug(bool value
);
29 void set_log(bool value
);
30 void set_histogram(bool value
);
31 void set_procs_debug(bool value
);
32 void set_gdbserver(gdbserver_t
* gdbserver
) { this->gdbserver
= gdbserver
; }
33 const char* get_dts() { return dts
.c_str(); }
34 processor_t
* get_core(size_t i
) { return procs
.at(i
); }
37 char* mem
; // main memory
38 size_t memsz
; // memory size in bytes
39 mmu_t
* debug_mmu
; // debug port into main memory
40 std::vector
<processor_t
*> procs
;
42 std::unique_ptr
<rom_device_t
> boot_rom
;
43 std::unique_ptr
<rtc_t
> rtc
;
45 debug_module_t debug_module
;
47 processor_t
* get_core(const std::string
& i
);
48 void step(size_t n
); // step through simulation
49 static const size_t INTERLEAVE
= 5000;
50 static const size_t INSNS_PER_RTC_TICK
= 100; // 10 MHz clock for 1 BIPS core
51 static const size_t CPU_HZ
= 1000000000; // 1GHz CPU
56 bool histogram_enabled
; // provide a histogram of PCs
57 gdbserver_t
* gdbserver
;
59 // memory-mapped I/O routines
60 bool addr_is_mem(reg_t addr
) {
61 return addr
>= DRAM_BASE
&& addr
< DRAM_BASE
+ memsz
;
63 char* addr_to_mem(reg_t addr
) { return mem
+ addr
- DRAM_BASE
; }
64 reg_t
mem_to_addr(char* x
) { return x
- mem
+ DRAM_BASE
; }
65 bool mmio_load(reg_t addr
, size_t len
, uint8_t* bytes
);
66 bool mmio_store(reg_t addr
, size_t len
, const uint8_t* bytes
);
69 // presents a prompt for introspection into the simulation
72 // functions that help implement interactive()
73 void interactive_help(const std::string
& cmd
, const std::vector
<std::string
>& args
);
74 void interactive_quit(const std::string
& cmd
, const std::vector
<std::string
>& args
);
75 void interactive_run(const std::string
& cmd
, const std::vector
<std::string
>& args
, bool noisy
);
76 void interactive_run_noisy(const std::string
& cmd
, const std::vector
<std::string
>& args
);
77 void interactive_run_silent(const std::string
& cmd
, const std::vector
<std::string
>& args
);
78 void interactive_reg(const std::string
& cmd
, const std::vector
<std::string
>& args
);
79 void interactive_fregs(const std::string
& cmd
, const std::vector
<std::string
>& args
);
80 void interactive_fregd(const std::string
& cmd
, const std::vector
<std::string
>& args
);
81 void interactive_pc(const std::string
& cmd
, const std::vector
<std::string
>& args
);
82 void interactive_mem(const std::string
& cmd
, const std::vector
<std::string
>& args
);
83 void interactive_str(const std::string
& cmd
, const std::vector
<std::string
>& args
);
84 void interactive_until(const std::string
& cmd
, const std::vector
<std::string
>& args
);
85 reg_t
get_reg(const std::vector
<std::string
>& args
);
86 reg_t
get_freg(const std::vector
<std::string
>& args
);
87 reg_t
get_mem(const std::vector
<std::string
>& args
);
88 reg_t
get_pc(const std::vector
<std::string
>& args
);
90 friend class processor_t
;
92 friend class gdbserver_t
;
95 friend void sim_thread_main(void*);
102 void read_chunk(addr_t taddr
, size_t len
, void* dst
);
103 void write_chunk(addr_t taddr
, size_t len
, const void* src
);
104 size_t chunk_align() { return 8; }
105 size_t chunk_max_size() { return 8; }
108 extern volatile bool ctrlc_pressed
;