1 // See LICENSE for license details.
3 #ifndef _RISCV_SIMPLE_V_H
4 #define _RISCV_SIMPLE_V_H
8 // this table is for the CSRs (4? for RV32E, 16 for other types)
9 // it's a CAM that's used to generate 2 tables (below)
10 // just as in RV, writing to entries in this CAM *clears*
11 // all entries with a higher index
13 unsigned int type
: 1; // 0=INT, 1=FP
14 uint64_t regkey
: 5; // 5 bits
15 unsigned int elwidth
: 2; // 0=8-bit, 1=dflt, 2=dflt/2 3=dflt*2
16 uint64_t regidx
: 6; // yes 6 bits
17 unsigned int isvec
: 1; // vector=1, scalar=0
18 unsigned int packed
: 1; // Packed SIMD=1
23 extern sv_reg_csr_entry sv_csrs
[SV_CSR_SZ
];
25 // this is the "unpacked" table, generated from the CAM above
26 // there are 2 of them: one for FP, one for INT regs.
27 // one sv_reg_entry is required per FP *and* per INT reg.
28 // note that regidx is 6 bits however we actually only have
29 // 32 entries. reason: the *actual* number of registers is doubled
30 // in SV however the instruction is STILL ONLY 5 BITS.
32 unsigned int elwidth
: 2; // 0=8-bit, 1=dflt, 2=dflt/2 3=dflt*2
33 uint64_t regidx
: 6; // yes 6 bits.
34 unsigned int isvec
: 1; // vector=1, scalar=0
35 unsigned int packed
: 1; // Packed SIMD=1
36 unsigned int active
: 1; // enabled=1, disabled=0
39 // 32 entries: it's the size of the register table that needs to double
40 // (regidx=6 i.e. actual target register is indexed by 2^6)
41 extern sv_reg_entry sv_int_tb
[NXPR
];
42 extern sv_reg_entry sv_fp_tb
[NFPR
];
45 unsigned int type
: 1; // 0=INT, 1=FP
46 uint64_t regkey
: 5; // 5 bits
47 unsigned int zero
: 1; // zeroing=1, skipping=0
48 unsigned int inv
: 1; // inversion=1
49 uint64_t regidx
: 6; // 6 bits
50 unsigned int active
: 1; // enabled=1, disabled=0
53 extern sv_pred_csr_entry sv_pred_csrs
[SV_CSR_SZ
];
56 uint64_t regkey
: 5; // 5 bits
57 unsigned int zero
: 1; // zeroing=1, skipping=0
58 unsigned int inv
: 1; // inversion=1
59 uint64_t regidx
: 6; // 6 bits
60 unsigned int active
: 1; // enabled=1, disabled=0
63 // 32 entries, only integer regs are predicates.
64 extern sv_pred_entry sv_pred_tb
[NXPR
];
66 bool sv_check_reg(bool intreg
, uint64_t reg
);