2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
9 port (rs: in std_ulogic_vector(63 downto 0);
10 ra: in std_ulogic_vector(63 downto 0);
11 shift: in std_ulogic_vector(6 downto 0);
12 insn: in std_ulogic_vector(31 downto 0);
13 is_32bit: in std_ulogic;
14 right_shift: in std_ulogic;
16 clear_left: in std_ulogic;
17 clear_right: in std_ulogic;
18 sign_ext_rs: in std_ulogic;
19 result: out std_ulogic_vector(63 downto 0);
20 carry_out: out std_ulogic
24 architecture behaviour of rotator is
25 signal repl32: std_ulogic_vector(63 downto 0);
26 signal rot_count: std_ulogic_vector(5 downto 0);
27 signal rot1, rot2, rot: std_ulogic_vector(63 downto 0);
28 signal sh, mb, me: std_ulogic_vector(6 downto 0);
29 signal mr, ml: std_ulogic_vector(63 downto 0);
30 signal output_mode: std_ulogic_vector(1 downto 0);
32 -- note BE bit numbering
33 function right_mask(mask_begin: std_ulogic_vector(6 downto 0)) return std_ulogic_vector is
34 variable ret: std_ulogic_vector(63 downto 0);
36 ret := (others => '0');
38 if i >= to_integer(unsigned(mask_begin)) then
45 function left_mask(mask_end: std_ulogic_vector(6 downto 0)) return std_ulogic_vector is
46 variable ret: std_ulogic_vector(63 downto 0);
48 ret := (others => '0');
49 if mask_end(6) = '0' then
51 if i <= to_integer(unsigned(mask_end)) then
60 rotator_0: process(all)
61 variable hi32: std_ulogic_vector(31 downto 0);
63 -- First replicate bottom 32 bits to both halves if 32-bit
64 if is_32bit = '1' then
65 hi32 := rs(31 downto 0);
66 elsif sign_ext_rs = '1' then
67 -- sign extend bottom 32 bits
68 hi32 := (others => rs(31));
70 hi32 := rs(63 downto 32);
72 repl32 <= hi32 & rs(31 downto 0);
74 -- Negate shift count for right shifts
75 if right_shift = '1' then
76 rot_count <= std_ulogic_vector(- signed(shift(5 downto 0)));
78 rot_count <= shift(5 downto 0);
81 -- Rotator works in 3 stages using 2 bits of the rotate count each
82 -- time. This gives 4:1 multiplexors which is ideal for the 6-input
83 -- LUTs in the Xilinx Artix 7.
84 -- We look at the low bits of the rotate count first because they will
85 -- have less delay through the negation above.
86 -- First rotate by 0, 1, 2, or 3
87 case rot_count(1 downto 0) is
91 rot1 <= repl32(62 downto 0) & repl32(63);
93 rot1 <= repl32(61 downto 0) & repl32(63 downto 62);
95 rot1 <= repl32(60 downto 0) & repl32(63 downto 61);
97 -- Next rotate by 0, 4, 8 or 12
98 case rot_count(3 downto 2) is
102 rot2 <= rot1(59 downto 0) & rot1(63 downto 60);
104 rot2 <= rot1(55 downto 0) & rot1(63 downto 56);
106 rot2 <= rot1(51 downto 0) & rot1(63 downto 52);
108 -- Lastly rotate by 0, 16, 32 or 48
109 case rot_count(5 downto 4) is
113 rot <= rot2(47 downto 0) & rot2(63 downto 48);
115 rot <= rot2(31 downto 0) & rot2(63 downto 32);
117 rot <= rot2(15 downto 0) & rot2(63 downto 16);
120 -- Trim shift count to 6 bits for 32-bit shifts
121 sh <= (shift(6) and not is_32bit) & shift(5 downto 0);
123 -- Work out mask begin/end indexes (caution, big-endian bit numbering)
124 if clear_left = '1' then
125 if is_32bit = '1' then
126 mb <= "01" & insn(10 downto 6);
128 mb <= "0" & insn(5) & insn(10 downto 6);
130 elsif right_shift = '1' then
131 -- this is basically mb <= sh + (is_32bit? 32: 0);
132 if is_32bit = '1' then
133 mb <= sh(5) & not sh(5) & sh(4 downto 0);
138 mb <= ('0' & is_32bit & "00000");
140 if clear_right = '1' and is_32bit = '1' then
141 me <= "01" & insn(5 downto 1);
142 elsif clear_right = '1' and clear_left = '0' then
143 me <= "0" & insn(5) & insn(10 downto 6);
145 -- effectively, 63 - sh
146 me <= sh(6) & not sh(5 downto 0);
149 -- Calculate left and right masks
150 mr <= right_mask(mb);
153 -- Work out output mode
155 -- 0w for rlw*, rldic, rldicr, rldimi, where w = 1 iff mb > me
156 -- 10 for rldicl, sr[wd]
157 -- 1z for sra[wd][i], z = 1 if rs is negative
158 if (clear_left = '1' and clear_right = '0') or right_shift = '1' then
159 output_mode(1) <= '1';
160 output_mode(0) <= arith and repl32(63);
162 output_mode(1) <= '0';
163 if clear_right = '1' and unsigned(mb(5 downto 0)) > unsigned(me(5 downto 0)) then
164 output_mode(0) <= '1';
166 output_mode(0) <= '0';
170 -- Generate output from rotated input and masks
173 result <= (rot and (mr and ml)) or (ra and not (mr and ml));
175 result <= (rot and (mr or ml)) or (ra and not (mr or ml));
177 result <= rot and mr;
179 result <= rot or not mr;
182 -- Generate carry output for arithmetic shift right of negative value
183 if output_mode = "11" then
184 carry_out <= or (rs and not ml);