d4353c1b025dde0435262be9297753f539517587
[c4m-jtag.git] / rtl / vhdl / c4m_jtag_idblock.vhdl
1 -- The JTAG id and bypass handling block
2
3 library ieee;
4 use ieee.std_logic_1164.ALL;
5
6 use work.c4m_jtag.ALL;
7
8 entity c4m_jtag_idblock is
9 generic (
10 IR_WIDTH: integer := 2;
11
12 PART_NUMBER: std_logic_vector(15 downto 0);
13 VERSION: std_logic_vector(3 downto 0) := "0100";
14 MANUFACTURER: std_logic_vector(10 downto 0)
15 );
16 port (
17 -- needed TAP signals
18 TCK: in std_logic;
19 TDI: in std_logic;
20 TDO: out std_logic;
21
22 -- JTAG state
23 STATE: in TAPSTATE_TYPE;
24 NEXT_STATE: in TAPSTATE_TYPE;
25 DRSTATE: in std_logic;
26
27 -- The instruction
28 IR: in std_logic_vector(IR_WIDTH-1 downto 0)
29 );
30 end c4m_jtag_idblock;
31
32 architecture rtl of c4m_jtag_idblock is
33 constant IDCODE: std_logic_vector(31 downto 0) := VERSION & PART_NUMBER & MANUFACTURER & "1";
34
35 signal SR_ID: std_logic_vector(31 downto 0);
36 signal EN_TDO: boolean;
37
38 constant CMD_IDCODE: std_logic_vector(IR_WIDTH-1 downto 0) := c4m_jtag_cmd_idcode(IR_WIDTH);
39 constant CMD_BYPASS: std_logic_vector(IR_WIDTH-1 downto 0) := c4m_jtag_cmd_bypass(IR_WIDTH);
40 begin
41 process (TCK)
42 begin
43 if rising_edge(TCK) then
44 if DRSTATE = '1' then
45 case STATE is
46 when Capture =>
47 SR_ID <= IDCODE;
48
49 when Shift =>
50 if IR = CMD_IDCODE then
51 SR_ID(30 downto 0) <= SR_ID(31 downto 1);
52 SR_ID(31) <= TDI;
53 elsif IR = CMD_BYPASS then
54 SR_ID(0) <= TDI;
55 else
56 null;
57 end if;
58
59 when others =>
60 null;
61 end case;
62 end if;
63 end if;
64 end process;
65
66 EN_TDO <= STATE = Shift and DRSTATE = '1' and (IR = CMD_IDCODE or IR = CMD_BYPASS);
67 TDO <= SR_ID(0) when EN_TDO else
68 'Z';
69 end rtl;