3 # Create makefile dependencies for VHDL files, looking for "use work" and
4 # "entity work" declarations
9 from collections
import defaultdict
11 if len(sys
.argv
) == 1 and sys
.argv
[1] == '--help':
12 print("Usage: dependencies.py [--synth]")
17 if sys
.argv
[1] == '--synth':
21 # Look at what a file provides
22 entity
= re
.compile('entity (.*) is')
23 package
= re
.compile('package (.*) is')
25 # Look at what a file depends on
26 work
= re
.compile('use work\.([^.]+)\.')
27 entity_work
= re
.compile('entity work\.([^;]+)')
31 "dmi_dtm" : "dmi_dtm_dummy.vhdl",
32 "clock_generator" : "fpga/clk_gen_bypass.vhd",
33 "main_bram" : "fpga/main_bram.vhdl",
34 "pp_soc_uart" : "fpga/pp_soc_uart.vhd"
39 "dmi_dtm" : "dmi_dtm_xilinx.vhdl",
40 "clock_generator" : "fpga/clk_gen_bypass.vhd",
41 "main_bram" : "sim_bram.vhdl",
42 "pp_soc_uart" : "sim_uart.vhdl"
46 provides
= synth_provides
48 provides
= sim_provides
50 dependencies
= defaultdict(set)
53 with
open(filename
, 'r') as f
:
55 l
= line
.rstrip(os
.linesep
)
60 provides
[p
] = filename
66 provides
[p
] = filename
70 dependency
= m
.group(1)
71 dependencies
[filename
].add(dependency
)
73 m
= entity_work
.search(l
)
75 dependency
= m
.group(1)
76 dependencies
[filename
].add(dependency
)
80 def chase_dependencies(filename
):
81 if filename
not in dependencies
:
82 if filename
not in emitted
:
83 print("%s " % (filename
), end
="")
86 for dep
in dependencies
[filename
]:
90 print("%s " % (f
), end
="")
95 chase_dependencies("fpga/toplevel.vhdl")
96 print("fpga/toplevel.vhdl")
98 for filename
in dependencies
:
99 (basename
, suffix
) = filename
.split('.')
100 print("%s.o:" % (basename
), end
="")
101 for dependency
in dependencies
[filename
]:
102 p
= provides
[dependency
]
103 (basename2
, suffix2
) = p
.split('.')
104 print(" %s.o" % (basename2
), end
="")