3 from copy
import deepcopy
5 def pins(pingroup
, bankspec
, suffix
, offs
, bank
, mux
, spec
=None, limit
=None):
9 for name
in pingroup
[:limit
]:
11 name_
= "%s_%s" % (name
, suffix
)
14 if spec
and spec
.has_key(name
):
16 pin
= {mux
: (name_
, bank
)}
17 offs_bank
, offs_
= offs
20 idx_
+= bankspec
[bank
]
25 name_
= "%s_%s" % (name
, suffix
)
30 if not spec
.has_key(name
):
32 idx_
, mux_
, bank_
= spec
[name
]
34 #idx_ += bankspec[bank_]
35 pin
= {mux_
: (name_
, bank_
)}
42 def i2s(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None, limit
=None):
43 i2spins
= ['IISMCK', 'IISBCK', 'IISLRCK', 'IISDI']
45 i2spins
.append("IISDO%d" % i
)
46 return pins(i2spins
, bankspec
, suffix
, offs
, bank
, mux
, spec
, limit
)
48 def emmc(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
49 emmcpins
= ['MMCCMD', 'MMCCLK']
51 emmcpins
.append("MMCD%d" % i
)
52 return pins(emmcpins
, bankspec
, suffix
, offs
, bank
, mux
, spec
)
54 def sdmmc(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None,
55 start
=None, limit
=None):
56 sdmmcpins
= ['CMD', 'CLK']
58 sdmmcpins
.append("D%d" % i
)
59 sdmmcpins
= sdmmcpins
[start
:limit
]
60 sdmmcpins
= namesuffix('SD', suffix
, sdmmcpins
)
61 return pins(sdmmcpins
, bankspec
, '', offs
, bank
, mux
, spec
)
63 def spi(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
64 spipins
= namesuffix('SPI', suffix
,
65 ['CLK', 'NSS', 'MOSI', 'MISO', 'NSS'])
66 return pins(spipins
, bankspec
, '', offs
, bank
, mux
, spec
)
68 def quadspi(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None, limit
=None):
69 spipins
= namesuffix('SPI', suffix
,
70 ['CK', 'NSS', 'IO0', 'IO1', 'IO2', 'IO3'])
71 return pins(spipins
, bankspec
, '', offs
, bank
, mux
, spec
, limit
)
73 def i2c(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
74 spipins
= namesuffix('TWI', suffix
,
76 return pins(spipins
, bankspec
, '', offs
, bank
, mux
, spec
)
78 def jtag(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
79 uartpins
= namesuffix('JTAG', suffix
, ['MS', 'DI', 'DO', 'CK'])
80 return pins(uartpins
, bankspec
, '', offs
, bank
, mux
, spec
)
82 def uart(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
83 uartpins
= namesuffix('UART', suffix
, ['TX', 'RX'])
84 return pins(uartpins
, bankspec
, '', offs
, bank
, mux
, spec
)
86 def namesuffix(name
, suffix
, namelist
):
89 names
.append("%s%s_%s" % (name
, suffix
, n
))
92 def ulpi(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
93 ulpipins
= namesuffix('ULPI', suffix
, ['CK', 'DIR', 'STP', 'NXT'])
95 ulpipins
.append('ULPI%s_D%d' % (suffix
, i
))
96 return pins(ulpipins
, bankspec
, "", offs
, bank
, mux
, spec
)
98 def uartfull(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
99 uartpins
= namesuffix('UART', suffix
, ['TX', 'RX', 'CTS', 'RTS'])
100 return pins(uartpins
, bankspec
, '', offs
, bank
, mux
, spec
)
102 def rgbttl(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
103 ttlpins
= ['LCDCK', 'LCDDE', 'LCDHS', 'LCDVS']
105 ttlpins
.append("LCD%d" % i
)
106 return pins(ttlpins
, bankspec
, suffix
, offs
, bank
, mux
, spec
)
108 def rgmii(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
111 buspins
.append("RG_ERXD%d" % i
)
113 buspins
.append("RG_ETXD%d" % i
)
115 buspins
.append("RG_FB_CS%d" % i
)
116 buspins
+= ['RG_ERXCK', 'RG_ERXERR', 'RG_ERXDV',
117 'RG_EMDC', 'RG_EMDIO',
118 'RG_ETXEN', 'RG_ETXCK', 'RG_ECRS',
119 'RG_ECOL', 'RG_ETXERR']
120 return pins(buspins
, bankspec
, suffix
, offs
, bank
, mux
, spec
)
122 def flexbus1(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None, limit
=None):
125 buspins
.append("FB_AD%d" % i
)
127 buspins
.append("FB_CS%d" % i
)
128 buspins
+= ['FB_ALE', 'FB_OE', 'FB_RW', 'FB_TA', 'FB_CLK',
129 'FB_A0', 'FB_A1', 'FB_TS', 'FB_TBST',
130 'FB_TSIZ0', 'FB_TSIZ1']
132 buspins
.append("FB_BWE%d" % i
)
134 buspins
.append("FB_CS%d" % i
)
135 return pins(buspins
, bankspec
, suffix
, offs
, bank
, mux
, spec
, limit
)
137 def flexbus2(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None, limit
=None):
139 for i
in range(8,32):
140 buspins
.append("FB_AD%d" % i
)
141 return pins(buspins
, bankspec
, suffix
, offs
, bank
, mux
, spec
, limit
)
143 def sdram1(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
146 buspins
.append("SDRDQM%d" % i
)
148 buspins
.append("SDRAD%d" % i
)
150 buspins
.append("SDRDQ%d" % i
)
152 buspins
.append("SDRCS%d#" % i
)
154 buspins
.append("SDRDQ%d" % i
)
156 buspins
.append("SDRBA%d" % i
)
157 buspins
+= ['SDRCKE', 'SDRRAS#', 'SDRCAS#', 'SDRWE#',
159 return pins(buspins
, bankspec
, suffix
, offs
, bank
, mux
, spec
)
161 def sdram2(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None, limit
=None):
164 buspins
.append("SDRCS%d#" % i
)
165 for i
in range(8,32):
166 buspins
.append("SDRDQ%d" % i
)
167 return pins(buspins
, bankspec
, suffix
, offs
, bank
, mux
, spec
, limit
)
169 def mcu8080(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
172 buspins
.append("MCUD%d" % i
)
174 buspins
.append("MCUAD%d" % (i
+8))
176 buspins
.append("MCUCS%d" % i
)
178 buspins
.append("MCUNRB%d" % i
)
179 buspins
+= ['MCUCD', 'MCURD', 'MCUWR', 'MCUCLE', 'MCUALE',
181 return pins(buspins
, bankspec
, suffix
, offs
, bank
, mux
, spec
)
183 def _pinbank(bankspec
, prefix
, suffix
, offs
, bank
, gpiooffs
, gpionum
=1, mux
=1, spec
=None):
185 for i
in range(gpiooffs
, gpiooffs
+gpionum
):
186 gpiopins
.append("%s%s%d" % (prefix
, bank
, i
))
187 return pins(gpiopins
, bankspec
, suffix
, offs
, bank
, mux
, spec
)
189 def eint(bankspec
, suffix
, offs
, bank
, gpiooffs
, gpionum
=1, mux
=1, spec
=None):
191 for i
in range(gpiooffs
, gpiooffs
+gpionum
):
192 gpiopins
.append("EINT%d" % (i
))
193 return pins(gpiopins
, bankspec
, suffix
, offs
, bank
, mux
, spec
)
195 def pwm(bankspec
, suffix
, offs
, bank
, mux
=1, spec
=None):
196 return pins(['PWM', ], bankspec
, suffix
, offs
, bank
, mux
, spec
)
198 def gpio(bankspec
, suffix
, offs
, bank
, gpiooffs
, gpionum
=1, mux
=1, spec
=None):
199 return _pinbank(bankspec
, "GPIO", suffix
, offs
, bank
, gpiooffs
,
200 gpionum
, mux
=0, spec
=None)
203 print "| Pin | Mux0 | Mux1 | Mux2 | Mux3 |"
204 print "| --- | ----------- | ----------- | ----------- | ----------- |"
209 res
= '| %3d |' % pin
211 if not pdata
.has_key(mux
):
214 name
, bank
= pdata
[mux
]
215 res
+= " %s %-9s |" % (bank
, name
)
221 if not f
.startswith('FB_'):
225 return f2
[0], int(f2
[1])
228 while f
and not f
[0].isdigit():
231 return a
, int(f
) if f
else None
241 def find_fn(fname
, names
):
243 if fname
.startswith(n
):
246 def display_fns(bankspec
, pins
, function_names
):
247 fn_names
= function_names
.keys()
249 for (pin
, pdata
) in pins
.items():
250 for mux
in range(1,4): # skip GPIO for now
251 if not pdata
.has_key(mux
):
253 name
, bank
= pdata
[mux
]
254 if not fns
.has_key(name
):
256 fns
[name
].append((pin
-bankspec
[bank
], mux
, bank
))
262 fnbase
= find_fn(fname
, fn_names
)
264 if fnbase
!= current_fn
:
265 if current_fn
is not None:
267 print "## %s" % fnbase
269 print function_names
[fnbase
]
272 print "* %-9s :" % fname
,
273 for (pin
, mux
, bank
) in fns
[fname
]:
274 print "%s%d/%d" % (bank
, pin
, mux
),
279 def check_functions(title
, bankspec
, fns
, pins
, required
, eint
, pwm
,
282 pins
= deepcopy(pins
)
283 if descriptions
is None:
286 print "# Pinmap for %s" % title
290 for name
in required
:
293 if descriptions
and descriptions
.has_key(name
):
294 print descriptions
[name
]
297 name
= name
.split(':')
299 findbank
= name
[0][0]
300 findmux
= int(name
[0][1:])
306 name
= name
.split('/')
317 if not fname
.startswith(name
):
319 for pin
, mux
, bank
in fns
[fname
]:
320 if findbank
is not None:
325 pin_
= pin
+ bankspec
[bank
]
326 if pins
.has_key(pin_
):
327 pinfound
[pin_
] = (fname
, pin_
, bank
, pin
, mux
)
329 pinidx
= pinfound
.keys()
333 fname
, pin_
, bank
, pin
, mux
= pinfound
[pin_
]
337 if len(found
) > count
:
340 print "* %s %d %s%d/%d" % (fname
, pin_
, bank
, pin
, mux
)
346 for name
in descriptions
.keys():
347 if not name
.startswith('GPIO'):
362 if descriptions
and descriptions
.has_key(fname
):
363 desc
= ': %s' % descriptions
[fname
]
366 pin_
= pin
+ bankspec
[bank
]
367 if not pins
.has_key(pin_
):
371 print "* %-8s %d %s%-2d %s" % (fname
, pin_
, bank
, pin
, desc
)
375 display_group(bankspec
, "EINT", eint
, fns
, pins
, descriptions
)
377 display_group(bankspec
, "PWM", pwm
, fns
, pins
, descriptions
)
379 print "## Unused Pinouts (spare as GPIO) for '%s'" % title
381 if descriptions
and descriptions
.has_key('GPIO'):
382 print descriptions
['GPIO']
389 def display_group(bankspec
, title
, todisplay
, fns
, pins
, descriptions
):
390 print "## %s" % title
394 for fname
in todisplay
:
396 if descriptions
and descriptions
.has_key(fname
):
397 desc
= ': %s' % descriptions
[fname
]
398 fname
= fname
.split(':')
400 findbank
= fname
[0][0]
401 findmux
= int(fname
[0][1:])
407 for (pin
, mux
, bank
) in fns
[fname
]:
408 if findbank
is not None:
415 pin_
= pin
+ bankspec
[bank
]
416 if not pins
.has_key(pin_
):
420 print "* %s %d %s%d/%d %s" % (fname
, pin_
, bank
, pin
, mux
, desc
)
423 def pinmerge(pins
, fn
):
424 for (pinidx
, v
) in fn
.items():
425 if not pins
.has_key(pinidx
):
428 pins
[pinidx
].update(v
)
430 def display_fixed(fixed
, offs
):
435 for pin
, k
in enumerate(fkeys
):
440 for name
in fixed
[k
]:
444 if prevname
[:2] == name
[:2] and linecount
!= 0:
450 print "* %d: %d %s" % (pin_
, pin
, name
),