4 * PHY (to be determined)
13 ![UTMI_interface](https://www.crifan.com/files/pic/serial_story/other_site/p_blog_bb.JPG)
15 ![UTMI+levels](https://www.crifan.com/files/pic/serial_story/other_site/p_blog_aa.JPG)
17 ![UTMI+level3_interface](https://www.crifan.com/files/pic/serial_story/other_site/p_blog_cc.JPG)
19 ![LPI_signals](https://www.crifan.com/files/pic/serial_story/other_site/p_blog_dd.JPG)
21 ![LPI_signals_table](https://www.crifan.com/files/pic/serial_story/other_site/p_blog_dd.JPG)
24 * <https://opencores.org/project,ulpi_wrapper> (GPL'd)
25 * <https://github.com/mossmann/daisho/blob/master/sw/fpga/common/usb3/usb2_ulpi.v> (BSD)
26 * <https://opencores.org/project,usb>
27 * <https://github.com/alexforencich/verilog-wishbone>
28 * <https://github.com/www-asics-ws/usb2_dev>