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[libreriscv.git] / shakti / m_class / wishbone.mdwn
1 # Wishbone Bridge
2
3 See also [[AXI]] Bus
4 * <http://bugs.libre-riscv.org/show_bug.cgi?id=11>
5 * <https://github.com/alexforencich/verilog-wishbone>
http://libre-riscv.org ikiwiki