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[mesa.git] / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "util/u_pack_color.h"
31 #include "tgsi/tgsi_parse.h"
32 #include "radeonsi_pipe.h"
33 #include "radeonsi_shader.h"
34 #include "si_state.h"
35 #include "sid.h"
36
37 /*
38 * inferred framebuffer and blender state
39 */
40 static void si_update_fb_blend_state(struct r600_context *rctx)
41 {
42 struct si_pm4_state *pm4;
43 struct si_state_blend *blend = rctx->queued.named.blend;
44 uint32_t mask;
45
46 if (blend == NULL)
47 return;
48
49 pm4 = CALLOC_STRUCT(si_pm4_state);
50 if (pm4 == NULL)
51 return;
52
53 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
54 mask &= blend->cb_target_mask;
55 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
56
57 si_pm4_set_state(rctx, fb_blend, pm4);
58 }
59
60 /*
61 * Blender functions
62 */
63
64 static uint32_t si_translate_blend_function(int blend_func)
65 {
66 switch (blend_func) {
67 case PIPE_BLEND_ADD:
68 return V_028780_COMB_DST_PLUS_SRC;
69 case PIPE_BLEND_SUBTRACT:
70 return V_028780_COMB_SRC_MINUS_DST;
71 case PIPE_BLEND_REVERSE_SUBTRACT:
72 return V_028780_COMB_DST_MINUS_SRC;
73 case PIPE_BLEND_MIN:
74 return V_028780_COMB_MIN_DST_SRC;
75 case PIPE_BLEND_MAX:
76 return V_028780_COMB_MAX_DST_SRC;
77 default:
78 R600_ERR("Unknown blend function %d\n", blend_func);
79 assert(0);
80 break;
81 }
82 return 0;
83 }
84
85 static uint32_t si_translate_blend_factor(int blend_fact)
86 {
87 switch (blend_fact) {
88 case PIPE_BLENDFACTOR_ONE:
89 return V_028780_BLEND_ONE;
90 case PIPE_BLENDFACTOR_SRC_COLOR:
91 return V_028780_BLEND_SRC_COLOR;
92 case PIPE_BLENDFACTOR_SRC_ALPHA:
93 return V_028780_BLEND_SRC_ALPHA;
94 case PIPE_BLENDFACTOR_DST_ALPHA:
95 return V_028780_BLEND_DST_ALPHA;
96 case PIPE_BLENDFACTOR_DST_COLOR:
97 return V_028780_BLEND_DST_COLOR;
98 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
99 return V_028780_BLEND_SRC_ALPHA_SATURATE;
100 case PIPE_BLENDFACTOR_CONST_COLOR:
101 return V_028780_BLEND_CONSTANT_COLOR;
102 case PIPE_BLENDFACTOR_CONST_ALPHA:
103 return V_028780_BLEND_CONSTANT_ALPHA;
104 case PIPE_BLENDFACTOR_ZERO:
105 return V_028780_BLEND_ZERO;
106 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
107 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
108 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
109 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
110 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
111 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
112 case PIPE_BLENDFACTOR_INV_DST_COLOR:
113 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
114 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
115 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
116 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
117 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
118 case PIPE_BLENDFACTOR_SRC1_COLOR:
119 return V_028780_BLEND_SRC1_COLOR;
120 case PIPE_BLENDFACTOR_SRC1_ALPHA:
121 return V_028780_BLEND_SRC1_ALPHA;
122 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
123 return V_028780_BLEND_INV_SRC1_COLOR;
124 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
125 return V_028780_BLEND_INV_SRC1_ALPHA;
126 default:
127 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
128 assert(0);
129 break;
130 }
131 return 0;
132 }
133
134 static void *si_create_blend_state(struct pipe_context *ctx,
135 const struct pipe_blend_state *state)
136 {
137 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
138 struct si_pm4_state *pm4 = &blend->pm4;
139
140 uint32_t color_control;
141
142 if (blend == NULL)
143 return NULL;
144
145 color_control = S_028808_MODE(V_028808_CB_NORMAL);
146 if (state->logicop_enable) {
147 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
148 } else {
149 color_control |= S_028808_ROP3(0xcc);
150 }
151 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
152
153 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, ~0);
154 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, ~0);
155
156 blend->cb_target_mask = 0;
157 for (int i = 0; i < 8; i++) {
158 /* state->rt entries > 0 only written if independent blending */
159 const int j = state->independent_blend_enable ? i : 0;
160
161 unsigned eqRGB = state->rt[j].rgb_func;
162 unsigned srcRGB = state->rt[j].rgb_src_factor;
163 unsigned dstRGB = state->rt[j].rgb_dst_factor;
164 unsigned eqA = state->rt[j].alpha_func;
165 unsigned srcA = state->rt[j].alpha_src_factor;
166 unsigned dstA = state->rt[j].alpha_dst_factor;
167
168 unsigned blend_cntl = 0;
169
170 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
171 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
172
173 if (!state->rt[j].blend_enable) {
174 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
175 continue;
176 }
177
178 blend_cntl |= S_028780_ENABLE(1);
179 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
180 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
181 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
182
183 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
184 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
185 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
186 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
187 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
188 }
189 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
190 }
191
192 return blend;
193 }
194
195 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
196 {
197 struct r600_context *rctx = (struct r600_context *)ctx;
198 si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state);
199 si_update_fb_blend_state(rctx);
200 }
201
202 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
203 {
204 struct r600_context *rctx = (struct r600_context *)ctx;
205 si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state);
206 }
207
208 static void si_set_blend_color(struct pipe_context *ctx,
209 const struct pipe_blend_color *state)
210 {
211 struct r600_context *rctx = (struct r600_context *)ctx;
212 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
213
214 if (pm4 == NULL)
215 return;
216
217 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
218 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
219 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
220 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
221
222 si_pm4_set_state(rctx, blend_color, pm4);
223 }
224
225 /*
226 * Clipping, scissors and viewport
227 */
228
229 static void si_set_clip_state(struct pipe_context *ctx,
230 const struct pipe_clip_state *state)
231 {
232 struct r600_context *rctx = (struct r600_context *)ctx;
233 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
234
235 if (pm4 == NULL)
236 return;
237
238 for (int i = 0; i < 6; i++) {
239 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
240 fui(state->ucp[i][0]));
241 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
242 fui(state->ucp[i][1]));
243 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
244 fui(state->ucp[i][2]));
245 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
246 fui(state->ucp[i][3]));
247 }
248
249 si_pm4_set_state(rctx, clip, pm4);
250 }
251
252 static void si_set_scissor_state(struct pipe_context *ctx,
253 const struct pipe_scissor_state *state)
254 {
255 struct r600_context *rctx = (struct r600_context *)ctx;
256 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
257 uint32_t tl, br;
258
259 if (pm4 == NULL)
260 return;
261
262 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
263 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
264 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl);
265 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br);
266 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl);
267 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br);
268 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl);
269 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br);
270 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl);
271 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br);
272
273 si_pm4_set_state(rctx, scissor, pm4);
274 }
275
276 static void si_set_viewport_state(struct pipe_context *ctx,
277 const struct pipe_viewport_state *state)
278 {
279 struct r600_context *rctx = (struct r600_context *)ctx;
280 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
281 struct si_pm4_state *pm4 = &viewport->pm4;
282
283 if (viewport == NULL)
284 return;
285
286 viewport->viewport = *state;
287 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
288 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
289 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
290 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
291 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
292 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
293 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
294 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
295 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
296 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
297
298 si_pm4_set_state(rctx, viewport, viewport);
299 }
300
301 /*
302 * inferred state between framebuffer and rasterizer
303 */
304 static void si_update_fb_rs_state(struct r600_context *rctx)
305 {
306 struct si_state_rasterizer *rs = rctx->queued.named.rasterizer;
307 struct si_pm4_state *pm4;
308 unsigned offset_db_fmt_cntl = 0, depth;
309 float offset_units;
310
311 if (!rs || !rctx->framebuffer.zsbuf)
312 return;
313
314 offset_units = rctx->queued.named.rasterizer->offset_units;
315 switch (rctx->framebuffer.zsbuf->texture->format) {
316 case PIPE_FORMAT_Z24X8_UNORM:
317 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
318 depth = -24;
319 offset_units *= 2.0f;
320 break;
321 case PIPE_FORMAT_Z32_FLOAT:
322 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
323 depth = -23;
324 offset_units *= 1.0f;
325 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
326 break;
327 case PIPE_FORMAT_Z16_UNORM:
328 depth = -16;
329 offset_units *= 4.0f;
330 break;
331 default:
332 return;
333 }
334
335 pm4 = CALLOC_STRUCT(si_pm4_state);
336 /* FIXME some of those reg can be computed with cso */
337 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
338 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
339 fui(rctx->queued.named.rasterizer->offset_scale));
340 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
341 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
342 fui(rctx->queued.named.rasterizer->offset_scale));
343 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
344 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl);
345
346 si_pm4_set_state(rctx, fb_rs, pm4);
347 }
348
349 /*
350 * Rasterizer
351 */
352
353 static uint32_t si_translate_fill(uint32_t func)
354 {
355 switch(func) {
356 case PIPE_POLYGON_MODE_FILL:
357 return V_028814_X_DRAW_TRIANGLES;
358 case PIPE_POLYGON_MODE_LINE:
359 return V_028814_X_DRAW_LINES;
360 case PIPE_POLYGON_MODE_POINT:
361 return V_028814_X_DRAW_POINTS;
362 default:
363 assert(0);
364 return V_028814_X_DRAW_POINTS;
365 }
366 }
367
368 static void *si_create_rs_state(struct pipe_context *ctx,
369 const struct pipe_rasterizer_state *state)
370 {
371 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
372 struct si_pm4_state *pm4 = &rs->pm4;
373 unsigned tmp;
374 unsigned prov_vtx = 1, polygon_dual_mode;
375 unsigned clip_rule;
376 float psize_min, psize_max;
377
378 if (rs == NULL) {
379 return NULL;
380 }
381
382 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
383 state->fill_back != PIPE_POLYGON_MODE_FILL);
384
385 if (state->flatshade_first)
386 prov_vtx = 0;
387
388 rs->flatshade = state->flatshade;
389 rs->sprite_coord_enable = state->sprite_coord_enable;
390 rs->pa_sc_line_stipple = state->line_stipple_enable ?
391 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
392 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
393 rs->pa_su_sc_mode_cntl =
394 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
395 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
396 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
397 S_028814_FACE(!state->front_ccw) |
398 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
399 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
400 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
401 S_028814_POLY_MODE(polygon_dual_mode) |
402 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
403 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
404 rs->pa_cl_clip_cntl =
405 S_028810_PS_UCP_MODE(3) |
406 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
407 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
408 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
409 rs->pa_cl_vs_out_cntl =
410 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
411 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
412
413 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
414
415 /* offset */
416 rs->offset_units = state->offset_units;
417 rs->offset_scale = state->offset_scale * 12.0f;
418
419 /* XXX: Flat shading hangs the GPU */
420 tmp = S_0286D4_FLAT_SHADE_ENA(0);
421 if (state->sprite_coord_enable) {
422 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
423 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
424 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
425 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
426 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
427 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
428 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
429 }
430 }
431 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
432
433 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
434 /* point size 12.4 fixed point */
435 tmp = (unsigned)(state->point_size * 8.0);
436 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
437
438 if (state->point_size_per_vertex) {
439 psize_min = util_get_min_point_size(state);
440 psize_max = 8192;
441 } else {
442 /* Force the point size to be as if the vertex output was disabled. */
443 psize_min = state->point_size;
444 psize_max = state->point_size;
445 }
446 /* Divide by two, because 0.5 = 1 pixel. */
447 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
448 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
449 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
450
451 tmp = (unsigned)state->line_width * 8;
452 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
453 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
454 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
455
456 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, 0x00000400);
457 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
458 S_028BE4_PIX_CENTER(state->gl_rasterization_rules));
459 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
460 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
461 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
462 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
463
464 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
465 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule);
466
467 return rs;
468 }
469
470 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
471 {
472 struct r600_context *rctx = (struct r600_context *)ctx;
473 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
474
475 if (state == NULL)
476 return;
477
478 // TODO
479 rctx->sprite_coord_enable = rs->sprite_coord_enable;
480 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
481 rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
482 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
483 rctx->pa_cl_vs_out_cntl = rs->pa_cl_vs_out_cntl;
484
485 si_pm4_bind_state(rctx, rasterizer, rs);
486 si_update_fb_rs_state(rctx);
487 }
488
489 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
490 {
491 struct r600_context *rctx = (struct r600_context *)ctx;
492 si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state);
493 }
494
495 /*
496 * infeered state between dsa and stencil ref
497 */
498 static void si_update_dsa_stencil_ref(struct r600_context *rctx)
499 {
500 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
501 struct pipe_stencil_ref *ref = &rctx->stencil_ref;
502 struct si_state_dsa *dsa = rctx->queued.named.dsa;
503
504 if (pm4 == NULL)
505 return;
506
507 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
508 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
509 S_028430_STENCILMASK(dsa->valuemask[0]) |
510 S_028430_STENCILWRITEMASK(dsa->writemask[0]));
511 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
512 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
513 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
514 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]));
515
516 si_pm4_set_state(rctx, dsa_stencil_ref, pm4);
517 }
518
519 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
520 const struct pipe_stencil_ref *state)
521 {
522 struct r600_context *rctx = (struct r600_context *)ctx;
523 rctx->stencil_ref = *state;
524 si_update_dsa_stencil_ref(rctx);
525 }
526
527
528 /*
529 * DSA
530 */
531
532 static uint32_t si_translate_stencil_op(int s_op)
533 {
534 switch (s_op) {
535 case PIPE_STENCIL_OP_KEEP:
536 return V_02842C_STENCIL_KEEP;
537 case PIPE_STENCIL_OP_ZERO:
538 return V_02842C_STENCIL_ZERO;
539 case PIPE_STENCIL_OP_REPLACE:
540 return V_02842C_STENCIL_REPLACE_TEST;
541 case PIPE_STENCIL_OP_INCR:
542 return V_02842C_STENCIL_ADD_CLAMP;
543 case PIPE_STENCIL_OP_DECR:
544 return V_02842C_STENCIL_SUB_CLAMP;
545 case PIPE_STENCIL_OP_INCR_WRAP:
546 return V_02842C_STENCIL_ADD_WRAP;
547 case PIPE_STENCIL_OP_DECR_WRAP:
548 return V_02842C_STENCIL_SUB_WRAP;
549 case PIPE_STENCIL_OP_INVERT:
550 return V_02842C_STENCIL_INVERT;
551 default:
552 R600_ERR("Unknown stencil op %d", s_op);
553 assert(0);
554 break;
555 }
556 return 0;
557 }
558
559 static void *si_create_dsa_state(struct pipe_context *ctx,
560 const struct pipe_depth_stencil_alpha_state *state)
561 {
562 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
563 struct si_pm4_state *pm4 = &dsa->pm4;
564 unsigned db_depth_control, /* alpha_test_control, */ alpha_ref;
565 unsigned db_render_override, db_render_control;
566 uint32_t db_stencil_control = 0;
567
568 if (dsa == NULL) {
569 return NULL;
570 }
571
572 dsa->valuemask[0] = state->stencil[0].valuemask;
573 dsa->valuemask[1] = state->stencil[1].valuemask;
574 dsa->writemask[0] = state->stencil[0].writemask;
575 dsa->writemask[1] = state->stencil[1].writemask;
576
577 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
578 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
579 S_028800_ZFUNC(state->depth.func);
580
581 /* stencil */
582 if (state->stencil[0].enabled) {
583 db_depth_control |= S_028800_STENCIL_ENABLE(1);
584 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
585 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
586 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
587 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
588
589 if (state->stencil[1].enabled) {
590 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
591 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
592 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
593 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
594 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
595 }
596 }
597
598 /* alpha */
599 //alpha_test_control = 0;
600 alpha_ref = 0;
601 if (state->alpha.enabled) {
602 //alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
603 //alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
604 alpha_ref = fui(state->alpha.ref_value);
605 }
606 dsa->alpha_ref = alpha_ref;
607
608 /* misc */
609 db_render_control = 0;
610 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
611 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
612 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
613 /* TODO db_render_override depends on query */
614 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
615 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
616 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
617 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
618 //si_pm4_set_reg(pm4, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control);
619 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
620 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
621 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
622 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
623 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
624 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
625 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
626 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
627 dsa->db_render_override = db_render_override;
628
629 return dsa;
630 }
631
632 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
633 {
634 struct r600_context *rctx = (struct r600_context *)ctx;
635 struct si_state_dsa *dsa = state;
636
637 if (state == NULL)
638 return;
639
640 si_pm4_bind_state(rctx, dsa, dsa);
641 si_update_dsa_stencil_ref(rctx);
642
643 // TODO
644 rctx->alpha_ref = dsa->alpha_ref;
645 rctx->alpha_ref_dirty = true;
646 }
647
648 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
649 {
650 struct r600_context *rctx = (struct r600_context *)ctx;
651 si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state);
652 }
653
654 static void *si_create_db_flush_dsa(struct r600_context *rctx)
655 {
656 struct pipe_depth_stencil_alpha_state dsa;
657 struct si_state_dsa *state;
658
659 memset(&dsa, 0, sizeof(dsa));
660
661 state = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
662 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
663 S_028000_DEPTH_COPY(1) |
664 S_028000_STENCIL_COPY(1) |
665 S_028000_COPY_CENTROID(1));
666 return state;
667 }
668
669 /*
670 * format translation
671 */
672 static uint32_t si_translate_colorformat(enum pipe_format format)
673 {
674 switch (format) {
675 /* 8-bit buffers. */
676 case PIPE_FORMAT_A8_UNORM:
677 case PIPE_FORMAT_A8_UINT:
678 case PIPE_FORMAT_A8_SINT:
679 case PIPE_FORMAT_I8_UNORM:
680 case PIPE_FORMAT_I8_UINT:
681 case PIPE_FORMAT_I8_SINT:
682 case PIPE_FORMAT_L8_UNORM:
683 case PIPE_FORMAT_L8_UINT:
684 case PIPE_FORMAT_L8_SINT:
685 case PIPE_FORMAT_L8_SRGB:
686 case PIPE_FORMAT_R8_UNORM:
687 case PIPE_FORMAT_R8_SNORM:
688 case PIPE_FORMAT_R8_UINT:
689 case PIPE_FORMAT_R8_SINT:
690 return V_028C70_COLOR_8;
691
692 /* 16-bit buffers. */
693 case PIPE_FORMAT_B5G6R5_UNORM:
694 return V_028C70_COLOR_5_6_5;
695
696 case PIPE_FORMAT_B5G5R5A1_UNORM:
697 case PIPE_FORMAT_B5G5R5X1_UNORM:
698 return V_028C70_COLOR_1_5_5_5;
699
700 case PIPE_FORMAT_B4G4R4A4_UNORM:
701 case PIPE_FORMAT_B4G4R4X4_UNORM:
702 return V_028C70_COLOR_4_4_4_4;
703
704 case PIPE_FORMAT_L8A8_UNORM:
705 case PIPE_FORMAT_L8A8_UINT:
706 case PIPE_FORMAT_L8A8_SINT:
707 case PIPE_FORMAT_L8A8_SRGB:
708 case PIPE_FORMAT_R8G8_UNORM:
709 case PIPE_FORMAT_R8G8_UINT:
710 case PIPE_FORMAT_R8G8_SINT:
711 return V_028C70_COLOR_8_8;
712
713 case PIPE_FORMAT_Z16_UNORM:
714 case PIPE_FORMAT_R16_UNORM:
715 case PIPE_FORMAT_R16_UINT:
716 case PIPE_FORMAT_R16_SINT:
717 case PIPE_FORMAT_R16_FLOAT:
718 case PIPE_FORMAT_R16G16_FLOAT:
719 return V_028C70_COLOR_16;
720
721 /* 32-bit buffers. */
722 case PIPE_FORMAT_A8B8G8R8_SRGB:
723 case PIPE_FORMAT_A8B8G8R8_UNORM:
724 case PIPE_FORMAT_A8R8G8B8_UNORM:
725 case PIPE_FORMAT_B8G8R8A8_SRGB:
726 case PIPE_FORMAT_B8G8R8A8_UNORM:
727 case PIPE_FORMAT_B8G8R8X8_UNORM:
728 case PIPE_FORMAT_R8G8B8A8_SNORM:
729 case PIPE_FORMAT_R8G8B8A8_UNORM:
730 case PIPE_FORMAT_R8G8B8X8_UNORM:
731 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
732 case PIPE_FORMAT_X8B8G8R8_UNORM:
733 case PIPE_FORMAT_X8R8G8B8_UNORM:
734 case PIPE_FORMAT_R8G8B8_UNORM:
735 case PIPE_FORMAT_R8G8B8A8_SSCALED:
736 case PIPE_FORMAT_R8G8B8A8_USCALED:
737 case PIPE_FORMAT_R8G8B8A8_SINT:
738 case PIPE_FORMAT_R8G8B8A8_UINT:
739 return V_028C70_COLOR_8_8_8_8;
740
741 case PIPE_FORMAT_R10G10B10A2_UNORM:
742 case PIPE_FORMAT_R10G10B10X2_SNORM:
743 case PIPE_FORMAT_B10G10R10A2_UNORM:
744 case PIPE_FORMAT_B10G10R10A2_UINT:
745 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
746 return V_028C70_COLOR_2_10_10_10;
747
748 case PIPE_FORMAT_Z24X8_UNORM:
749 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
750 return V_028C70_COLOR_8_24;
751
752 case PIPE_FORMAT_X8Z24_UNORM:
753 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
754 return V_028C70_COLOR_24_8;
755
756 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
757 return V_028C70_COLOR_X24_8_32_FLOAT;
758
759 case PIPE_FORMAT_R32_FLOAT:
760 case PIPE_FORMAT_Z32_FLOAT:
761 return V_028C70_COLOR_32;
762
763 case PIPE_FORMAT_R16G16_SSCALED:
764 case PIPE_FORMAT_R16G16_UNORM:
765 case PIPE_FORMAT_R16G16_UINT:
766 case PIPE_FORMAT_R16G16_SINT:
767 return V_028C70_COLOR_16_16;
768
769 case PIPE_FORMAT_R11G11B10_FLOAT:
770 return V_028C70_COLOR_10_11_11;
771
772 /* 64-bit buffers. */
773 case PIPE_FORMAT_R16G16B16_USCALED:
774 case PIPE_FORMAT_R16G16B16_SSCALED:
775 case PIPE_FORMAT_R16G16B16A16_UINT:
776 case PIPE_FORMAT_R16G16B16A16_SINT:
777 case PIPE_FORMAT_R16G16B16A16_USCALED:
778 case PIPE_FORMAT_R16G16B16A16_SSCALED:
779 case PIPE_FORMAT_R16G16B16A16_UNORM:
780 case PIPE_FORMAT_R16G16B16A16_SNORM:
781 case PIPE_FORMAT_R16G16B16_FLOAT:
782 case PIPE_FORMAT_R16G16B16A16_FLOAT:
783 return V_028C70_COLOR_16_16_16_16;
784
785 case PIPE_FORMAT_R32G32_FLOAT:
786 case PIPE_FORMAT_R32G32_USCALED:
787 case PIPE_FORMAT_R32G32_SSCALED:
788 case PIPE_FORMAT_R32G32_SINT:
789 case PIPE_FORMAT_R32G32_UINT:
790 return V_028C70_COLOR_32_32;
791
792 /* 128-bit buffers. */
793 case PIPE_FORMAT_R32G32B32A32_SNORM:
794 case PIPE_FORMAT_R32G32B32A32_UNORM:
795 case PIPE_FORMAT_R32G32B32A32_SSCALED:
796 case PIPE_FORMAT_R32G32B32A32_USCALED:
797 case PIPE_FORMAT_R32G32B32A32_SINT:
798 case PIPE_FORMAT_R32G32B32A32_UINT:
799 case PIPE_FORMAT_R32G32B32A32_FLOAT:
800 return V_028C70_COLOR_32_32_32_32;
801
802 /* YUV buffers. */
803 case PIPE_FORMAT_UYVY:
804 case PIPE_FORMAT_YUYV:
805 /* 96-bit buffers. */
806 case PIPE_FORMAT_R32G32B32_FLOAT:
807 /* 8-bit buffers. */
808 case PIPE_FORMAT_L4A4_UNORM:
809 case PIPE_FORMAT_R4A4_UNORM:
810 case PIPE_FORMAT_A4R4_UNORM:
811 default:
812 return ~0U; /* Unsupported. */
813 }
814 }
815
816 static uint32_t si_translate_colorswap(enum pipe_format format)
817 {
818 switch (format) {
819 /* 8-bit buffers. */
820 case PIPE_FORMAT_L4A4_UNORM:
821 case PIPE_FORMAT_A4R4_UNORM:
822 return V_028C70_SWAP_ALT;
823
824 case PIPE_FORMAT_A8_UNORM:
825 case PIPE_FORMAT_A8_UINT:
826 case PIPE_FORMAT_A8_SINT:
827 case PIPE_FORMAT_R4A4_UNORM:
828 return V_028C70_SWAP_ALT_REV;
829 case PIPE_FORMAT_I8_UNORM:
830 case PIPE_FORMAT_L8_UNORM:
831 case PIPE_FORMAT_I8_UINT:
832 case PIPE_FORMAT_I8_SINT:
833 case PIPE_FORMAT_L8_UINT:
834 case PIPE_FORMAT_L8_SINT:
835 case PIPE_FORMAT_L8_SRGB:
836 case PIPE_FORMAT_R8_UNORM:
837 case PIPE_FORMAT_R8_SNORM:
838 case PIPE_FORMAT_R8_UINT:
839 case PIPE_FORMAT_R8_SINT:
840 return V_028C70_SWAP_STD;
841
842 /* 16-bit buffers. */
843 case PIPE_FORMAT_B5G6R5_UNORM:
844 return V_028C70_SWAP_STD_REV;
845
846 case PIPE_FORMAT_B5G5R5A1_UNORM:
847 case PIPE_FORMAT_B5G5R5X1_UNORM:
848 return V_028C70_SWAP_ALT;
849
850 case PIPE_FORMAT_B4G4R4A4_UNORM:
851 case PIPE_FORMAT_B4G4R4X4_UNORM:
852 return V_028C70_SWAP_ALT;
853
854 case PIPE_FORMAT_Z16_UNORM:
855 return V_028C70_SWAP_STD;
856
857 case PIPE_FORMAT_L8A8_UNORM:
858 case PIPE_FORMAT_L8A8_UINT:
859 case PIPE_FORMAT_L8A8_SINT:
860 case PIPE_FORMAT_L8A8_SRGB:
861 return V_028C70_SWAP_ALT;
862 case PIPE_FORMAT_R8G8_UNORM:
863 case PIPE_FORMAT_R8G8_UINT:
864 case PIPE_FORMAT_R8G8_SINT:
865 return V_028C70_SWAP_STD;
866
867 case PIPE_FORMAT_R16_UNORM:
868 case PIPE_FORMAT_R16_UINT:
869 case PIPE_FORMAT_R16_SINT:
870 case PIPE_FORMAT_R16_FLOAT:
871 return V_028C70_SWAP_STD;
872
873 /* 32-bit buffers. */
874 case PIPE_FORMAT_A8B8G8R8_SRGB:
875 return V_028C70_SWAP_STD_REV;
876 case PIPE_FORMAT_B8G8R8A8_SRGB:
877 return V_028C70_SWAP_ALT;
878
879 case PIPE_FORMAT_B8G8R8A8_UNORM:
880 case PIPE_FORMAT_B8G8R8X8_UNORM:
881 return V_028C70_SWAP_ALT;
882
883 case PIPE_FORMAT_A8R8G8B8_UNORM:
884 case PIPE_FORMAT_X8R8G8B8_UNORM:
885 return V_028C70_SWAP_ALT_REV;
886 case PIPE_FORMAT_R8G8B8A8_SNORM:
887 case PIPE_FORMAT_R8G8B8A8_UNORM:
888 case PIPE_FORMAT_R8G8B8A8_SSCALED:
889 case PIPE_FORMAT_R8G8B8A8_USCALED:
890 case PIPE_FORMAT_R8G8B8A8_SINT:
891 case PIPE_FORMAT_R8G8B8A8_UINT:
892 case PIPE_FORMAT_R8G8B8X8_UNORM:
893 return V_028C70_SWAP_STD;
894
895 case PIPE_FORMAT_A8B8G8R8_UNORM:
896 case PIPE_FORMAT_X8B8G8R8_UNORM:
897 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
898 return V_028C70_SWAP_STD_REV;
899
900 case PIPE_FORMAT_Z24X8_UNORM:
901 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
902 return V_028C70_SWAP_STD;
903
904 case PIPE_FORMAT_X8Z24_UNORM:
905 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
906 return V_028C70_SWAP_STD;
907
908 case PIPE_FORMAT_R10G10B10A2_UNORM:
909 case PIPE_FORMAT_R10G10B10X2_SNORM:
910 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
911 return V_028C70_SWAP_STD;
912
913 case PIPE_FORMAT_B10G10R10A2_UNORM:
914 case PIPE_FORMAT_B10G10R10A2_UINT:
915 return V_028C70_SWAP_ALT;
916
917 case PIPE_FORMAT_R11G11B10_FLOAT:
918 case PIPE_FORMAT_R32_FLOAT:
919 case PIPE_FORMAT_R32_UINT:
920 case PIPE_FORMAT_R32_SINT:
921 case PIPE_FORMAT_Z32_FLOAT:
922 case PIPE_FORMAT_R16G16_FLOAT:
923 case PIPE_FORMAT_R16G16_UNORM:
924 case PIPE_FORMAT_R16G16_UINT:
925 case PIPE_FORMAT_R16G16_SINT:
926 return V_028C70_SWAP_STD;
927
928 /* 64-bit buffers. */
929 case PIPE_FORMAT_R32G32_FLOAT:
930 case PIPE_FORMAT_R32G32_UINT:
931 case PIPE_FORMAT_R32G32_SINT:
932 case PIPE_FORMAT_R16G16B16A16_UNORM:
933 case PIPE_FORMAT_R16G16B16A16_SNORM:
934 case PIPE_FORMAT_R16G16B16A16_USCALED:
935 case PIPE_FORMAT_R16G16B16A16_SSCALED:
936 case PIPE_FORMAT_R16G16B16A16_UINT:
937 case PIPE_FORMAT_R16G16B16A16_SINT:
938 case PIPE_FORMAT_R16G16B16A16_FLOAT:
939 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
940
941 /* 128-bit buffers. */
942 case PIPE_FORMAT_R32G32B32A32_FLOAT:
943 case PIPE_FORMAT_R32G32B32A32_SNORM:
944 case PIPE_FORMAT_R32G32B32A32_UNORM:
945 case PIPE_FORMAT_R32G32B32A32_SSCALED:
946 case PIPE_FORMAT_R32G32B32A32_USCALED:
947 case PIPE_FORMAT_R32G32B32A32_SINT:
948 case PIPE_FORMAT_R32G32B32A32_UINT:
949 return V_028C70_SWAP_STD;
950 default:
951 R600_ERR("unsupported colorswap format %d\n", format);
952 return ~0U;
953 }
954 return ~0U;
955 }
956
957 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
958 {
959 if (R600_BIG_ENDIAN) {
960 switch(colorformat) {
961 /* 8-bit buffers. */
962 case V_028C70_COLOR_8:
963 return V_028C70_ENDIAN_NONE;
964
965 /* 16-bit buffers. */
966 case V_028C70_COLOR_5_6_5:
967 case V_028C70_COLOR_1_5_5_5:
968 case V_028C70_COLOR_4_4_4_4:
969 case V_028C70_COLOR_16:
970 case V_028C70_COLOR_8_8:
971 return V_028C70_ENDIAN_8IN16;
972
973 /* 32-bit buffers. */
974 case V_028C70_COLOR_8_8_8_8:
975 case V_028C70_COLOR_2_10_10_10:
976 case V_028C70_COLOR_8_24:
977 case V_028C70_COLOR_24_8:
978 case V_028C70_COLOR_16_16:
979 return V_028C70_ENDIAN_8IN32;
980
981 /* 64-bit buffers. */
982 case V_028C70_COLOR_16_16_16_16:
983 return V_028C70_ENDIAN_8IN16;
984
985 case V_028C70_COLOR_32_32:
986 return V_028C70_ENDIAN_8IN32;
987
988 /* 128-bit buffers. */
989 case V_028C70_COLOR_32_32_32_32:
990 return V_028C70_ENDIAN_8IN32;
991 default:
992 return V_028C70_ENDIAN_NONE; /* Unsupported. */
993 }
994 } else {
995 return V_028C70_ENDIAN_NONE;
996 }
997 }
998
999 /* Returns the size in bits of the widest component of a CB format */
1000 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1001 {
1002 switch(colorformat) {
1003 case V_028C70_COLOR_4_4_4_4:
1004 return 4;
1005
1006 case V_028C70_COLOR_1_5_5_5:
1007 case V_028C70_COLOR_5_5_5_1:
1008 return 5;
1009
1010 case V_028C70_COLOR_5_6_5:
1011 return 6;
1012
1013 case V_028C70_COLOR_8:
1014 case V_028C70_COLOR_8_8:
1015 case V_028C70_COLOR_8_8_8_8:
1016 return 8;
1017
1018 case V_028C70_COLOR_10_10_10_2:
1019 case V_028C70_COLOR_2_10_10_10:
1020 return 10;
1021
1022 case V_028C70_COLOR_10_11_11:
1023 case V_028C70_COLOR_11_11_10:
1024 return 11;
1025
1026 case V_028C70_COLOR_16:
1027 case V_028C70_COLOR_16_16:
1028 case V_028C70_COLOR_16_16_16_16:
1029 return 16;
1030
1031 case V_028C70_COLOR_8_24:
1032 case V_028C70_COLOR_24_8:
1033 return 24;
1034
1035 case V_028C70_COLOR_32:
1036 case V_028C70_COLOR_32_32:
1037 case V_028C70_COLOR_32_32_32_32:
1038 case V_028C70_COLOR_X24_8_32_FLOAT:
1039 return 32;
1040 }
1041
1042 assert(!"Unknown maximum component size");
1043 return 0;
1044 }
1045
1046 static uint32_t si_translate_dbformat(enum pipe_format format)
1047 {
1048 switch (format) {
1049 case PIPE_FORMAT_Z16_UNORM:
1050 return V_028040_Z_16;
1051 case PIPE_FORMAT_Z24X8_UNORM:
1052 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1053 return V_028040_Z_24; /* XXX no longer supported on SI */
1054 case PIPE_FORMAT_Z32_FLOAT:
1055 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1056 return V_028040_Z_32_FLOAT;
1057 default:
1058 return ~0U;
1059 }
1060 }
1061
1062 /*
1063 * Texture translation
1064 */
1065
1066 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1067 enum pipe_format format,
1068 const struct util_format_description *desc,
1069 int first_non_void)
1070 {
1071 boolean uniform = TRUE;
1072 int i;
1073
1074 /* Colorspace (return non-RGB formats directly). */
1075 switch (desc->colorspace) {
1076 /* Depth stencil formats */
1077 case UTIL_FORMAT_COLORSPACE_ZS:
1078 switch (format) {
1079 case PIPE_FORMAT_Z16_UNORM:
1080 return V_008F14_IMG_DATA_FORMAT_16;
1081 case PIPE_FORMAT_X24S8_UINT:
1082 case PIPE_FORMAT_Z24X8_UNORM:
1083 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1084 return V_008F14_IMG_DATA_FORMAT_24_8;
1085 case PIPE_FORMAT_S8X24_UINT:
1086 case PIPE_FORMAT_X8Z24_UNORM:
1087 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1088 return V_008F14_IMG_DATA_FORMAT_8_24;
1089 case PIPE_FORMAT_S8_UINT:
1090 return V_008F14_IMG_DATA_FORMAT_8;
1091 case PIPE_FORMAT_Z32_FLOAT:
1092 return V_008F14_IMG_DATA_FORMAT_32;
1093 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1094 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1095 default:
1096 goto out_unknown;
1097 }
1098
1099 case UTIL_FORMAT_COLORSPACE_YUV:
1100 goto out_unknown; /* TODO */
1101
1102 case UTIL_FORMAT_COLORSPACE_SRGB:
1103 break;
1104
1105 default:
1106 break;
1107 }
1108
1109 /* TODO compressed formats */
1110
1111 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1112 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1113 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1114 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1115 }
1116
1117 /* R8G8Bx_SNORM - TODO CxV8U8 */
1118
1119 /* See whether the components are of the same size. */
1120 for (i = 1; i < desc->nr_channels; i++) {
1121 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1122 }
1123
1124 /* Non-uniform formats. */
1125 if (!uniform) {
1126 switch(desc->nr_channels) {
1127 case 3:
1128 if (desc->channel[0].size == 5 &&
1129 desc->channel[1].size == 6 &&
1130 desc->channel[2].size == 5) {
1131 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1132 }
1133 goto out_unknown;
1134 case 4:
1135 if (desc->channel[0].size == 5 &&
1136 desc->channel[1].size == 5 &&
1137 desc->channel[2].size == 5 &&
1138 desc->channel[3].size == 1) {
1139 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1140 }
1141 if (desc->channel[0].size == 10 &&
1142 desc->channel[1].size == 10 &&
1143 desc->channel[2].size == 10 &&
1144 desc->channel[3].size == 2) {
1145 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1146 }
1147 goto out_unknown;
1148 }
1149 goto out_unknown;
1150 }
1151
1152 if (first_non_void < 0 || first_non_void > 3)
1153 goto out_unknown;
1154
1155 /* uniform formats */
1156 switch (desc->channel[first_non_void].size) {
1157 case 4:
1158 switch (desc->nr_channels) {
1159 case 2:
1160 return V_008F14_IMG_DATA_FORMAT_4_4;
1161 case 4:
1162 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1163 }
1164 break;
1165 case 8:
1166 switch (desc->nr_channels) {
1167 case 1:
1168 return V_008F14_IMG_DATA_FORMAT_8;
1169 case 2:
1170 return V_008F14_IMG_DATA_FORMAT_8_8;
1171 case 4:
1172 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1173 }
1174 break;
1175 case 16:
1176 switch (desc->nr_channels) {
1177 case 1:
1178 return V_008F14_IMG_DATA_FORMAT_16;
1179 case 2:
1180 return V_008F14_IMG_DATA_FORMAT_16_16;
1181 case 4:
1182 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1183 }
1184 break;
1185 case 32:
1186 switch (desc->nr_channels) {
1187 case 1:
1188 return V_008F14_IMG_DATA_FORMAT_32;
1189 case 2:
1190 return V_008F14_IMG_DATA_FORMAT_32_32;
1191 case 3:
1192 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1193 case 4:
1194 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1195 }
1196 }
1197
1198 out_unknown:
1199 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1200 return ~0;
1201 }
1202
1203 static unsigned si_tex_wrap(unsigned wrap)
1204 {
1205 switch (wrap) {
1206 default:
1207 case PIPE_TEX_WRAP_REPEAT:
1208 return V_008F30_SQ_TEX_WRAP;
1209 case PIPE_TEX_WRAP_CLAMP:
1210 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1211 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1212 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1213 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1214 return V_008F30_SQ_TEX_CLAMP_BORDER;
1215 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1216 return V_008F30_SQ_TEX_MIRROR;
1217 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1218 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1219 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1220 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1221 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1222 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1223 }
1224 }
1225
1226 static unsigned si_tex_filter(unsigned filter)
1227 {
1228 switch (filter) {
1229 default:
1230 case PIPE_TEX_FILTER_NEAREST:
1231 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1232 case PIPE_TEX_FILTER_LINEAR:
1233 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1234 }
1235 }
1236
1237 static unsigned si_tex_mipfilter(unsigned filter)
1238 {
1239 switch (filter) {
1240 case PIPE_TEX_MIPFILTER_NEAREST:
1241 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1242 case PIPE_TEX_MIPFILTER_LINEAR:
1243 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1244 default:
1245 case PIPE_TEX_MIPFILTER_NONE:
1246 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1247 }
1248 }
1249
1250 static unsigned si_tex_compare(unsigned compare)
1251 {
1252 switch (compare) {
1253 default:
1254 case PIPE_FUNC_NEVER:
1255 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1256 case PIPE_FUNC_LESS:
1257 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1258 case PIPE_FUNC_EQUAL:
1259 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1260 case PIPE_FUNC_LEQUAL:
1261 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1262 case PIPE_FUNC_GREATER:
1263 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1264 case PIPE_FUNC_NOTEQUAL:
1265 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1266 case PIPE_FUNC_GEQUAL:
1267 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1268 case PIPE_FUNC_ALWAYS:
1269 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1270 }
1271 }
1272
1273 static unsigned si_tex_dim(unsigned dim)
1274 {
1275 switch (dim) {
1276 default:
1277 case PIPE_TEXTURE_1D:
1278 return V_008F1C_SQ_RSRC_IMG_1D;
1279 case PIPE_TEXTURE_1D_ARRAY:
1280 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1281 case PIPE_TEXTURE_2D:
1282 case PIPE_TEXTURE_RECT:
1283 return V_008F1C_SQ_RSRC_IMG_2D;
1284 case PIPE_TEXTURE_2D_ARRAY:
1285 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1286 case PIPE_TEXTURE_3D:
1287 return V_008F1C_SQ_RSRC_IMG_3D;
1288 case PIPE_TEXTURE_CUBE:
1289 return V_008F1C_SQ_RSRC_IMG_CUBE;
1290 }
1291 }
1292
1293 /*
1294 * Format support testing
1295 */
1296
1297 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1298 {
1299 return si_translate_texformat(screen, format, util_format_description(format),
1300 util_format_get_first_non_void_channel(format)) != ~0U;
1301 }
1302
1303 static uint32_t si_translate_vertexformat(struct pipe_screen *screen,
1304 enum pipe_format format,
1305 const struct util_format_description *desc,
1306 int first_non_void)
1307 {
1308 unsigned type = desc->channel[first_non_void].type;
1309 int i;
1310
1311 if (type == UTIL_FORMAT_TYPE_FIXED)
1312 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1313
1314 /* See whether the components are of the same size. */
1315 for (i = 0; i < desc->nr_channels; i++) {
1316 if (desc->channel[first_non_void].size != desc->channel[i].size)
1317 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1318 }
1319
1320 switch (desc->channel[first_non_void].size) {
1321 case 8:
1322 switch (desc->nr_channels) {
1323 case 1:
1324 return V_008F0C_BUF_DATA_FORMAT_8;
1325 case 2:
1326 return V_008F0C_BUF_DATA_FORMAT_8_8;
1327 case 3:
1328 case 4:
1329 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1330 }
1331 break;
1332 case 16:
1333 switch (desc->nr_channels) {
1334 case 1:
1335 return V_008F0C_BUF_DATA_FORMAT_16;
1336 case 2:
1337 return V_008F0C_BUF_DATA_FORMAT_16_16;
1338 case 3:
1339 case 4:
1340 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1341 }
1342 break;
1343 case 32:
1344 if (type != UTIL_FORMAT_TYPE_FLOAT)
1345 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1346
1347 switch (desc->nr_channels) {
1348 case 1:
1349 return V_008F0C_BUF_DATA_FORMAT_32;
1350 case 2:
1351 return V_008F0C_BUF_DATA_FORMAT_32_32;
1352 case 3:
1353 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1354 case 4:
1355 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1356 }
1357 break;
1358 }
1359
1360 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1361 }
1362
1363 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1364 {
1365 const struct util_format_description *desc;
1366 int first_non_void;
1367 unsigned data_format;
1368
1369 desc = util_format_description(format);
1370 first_non_void = util_format_get_first_non_void_channel(format);
1371 data_format = si_translate_vertexformat(screen, format, desc, first_non_void);
1372 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1373 }
1374
1375 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1376 {
1377 return si_translate_colorformat(format) != ~0U &&
1378 si_translate_colorswap(format) != ~0U;
1379 }
1380
1381 static bool si_is_zs_format_supported(enum pipe_format format)
1382 {
1383 return si_translate_dbformat(format) != ~0U;
1384 }
1385
1386 bool si_is_format_supported(struct pipe_screen *screen,
1387 enum pipe_format format,
1388 enum pipe_texture_target target,
1389 unsigned sample_count,
1390 unsigned usage)
1391 {
1392 unsigned retval = 0;
1393
1394 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1395 R600_ERR("r600: unsupported texture type %d\n", target);
1396 return FALSE;
1397 }
1398
1399 if (!util_format_is_supported(format, usage))
1400 return FALSE;
1401
1402 /* Multisample */
1403 if (sample_count > 1)
1404 return FALSE;
1405
1406 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
1407 si_is_sampler_format_supported(screen, format)) {
1408 retval |= PIPE_BIND_SAMPLER_VIEW;
1409 }
1410
1411 if ((usage & (PIPE_BIND_RENDER_TARGET |
1412 PIPE_BIND_DISPLAY_TARGET |
1413 PIPE_BIND_SCANOUT |
1414 PIPE_BIND_SHARED)) &&
1415 si_is_colorbuffer_format_supported(format)) {
1416 retval |= usage &
1417 (PIPE_BIND_RENDER_TARGET |
1418 PIPE_BIND_DISPLAY_TARGET |
1419 PIPE_BIND_SCANOUT |
1420 PIPE_BIND_SHARED);
1421 }
1422
1423 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1424 si_is_zs_format_supported(format)) {
1425 retval |= PIPE_BIND_DEPTH_STENCIL;
1426 }
1427
1428 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1429 si_is_vertex_format_supported(screen, format)) {
1430 retval |= PIPE_BIND_VERTEX_BUFFER;
1431 }
1432
1433 if (usage & PIPE_BIND_TRANSFER_READ)
1434 retval |= PIPE_BIND_TRANSFER_READ;
1435 if (usage & PIPE_BIND_TRANSFER_WRITE)
1436 retval |= PIPE_BIND_TRANSFER_WRITE;
1437
1438 return retval == usage;
1439 }
1440
1441 /*
1442 * framebuffer handling
1443 */
1444
1445 static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
1446 const struct pipe_framebuffer_state *state, int cb)
1447 {
1448 struct r600_resource_texture *rtex;
1449 struct r600_surface *surf;
1450 unsigned level = state->cbufs[cb]->u.tex.level;
1451 unsigned pitch, slice;
1452 unsigned color_info, color_attrib;
1453 unsigned format, swap, ntype, endian;
1454 uint64_t offset;
1455 unsigned blocksize;
1456 const struct util_format_description *desc;
1457 int i;
1458 unsigned blend_clamp = 0, blend_bypass = 0;
1459 unsigned max_comp_size;
1460
1461 surf = (struct r600_surface *)state->cbufs[cb];
1462 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1463 blocksize = util_format_get_blocksize(rtex->real_format);
1464
1465 if (rtex->depth)
1466 rctx->have_depth_fb = TRUE;
1467
1468 if (rtex->depth && !rtex->is_flushing_texture) {
1469 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1470 rtex = rtex->flushed_depth_texture;
1471 }
1472
1473 offset = rtex->surface.level[level].offset;
1474 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1475 offset += rtex->surface.level[level].slice_size *
1476 state->cbufs[cb]->u.tex.first_layer;
1477 }
1478 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1479 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1480 if (slice) {
1481 slice = slice - 1;
1482 }
1483
1484 color_attrib = S_028C74_TILE_MODE_INDEX(8);
1485 switch (rtex->surface.level[level].mode) {
1486 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1487 color_attrib = S_028C74_TILE_MODE_INDEX(8);
1488 break;
1489 case RADEON_SURF_MODE_1D:
1490 color_attrib = S_028C74_TILE_MODE_INDEX(9);
1491 break;
1492 case RADEON_SURF_MODE_2D:
1493 if (rtex->resource.b.b.bind & PIPE_BIND_SCANOUT) {
1494 switch (blocksize) {
1495 case 1:
1496 color_attrib = S_028C74_TILE_MODE_INDEX(10);
1497 break;
1498 case 2:
1499 color_attrib = S_028C74_TILE_MODE_INDEX(11);
1500 break;
1501 case 4:
1502 color_attrib = S_028C74_TILE_MODE_INDEX(12);
1503 break;
1504 }
1505 break;
1506 } else switch (blocksize) {
1507 case 1:
1508 color_attrib = S_028C74_TILE_MODE_INDEX(14);
1509 break;
1510 case 2:
1511 color_attrib = S_028C74_TILE_MODE_INDEX(15);
1512 break;
1513 case 4:
1514 color_attrib = S_028C74_TILE_MODE_INDEX(16);
1515 break;
1516 case 8:
1517 color_attrib = S_028C74_TILE_MODE_INDEX(17);
1518 break;
1519 default:
1520 color_attrib = S_028C74_TILE_MODE_INDEX(13);
1521 }
1522 break;
1523 }
1524
1525 desc = util_format_description(surf->base.format);
1526 for (i = 0; i < 4; i++) {
1527 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1528 break;
1529 }
1530 }
1531 if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1532 ntype = V_028C70_NUMBER_FLOAT;
1533 } else {
1534 ntype = V_028C70_NUMBER_UNORM;
1535 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1536 ntype = V_028C70_NUMBER_SRGB;
1537 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1538 if (desc->channel[i].normalized)
1539 ntype = V_028C70_NUMBER_SNORM;
1540 else if (desc->channel[i].pure_integer)
1541 ntype = V_028C70_NUMBER_SINT;
1542 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1543 if (desc->channel[i].normalized)
1544 ntype = V_028C70_NUMBER_UNORM;
1545 else if (desc->channel[i].pure_integer)
1546 ntype = V_028C70_NUMBER_UINT;
1547 }
1548 }
1549
1550 format = si_translate_colorformat(surf->base.format);
1551 swap = si_translate_colorswap(surf->base.format);
1552 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1553 endian = V_028C70_ENDIAN_NONE;
1554 } else {
1555 endian = si_colorformat_endian_swap(format);
1556 }
1557
1558 /* blend clamp should be set for all NORM/SRGB types */
1559 if (ntype == V_028C70_NUMBER_UNORM ||
1560 ntype == V_028C70_NUMBER_SNORM ||
1561 ntype == V_028C70_NUMBER_SRGB)
1562 blend_clamp = 1;
1563
1564 /* set blend bypass according to docs if SINT/UINT or
1565 8/24 COLOR variants */
1566 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1567 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1568 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1569 blend_clamp = 0;
1570 blend_bypass = 1;
1571 }
1572
1573 color_info = S_028C70_FORMAT(format) |
1574 S_028C70_COMP_SWAP(swap) |
1575 S_028C70_BLEND_CLAMP(blend_clamp) |
1576 S_028C70_BLEND_BYPASS(blend_bypass) |
1577 S_028C70_NUMBER_TYPE(ntype) |
1578 S_028C70_ENDIAN(endian);
1579
1580 rctx->alpha_ref_dirty = true;
1581
1582 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1583 offset >>= 8;
1584
1585 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1586 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1587 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset);
1588 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, S_028C64_TILE_MAX(pitch));
1589 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice));
1590
1591 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1592 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 0x00000000);
1593 } else {
1594 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1595 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1596 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1597 }
1598 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
1599 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib);
1600
1601 /* Determine pixel shader export format */
1602 max_comp_size = si_colorformat_max_comp_size(format);
1603 if (ntype == V_028C70_NUMBER_SRGB ||
1604 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1605 max_comp_size <= 10) ||
1606 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1607 rctx->export_16bpc |= 1 << cb;
1608 rctx->spi_shader_col_format |= V_028714_SPI_SHADER_FP16_ABGR << (4 * cb);
1609 } else
1610 rctx->spi_shader_col_format |= V_028714_SPI_SHADER_32_ABGR << (4 * cb);
1611 }
1612
1613 static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
1614 const struct pipe_framebuffer_state *state)
1615 {
1616 struct r600_resource_texture *rtex;
1617 struct r600_surface *surf;
1618 unsigned level, pitch, slice, format;
1619 uint32_t z_info, s_info;
1620 uint64_t z_offs, s_offs;
1621
1622 if (state->zsbuf == NULL) {
1623 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
1624 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0);
1625 return;
1626 }
1627
1628 surf = (struct r600_surface *)state->zsbuf;
1629 level = surf->base.u.tex.level;
1630 rtex = (struct r600_resource_texture*)surf->base.texture;
1631
1632 format = si_translate_dbformat(rtex->real_format);
1633
1634 z_offs = r600_resource_va(rctx->context.screen, surf->base.texture);
1635 z_offs += rtex->surface.level[level].offset;
1636
1637 s_offs = r600_resource_va(rctx->context.screen, surf->base.texture);
1638 s_offs += rtex->surface.stencil_offset;
1639 z_offs += rtex->surface.level[level].offset / 4;
1640
1641 z_offs >>= 8;
1642 s_offs >>= 8;
1643
1644 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1645 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1646 if (slice) {
1647 slice = slice - 1;
1648 }
1649
1650 z_info = S_028040_FORMAT(format);
1651 s_info = S_028044_FORMAT(1);
1652
1653 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_1D) {
1654 z_info |= S_028040_TILE_MODE_INDEX(4);
1655 s_info |= S_028044_TILE_MODE_INDEX(4);
1656
1657 } else if (rtex->surface.level[level].mode == RADEON_SURF_MODE_2D) {
1658 switch (format) {
1659 case V_028040_Z_16:
1660 z_info |= S_028040_TILE_MODE_INDEX(5);
1661 s_info |= S_028044_TILE_MODE_INDEX(5);
1662 break;
1663 case V_028040_Z_24:
1664 case V_028040_Z_32_FLOAT:
1665 z_info |= S_028040_TILE_MODE_INDEX(6);
1666 s_info |= S_028044_TILE_MODE_INDEX(6);
1667 break;
1668 default:
1669 z_info |= S_028040_TILE_MODE_INDEX(7);
1670 s_info |= S_028044_TILE_MODE_INDEX(7);
1671 }
1672
1673 } else {
1674 R600_ERR("Invalid DB tiling mode %d!\n",
1675 rtex->surface.level[level].mode);
1676 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
1677 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0);
1678 return;
1679 }
1680
1681 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
1682 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1683 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1684
1685 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, 0x1);
1686 if (format != ~0U) {
1687 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
1688
1689 } else {
1690 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
1691 }
1692
1693 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1694 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
1695 } else {
1696 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0);
1697 }
1698
1699 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1700 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
1701 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs);
1702 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs);
1703 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs);
1704
1705 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
1706 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
1707 }
1708
1709 static void si_set_framebuffer_state(struct pipe_context *ctx,
1710 const struct pipe_framebuffer_state *state)
1711 {
1712 struct r600_context *rctx = (struct r600_context *)ctx;
1713 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
1714 uint32_t shader_mask, tl, br;
1715 int tl_x, tl_y, br_x, br_y;
1716
1717 if (pm4 == NULL)
1718 return;
1719
1720 si_pm4_inval_fb_cache(pm4, state->nr_cbufs);
1721
1722 if (state->zsbuf)
1723 si_pm4_inval_zsbuf_cache(pm4);
1724
1725 util_copy_framebuffer_state(&rctx->framebuffer, state);
1726
1727 /* build states */
1728 rctx->have_depth_fb = 0;
1729 rctx->export_16bpc = 0;
1730 rctx->spi_shader_col_format = 0;
1731 for (int i = 0; i < state->nr_cbufs; i++) {
1732 si_cb(rctx, pm4, state, i);
1733 }
1734 assert(!(rctx->export_16bpc & ~0xff));
1735 si_db(rctx, pm4, state);
1736
1737 shader_mask = 0;
1738 for (int i = 0; i < state->nr_cbufs; i++) {
1739 shader_mask |= 0xf << (i * 4);
1740 }
1741 tl_x = 0;
1742 tl_y = 0;
1743 br_x = state->width;
1744 br_y = state->height;
1745 #if 0 /* These shouldn't be necessary on SI, see PA_SC_ENHANCE register */
1746 /* EG hw workaround */
1747 if (br_x == 0)
1748 tl_x = 1;
1749 if (br_y == 0)
1750 tl_y = 1;
1751 /* cayman hw workaround */
1752 if (rctx->chip_class == CAYMAN) {
1753 if (br_x == 1 && br_y == 1)
1754 br_x = 2;
1755 }
1756 #endif
1757 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1758 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1759
1760 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl);
1761 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br);
1762 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1763 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1764 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl);
1765 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br);
1766 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1767 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1768 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000);
1769 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
1770 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader_mask);
1771 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
1772 rctx->spi_shader_col_format);
1773 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0x00000000);
1774
1775 si_pm4_set_state(rctx, framebuffer, pm4);
1776 si_update_fb_rs_state(rctx);
1777 si_update_fb_blend_state(rctx);
1778 }
1779
1780 /*
1781 * shaders
1782 */
1783
1784 /* Compute the key for the hw shader variant */
1785 static INLINE unsigned si_shader_selector_key(struct pipe_context *ctx,
1786 struct si_pipe_shader_selector *sel)
1787 {
1788 struct r600_context *rctx = (struct r600_context *)ctx;
1789 unsigned key = 0;
1790
1791 if (sel->type == PIPE_SHADER_FRAGMENT) {
1792 if (sel->fs_write_all)
1793 key |= rctx->framebuffer.nr_cbufs;
1794 key |= rctx->export_16bpc << 4;
1795 /*if (rctx->queued.named.rasterizer)
1796 key |= rctx->queued.named.rasterizer->flatshade << 12;*/
1797 /*key |== rctx->two_side << 13;*/
1798 }
1799
1800 return key;
1801 }
1802
1803 /* Select the hw shader variant depending on the current state.
1804 * (*dirty) is set to 1 if current variant was changed */
1805 int si_shader_select(struct pipe_context *ctx,
1806 struct si_pipe_shader_selector *sel,
1807 unsigned *dirty)
1808 {
1809 unsigned key;
1810 struct si_pipe_shader * shader = NULL;
1811 int r;
1812
1813 key = si_shader_selector_key(ctx, sel);
1814
1815 /* Check if we don't need to change anything.
1816 * This path is also used for most shaders that don't need multiple
1817 * variants, it will cost just a computation of the key and this
1818 * test. */
1819 if (likely(sel->current && sel->current->key == key)) {
1820 return 0;
1821 }
1822
1823 /* lookup if we have other variants in the list */
1824 if (sel->num_shaders > 1) {
1825 struct si_pipe_shader *p = sel->current, *c = p->next_variant;
1826
1827 while (c && c->key != key) {
1828 p = c;
1829 c = c->next_variant;
1830 }
1831
1832 if (c) {
1833 p->next_variant = c->next_variant;
1834 shader = c;
1835 }
1836 }
1837
1838 if (unlikely(!shader)) {
1839 shader = CALLOC(1, sizeof(struct si_pipe_shader));
1840 shader->selector = sel;
1841
1842 r = si_pipe_shader_create(ctx, shader);
1843 if (unlikely(r)) {
1844 R600_ERR("Failed to build shader variant (type=%u, key=%u) %d\n",
1845 sel->type, key, r);
1846 sel->current = NULL;
1847 return r;
1848 }
1849
1850 /* We don't know the value of fs_write_all property until we built
1851 * at least one variant, so we may need to recompute the key (include
1852 * rctx->framebuffer.nr_cbufs) after building first variant. */
1853 if (sel->type == PIPE_SHADER_FRAGMENT &&
1854 sel->num_shaders == 0 &&
1855 shader->shader.fs_write_all) {
1856 sel->fs_write_all = 1;
1857 key = si_shader_selector_key(ctx, sel);
1858 }
1859
1860 shader->key = key;
1861 sel->num_shaders++;
1862 }
1863
1864 if (dirty)
1865 *dirty = 1;
1866
1867 shader->next_variant = sel->current;
1868 sel->current = shader;
1869
1870 return 0;
1871 }
1872
1873 static void *si_create_shader_state(struct pipe_context *ctx,
1874 const struct pipe_shader_state *state,
1875 unsigned pipe_shader_type)
1876 {
1877 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
1878 int r;
1879
1880 sel->type = pipe_shader_type;
1881 sel->tokens = tgsi_dup_tokens(state->tokens);
1882 sel->so = state->stream_output;
1883
1884 r = si_shader_select(ctx, sel, NULL);
1885 if (r) {
1886 free(sel);
1887 return NULL;
1888 }
1889
1890 return sel;
1891 }
1892
1893 static void *si_create_fs_state(struct pipe_context *ctx,
1894 const struct pipe_shader_state *state)
1895 {
1896 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
1897 }
1898
1899 static void *si_create_vs_state(struct pipe_context *ctx,
1900 const struct pipe_shader_state *state)
1901 {
1902 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
1903 }
1904
1905 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
1906 {
1907 struct r600_context *rctx = (struct r600_context *)ctx;
1908 struct si_pipe_shader_selector *sel = state;
1909
1910 if (rctx->vs_shader == sel)
1911 return;
1912
1913 rctx->shader_dirty = true;
1914 rctx->vs_shader = sel;
1915
1916 if (sel && sel->current)
1917 si_pm4_bind_state(rctx, vs, sel->current->pm4);
1918 else
1919 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
1920 }
1921
1922 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
1923 {
1924 struct r600_context *rctx = (struct r600_context *)ctx;
1925 struct si_pipe_shader_selector *sel = state;
1926
1927 if (rctx->ps_shader == sel)
1928 return;
1929
1930 rctx->shader_dirty = true;
1931 rctx->ps_shader = sel;
1932
1933 if (sel && sel->current)
1934 si_pm4_bind_state(rctx, ps, sel->current->pm4);
1935 else
1936 si_pm4_bind_state(rctx, ps, rctx->dummy_pixel_shader->pm4);
1937 }
1938
1939 static void si_delete_shader_selector(struct pipe_context *ctx,
1940 struct si_pipe_shader_selector *sel)
1941 {
1942 struct r600_context *rctx = (struct r600_context *)ctx;
1943 struct si_pipe_shader *p = sel->current, *c;
1944
1945 while (p) {
1946 c = p->next_variant;
1947 si_pm4_delete_state(rctx, vs, p->pm4);
1948 si_pipe_shader_destroy(ctx, p);
1949 free(p);
1950 p = c;
1951 }
1952
1953 free(sel->tokens);
1954 free(sel);
1955 }
1956
1957 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
1958 {
1959 struct r600_context *rctx = (struct r600_context *)ctx;
1960 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
1961
1962 if (rctx->vs_shader == sel) {
1963 rctx->vs_shader = NULL;
1964 }
1965
1966 si_delete_shader_selector(ctx, sel);
1967 }
1968
1969 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
1970 {
1971 struct r600_context *rctx = (struct r600_context *)ctx;
1972 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
1973
1974 if (rctx->ps_shader == sel) {
1975 rctx->ps_shader = NULL;
1976 }
1977
1978 si_delete_shader_selector(ctx, sel);
1979 }
1980
1981 /*
1982 * Samplers
1983 */
1984
1985 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
1986 struct pipe_resource *texture,
1987 const struct pipe_sampler_view *state)
1988 {
1989 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
1990 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
1991 const struct util_format_description *desc = util_format_description(state->format);
1992 unsigned blocksize = util_format_get_blocksize(tmp->real_format);
1993 unsigned format, num_format, /*endian,*/ tiling_index;
1994 uint32_t pitch = 0;
1995 unsigned char state_swizzle[4], swizzle[4];
1996 unsigned height, depth, width, offset_level, last_level;
1997 int first_non_void;
1998 uint64_t va;
1999
2000 if (view == NULL)
2001 return NULL;
2002
2003 /* initialize base object */
2004 view->base = *state;
2005 view->base.texture = NULL;
2006 pipe_reference(NULL, &texture->reference);
2007 view->base.texture = texture;
2008 view->base.reference.count = 1;
2009 view->base.context = ctx;
2010
2011 state_swizzle[0] = state->swizzle_r;
2012 state_swizzle[1] = state->swizzle_g;
2013 state_swizzle[2] = state->swizzle_b;
2014 state_swizzle[3] = state->swizzle_a;
2015 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2016
2017 first_non_void = util_format_get_first_non_void_channel(state->format);
2018 switch (desc->channel[first_non_void].type) {
2019 case UTIL_FORMAT_TYPE_FLOAT:
2020 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2021 break;
2022 case UTIL_FORMAT_TYPE_SIGNED:
2023 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2024 break;
2025 case UTIL_FORMAT_TYPE_UNSIGNED:
2026 default:
2027 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2028 }
2029
2030 format = si_translate_texformat(ctx->screen, state->format, desc, first_non_void);
2031 if (format == ~0) {
2032 format = 0;
2033 }
2034
2035 if (tmp->depth && !tmp->is_flushing_texture) {
2036 r600_texture_depth_flush(ctx, texture, TRUE);
2037 tmp = tmp->flushed_depth_texture;
2038 }
2039
2040 /* not supported any more */
2041 //endian = si_colorformat_endian_swap(format);
2042
2043 offset_level = state->u.tex.first_level;
2044 last_level = state->u.tex.last_level - offset_level;
2045 width = tmp->surface.level[offset_level].npix_x;
2046 height = tmp->surface.level[offset_level].npix_y;
2047 depth = tmp->surface.level[offset_level].npix_z;
2048 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
2049
2050 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2051 height = 1;
2052 depth = texture->array_size;
2053 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2054 depth = texture->array_size;
2055 }
2056
2057 tiling_index = 8;
2058 switch (tmp->surface.level[state->u.tex.first_level].mode) {
2059 case RADEON_SURF_MODE_LINEAR_ALIGNED:
2060 tiling_index = 8;
2061 break;
2062 case RADEON_SURF_MODE_1D:
2063 tiling_index = 9;
2064 break;
2065 case RADEON_SURF_MODE_2D:
2066 if (tmp->resource.b.b.bind & PIPE_BIND_SCANOUT) {
2067 switch (blocksize) {
2068 case 1:
2069 tiling_index = 10;
2070 break;
2071 case 2:
2072 tiling_index = 11;
2073 break;
2074 case 4:
2075 tiling_index = 12;
2076 break;
2077 }
2078 break;
2079 } else switch (blocksize) {
2080 case 1:
2081 tiling_index = 14;
2082 break;
2083 case 2:
2084 tiling_index = 15;
2085 break;
2086 case 4:
2087 tiling_index = 16;
2088 break;
2089 case 8:
2090 tiling_index = 17;
2091 break;
2092 default:
2093 tiling_index = 13;
2094 }
2095 break;
2096 }
2097
2098 va = r600_resource_va(ctx->screen, texture);
2099 va += tmp->surface.level[offset_level].offset;
2100 view->state[0] = va >> 8;
2101 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2102 S_008F14_DATA_FORMAT(format) |
2103 S_008F14_NUM_FORMAT(num_format));
2104 view->state[2] = (S_008F18_WIDTH(width - 1) |
2105 S_008F18_HEIGHT(height - 1));
2106 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2107 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2108 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2109 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2110 S_008F1C_BASE_LEVEL(offset_level) |
2111 S_008F1C_LAST_LEVEL(last_level) |
2112 S_008F1C_TILING_INDEX(tiling_index) |
2113 S_008F1C_TYPE(si_tex_dim(texture->target)));
2114 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2115 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2116 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2117 view->state[6] = 0;
2118 view->state[7] = 0;
2119
2120 return &view->base;
2121 }
2122
2123 static void si_sampler_view_destroy(struct pipe_context *ctx,
2124 struct pipe_sampler_view *state)
2125 {
2126 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
2127
2128 pipe_resource_reference(&state->texture, NULL);
2129 FREE(resource);
2130 }
2131
2132 static void *si_create_sampler_state(struct pipe_context *ctx,
2133 const struct pipe_sampler_state *state)
2134 {
2135 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
2136 union util_color uc;
2137 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2138 unsigned border_color_type;
2139
2140 if (rstate == NULL) {
2141 return NULL;
2142 }
2143
2144 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
2145 switch (uc.ui) {
2146 case 0x000000FF:
2147 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
2148 break;
2149 case 0x00000000:
2150 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2151 break;
2152 case 0xFFFFFFFF:
2153 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
2154 break;
2155 default: /* Use border color pointer */
2156 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2157 }
2158
2159 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2160 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2161 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2162 (state->max_anisotropy & 0x7) << 9 | /* XXX */
2163 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2164 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2165 aniso_flag_offset << 16 | /* XXX */
2166 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2167 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2168 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2169 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2170 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
2171 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
2172 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2173 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2174
2175 #if 0
2176 if (border_color_type == 3) {
2177 si_pm4_set_reg(pm4, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]));
2178 si_pm4_set_reg(pm4, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]));
2179 si_pm4_set_reg(pm4, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]));
2180 si_pm4_set_reg(pm4, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]));
2181 }
2182 #endif
2183 return rstate;
2184 }
2185
2186 static void si_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
2187 struct pipe_sampler_view **views)
2188 {
2189 assert(count == 0);
2190 }
2191
2192 static void si_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
2193 struct pipe_sampler_view **views)
2194 {
2195 struct r600_context *rctx = (struct r600_context *)ctx;
2196 struct si_pipe_sampler_view **resource = (struct si_pipe_sampler_view **)views;
2197 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2198 int i, j;
2199 int has_depth = 0;
2200
2201 if (!count)
2202 goto out;
2203
2204 si_pm4_inval_texture_cache(pm4);
2205
2206 si_pm4_sh_data_begin(pm4);
2207 for (i = 0; i < count; i++) {
2208 pipe_sampler_view_reference(
2209 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
2210 views[i]);
2211
2212 if (views[i]) {
2213 struct r600_resource_texture *tex = (void *)resource[i]->base.texture;
2214
2215 si_pm4_add_bo(pm4, &tex->resource, RADEON_USAGE_READ);
2216
2217 for (j = 0; j < Elements(resource[i]->state); ++j) {
2218 si_pm4_sh_data_add(pm4, resource[i]->state[j]);
2219 }
2220 }
2221 }
2222
2223 for (i = count; i < NUM_TEX_UNITS; i++) {
2224 if (rctx->ps_samplers.views[i])
2225 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
2226 }
2227
2228 si_pm4_sh_data_end(pm4, R_00B040_SPI_SHADER_USER_DATA_PS_4);
2229
2230 out:
2231 si_pm4_set_state(rctx, ps_sampler_views, pm4);
2232 rctx->have_depth_texture = has_depth;
2233 rctx->ps_samplers.n_views = count;
2234 }
2235
2236 static void si_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
2237 {
2238 assert(count == 0);
2239 }
2240
2241 static void si_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
2242 {
2243 struct r600_context *rctx = (struct r600_context *)ctx;
2244 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
2245 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2246 int i, j;
2247
2248 if (!count)
2249 goto out;
2250
2251 si_pm4_inval_texture_cache(pm4);
2252
2253 si_pm4_sh_data_begin(pm4);
2254 for (i = 0; i < count; i++) {
2255 for (j = 0; j < Elements(rstates[i]->val); ++j) {
2256 si_pm4_sh_data_add(pm4, rstates[i]->val[j]);
2257 }
2258 }
2259 si_pm4_sh_data_end(pm4, R_00B038_SPI_SHADER_USER_DATA_PS_2);
2260
2261 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
2262
2263 out:
2264 si_pm4_set_state(rctx, ps_sampler, pm4);
2265 rctx->ps_samplers.n_samplers = count;
2266 }
2267
2268 static void si_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
2269 {
2270 }
2271
2272 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2273 {
2274 free(state);
2275 }
2276
2277 /*
2278 * Constants
2279 */
2280 static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
2281 struct pipe_constant_buffer *cb)
2282 {
2283 struct r600_context *rctx = (struct r600_context *)ctx;
2284 struct si_resource *rbuffer = cb ? si_resource(cb->buffer) : NULL;
2285 struct si_pm4_state *pm4;
2286 uint64_t va_offset;
2287 uint32_t offset;
2288
2289 /* Note that the state tracker can unbind constant buffers by
2290 * passing NULL here.
2291 */
2292 if (cb == NULL)
2293 return;
2294
2295 pm4 = CALLOC_STRUCT(si_pm4_state);
2296 si_pm4_inval_shader_cache(pm4);
2297
2298 if (cb->user_buffer)
2299 r600_upload_const_buffer(rctx, &rbuffer, cb->user_buffer, cb->buffer_size, &offset);
2300 else
2301 offset = 0;
2302 va_offset = r600_resource_va(ctx->screen, (void*)rbuffer);
2303 va_offset += offset;
2304
2305 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
2306
2307 switch (shader) {
2308 case PIPE_SHADER_VERTEX:
2309 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, va_offset);
2310 si_pm4_set_reg(pm4, R_00B134_SPI_SHADER_USER_DATA_VS_1, va_offset >> 32);
2311 si_pm4_set_state(rctx, vs_const, pm4);
2312 break;
2313
2314 case PIPE_SHADER_FRAGMENT:
2315 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0, va_offset);
2316 si_pm4_set_reg(pm4, R_00B034_SPI_SHADER_USER_DATA_PS_1, va_offset >> 32);
2317 si_pm4_set_state(rctx, ps_const, pm4);
2318 break;
2319
2320 default:
2321 R600_ERR("unsupported %d\n", shader);
2322 }
2323
2324 if (cb->buffer != &rbuffer->b.b)
2325 si_resource_reference(&rbuffer, NULL);
2326 }
2327
2328 /*
2329 * Vertex elements & buffers
2330 */
2331
2332 static void *si_create_vertex_elements(struct pipe_context *ctx,
2333 unsigned count,
2334 const struct pipe_vertex_element *elements)
2335 {
2336 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2337 int i;
2338
2339 assert(count < PIPE_MAX_ATTRIBS);
2340 if (!v)
2341 return NULL;
2342
2343 v->count = count;
2344 for (i = 0; i < count; ++i) {
2345 const struct util_format_description *desc;
2346 unsigned data_format, num_format;
2347 int first_non_void;
2348
2349 desc = util_format_description(elements[i].src_format);
2350 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2351 data_format = si_translate_vertexformat(ctx->screen, elements[i].src_format,
2352 desc, first_non_void);
2353
2354 switch (desc->channel[first_non_void].type) {
2355 case UTIL_FORMAT_TYPE_FIXED:
2356 num_format = V_008F0C_BUF_NUM_FORMAT_USCALED; /* XXX */
2357 break;
2358 case UTIL_FORMAT_TYPE_SIGNED:
2359 num_format = V_008F0C_BUF_NUM_FORMAT_SNORM;
2360 break;
2361 case UTIL_FORMAT_TYPE_UNSIGNED:
2362 num_format = V_008F0C_BUF_NUM_FORMAT_UNORM;
2363 break;
2364 case UTIL_FORMAT_TYPE_FLOAT:
2365 default:
2366 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2367 }
2368
2369 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2370 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2371 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2372 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2373 S_008F0C_NUM_FORMAT(num_format) |
2374 S_008F0C_DATA_FORMAT(data_format);
2375 }
2376 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2377
2378 return v;
2379 }
2380
2381 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2382 {
2383 struct r600_context *rctx = (struct r600_context *)ctx;
2384 struct si_vertex_element *v = (struct si_vertex_element*)state;
2385
2386 rctx->vertex_elements = v;
2387 }
2388
2389 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2390 {
2391 struct r600_context *rctx = (struct r600_context *)ctx;
2392
2393 if (rctx->vertex_elements == state)
2394 rctx->vertex_elements = NULL;
2395 FREE(state);
2396 }
2397
2398 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
2399 const struct pipe_vertex_buffer *buffers)
2400 {
2401 struct r600_context *rctx = (struct r600_context *)ctx;
2402
2403 util_copy_vertex_buffers(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, count);
2404 }
2405
2406 static void si_set_index_buffer(struct pipe_context *ctx,
2407 const struct pipe_index_buffer *ib)
2408 {
2409 struct r600_context *rctx = (struct r600_context *)ctx;
2410
2411 if (ib) {
2412 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
2413 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
2414 } else {
2415 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
2416 }
2417 }
2418
2419 /*
2420 * Misc
2421 */
2422 static void si_set_polygon_stipple(struct pipe_context *ctx,
2423 const struct pipe_poly_stipple *state)
2424 {
2425 }
2426
2427 static void si_texture_barrier(struct pipe_context *ctx)
2428 {
2429 struct r600_context *rctx = (struct r600_context *)ctx;
2430 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2431
2432 si_pm4_inval_texture_cache(pm4);
2433 si_pm4_inval_fb_cache(pm4, rctx->framebuffer.nr_cbufs);
2434 si_pm4_set_state(rctx, texture_barrier, pm4);
2435 }
2436
2437 void si_init_state_functions(struct r600_context *rctx)
2438 {
2439 rctx->context.create_blend_state = si_create_blend_state;
2440 rctx->context.bind_blend_state = si_bind_blend_state;
2441 rctx->context.delete_blend_state = si_delete_blend_state;
2442 rctx->context.set_blend_color = si_set_blend_color;
2443
2444 rctx->context.create_rasterizer_state = si_create_rs_state;
2445 rctx->context.bind_rasterizer_state = si_bind_rs_state;
2446 rctx->context.delete_rasterizer_state = si_delete_rs_state;
2447
2448 rctx->context.create_depth_stencil_alpha_state = si_create_dsa_state;
2449 rctx->context.bind_depth_stencil_alpha_state = si_bind_dsa_state;
2450 rctx->context.delete_depth_stencil_alpha_state = si_delete_dsa_state;
2451 rctx->custom_dsa_flush = si_create_db_flush_dsa(rctx);
2452
2453 rctx->context.set_clip_state = si_set_clip_state;
2454 rctx->context.set_scissor_state = si_set_scissor_state;
2455 rctx->context.set_viewport_state = si_set_viewport_state;
2456 rctx->context.set_stencil_ref = si_set_pipe_stencil_ref;
2457
2458 rctx->context.set_framebuffer_state = si_set_framebuffer_state;
2459
2460 rctx->context.create_vs_state = si_create_vs_state;
2461 rctx->context.create_fs_state = si_create_fs_state;
2462 rctx->context.bind_vs_state = si_bind_vs_shader;
2463 rctx->context.bind_fs_state = si_bind_ps_shader;
2464 rctx->context.delete_vs_state = si_delete_vs_shader;
2465 rctx->context.delete_fs_state = si_delete_ps_shader;
2466
2467 rctx->context.create_sampler_state = si_create_sampler_state;
2468 rctx->context.bind_vertex_sampler_states = si_bind_vs_sampler;
2469 rctx->context.bind_fragment_sampler_states = si_bind_ps_sampler;
2470 rctx->context.delete_sampler_state = si_delete_sampler_state;
2471
2472 rctx->context.create_sampler_view = si_create_sampler_view;
2473 rctx->context.set_vertex_sampler_views = si_set_vs_sampler_view;
2474 rctx->context.set_fragment_sampler_views = si_set_ps_sampler_view;
2475 rctx->context.sampler_view_destroy = si_sampler_view_destroy;
2476
2477 rctx->context.set_sample_mask = si_set_sample_mask;
2478
2479 rctx->context.set_constant_buffer = si_set_constant_buffer;
2480
2481 rctx->context.create_vertex_elements_state = si_create_vertex_elements;
2482 rctx->context.bind_vertex_elements_state = si_bind_vertex_elements;
2483 rctx->context.delete_vertex_elements_state = si_delete_vertex_element;
2484 rctx->context.set_vertex_buffers = si_set_vertex_buffers;
2485 rctx->context.set_index_buffer = si_set_index_buffer;
2486
2487 rctx->context.create_stream_output_target = si_create_so_target;
2488 rctx->context.stream_output_target_destroy = si_so_target_destroy;
2489 rctx->context.set_stream_output_targets = si_set_so_targets;
2490
2491 rctx->context.texture_barrier = si_texture_barrier;
2492 rctx->context.set_polygon_stipple = si_set_polygon_stipple;
2493
2494 rctx->context.draw_vbo = si_draw_vbo;
2495 }
2496
2497 void si_init_config(struct r600_context *rctx)
2498 {
2499 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2500
2501 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
2502 si_pm4_cmd_add(pm4, 0x80000000);
2503 si_pm4_cmd_add(pm4, 0x80000000);
2504 si_pm4_cmd_end(pm4, false);
2505
2506 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
2507
2508 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
2509 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
2510 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
2511 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
2512 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
2513 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
2514 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
2515 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
2516 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
2517 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
2518 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
2519 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
2520 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0);
2521 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
2522 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
2523 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
2524 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
2525 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
2526 S_028AA8_SWITCH_ON_EOP(1) |
2527 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
2528 S_028AA8_PRIMGROUP_SIZE(63));
2529 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
2530 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
2531 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2532
2533 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0);
2534 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
2535 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
2536
2537 si_pm4_set_reg(pm4, R_028804_DB_EQAA, 0x110000);
2538
2539 si_pm4_set_state(rctx, init, pm4);
2540 }