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[mesa.git] / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "radeonsi_pipe.h"
32 #include "radeonsi_shader.h"
33 #include "si_state.h"
34 #include "sid.h"
35
36 /*
37 * Shaders
38 */
39
40 static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader)
41 {
42 struct r600_context *rctx = (struct r600_context *)ctx;
43 struct si_pm4_state *pm4;
44 unsigned num_sgprs, num_user_sgprs;
45 unsigned nparams, i;
46 uint64_t va;
47
48 if (si_pipe_shader_create(ctx, shader))
49 return;
50
51 si_pm4_delete_state(rctx, vs, shader->pm4);
52 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
53
54 si_pm4_inval_shader_cache(pm4);
55
56 /* Certain attributes (position, psize, etc.) don't count as params.
57 * VS is required to export at least one param and r600_shader_from_tgsi()
58 * takes care of adding a dummy export.
59 */
60 for (nparams = 0, i = 0 ; i < shader->shader.noutput; i++) {
61 if (shader->shader.output[i].name != TGSI_SEMANTIC_POSITION)
62 nparams++;
63 }
64 if (nparams < 1)
65 nparams = 1;
66
67 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
68 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
69
70 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
71 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
72 S_02870C_POS1_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) |
73 S_02870C_POS2_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) |
74 S_02870C_POS3_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE));
75
76 va = r600_resource_va(ctx->screen, (void *)shader->bo);
77 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
78 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
79 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
80
81 num_user_sgprs = 8;
82 num_sgprs = shader->num_sgprs;
83 if (num_user_sgprs > num_sgprs)
84 num_sgprs = num_user_sgprs;
85 /* Last 2 reserved SGPRs are used for VCC */
86 num_sgprs += 2;
87 assert(num_sgprs <= 104);
88
89 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
90 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
91 S_00B128_SGPRS((num_sgprs - 1) / 8));
92 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
93 S_00B12C_USER_SGPR(num_user_sgprs));
94
95 si_pm4_bind_state(rctx, vs, shader->pm4);
96 }
97
98 static void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader)
99 {
100 struct r600_context *rctx = (struct r600_context *)ctx;
101 struct si_pm4_state *pm4;
102 unsigned i, exports_ps, num_cout, spi_ps_in_control, db_shader_control;
103 unsigned num_sgprs, num_user_sgprs;
104 int ninterp = 0;
105 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
106 unsigned spi_baryc_cntl, spi_ps_input_ena;
107 uint64_t va;
108
109 if (si_pipe_shader_create(ctx, shader))
110 return;
111
112 si_pm4_delete_state(rctx, ps, shader->pm4);
113 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
114
115 si_pm4_inval_shader_cache(pm4);
116
117 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
118 for (i = 0; i < shader->shader.ninput; i++) {
119 ninterp++;
120 /* XXX: Flat shading hangs the GPU */
121 if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
122 (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
123 rctx->queued.named.rasterizer->flatshade))
124 have_linear = TRUE;
125 if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
126 have_linear = TRUE;
127 if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
128 have_perspective = TRUE;
129 if (shader->shader.input[i].centroid)
130 have_centroid = TRUE;
131 }
132
133 for (i = 0; i < shader->shader.noutput; i++) {
134 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION)
135 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
136 if (shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
137 db_shader_control |= 0; // XXX OP_VAL or TEST_VAL?
138 }
139 if (shader->shader.uses_kill)
140 db_shader_control |= S_02880C_KILL_ENABLE(1);
141
142 exports_ps = 0;
143 num_cout = 0;
144 for (i = 0; i < shader->shader.noutput; i++) {
145 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION ||
146 shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
147 exports_ps |= 1;
148 else if (shader->shader.output[i].name == TGSI_SEMANTIC_COLOR) {
149 if (shader->shader.fs_write_all)
150 num_cout = shader->shader.nr_cbufs;
151 else
152 num_cout++;
153 }
154 }
155 if (!exports_ps) {
156 /* always at least export 1 component per pixel */
157 exports_ps = 2;
158 }
159
160 spi_ps_in_control = S_0286D8_NUM_INTERP(ninterp);
161
162 spi_baryc_cntl = 0;
163 if (have_perspective)
164 spi_baryc_cntl |= have_centroid ?
165 S_0286E0_PERSP_CENTROID_CNTL(1) : S_0286E0_PERSP_CENTER_CNTL(1);
166 if (have_linear)
167 spi_baryc_cntl |= have_centroid ?
168 S_0286E0_LINEAR_CENTROID_CNTL(1) : S_0286E0_LINEAR_CENTER_CNTL(1);
169
170 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
171 spi_ps_input_ena = shader->spi_ps_input_ena;
172 /* we need to enable at least one of them, otherwise we hang the GPU */
173 if (!spi_ps_input_ena & (C_0286CC_PERSP_SAMPLE_ENA |
174 C_0286CC_PERSP_CENTROID_ENA |
175 C_0286CC_PERSP_PULL_MODEL_ENA |
176 C_0286CC_LINEAR_SAMPLE_ENA |
177 C_0286CC_LINEAR_CENTER_ENA |
178 C_0286CC_LINEAR_CENTROID_ENA |
179 C_0286CC_LINE_STIPPLE_TEX_ENA)) {
180 spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
181 }
182 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
183 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
184 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
185
186 /* XXX: Depends on Z buffer format? */
187 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, 0);
188
189 va = r600_resource_va(ctx->screen, (void *)shader->bo);
190 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
191 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
192 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
193
194 num_user_sgprs = 6;
195 num_sgprs = shader->num_sgprs;
196 if (num_user_sgprs > num_sgprs)
197 num_sgprs = num_user_sgprs;
198 /* Last 2 reserved SGPRs are used for VCC */
199 num_sgprs += 2;
200 assert(num_sgprs <= 104);
201
202 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
203 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
204 S_00B028_SGPRS((num_sgprs - 1) / 8));
205 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
206 S_00B02C_USER_SGPR(num_user_sgprs));
207
208 si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
209
210 shader->sprite_coord_enable = rctx->sprite_coord_enable;
211 si_pm4_bind_state(rctx, ps, shader->pm4);
212 }
213
214 /*
215 * Drawing
216 */
217
218 static unsigned si_conv_pipe_prim(unsigned pprim)
219 {
220 static const unsigned prim_conv[] = {
221 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
222 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
223 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
224 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
225 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
226 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
227 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
228 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
229 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
230 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
231 [PIPE_PRIM_LINES_ADJACENCY] = ~0,
232 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = ~0,
233 [PIPE_PRIM_TRIANGLES_ADJACENCY] = ~0,
234 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = ~0
235 };
236 unsigned result = prim_conv[pprim];
237 if (result == ~0) {
238 R600_ERR("unsupported primitive type %d\n", pprim);
239 }
240 return result;
241 }
242
243 static bool si_update_draw_info_state(struct r600_context *rctx,
244 const struct pipe_draw_info *info)
245 {
246 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
247 unsigned prim = si_conv_pipe_prim(info->mode);
248 unsigned ls_mask = 0;
249
250 if (pm4 == NULL)
251 return false;
252
253 if (prim == ~0) {
254 FREE(pm4);
255 return false;
256 }
257
258 si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
259 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
260 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
261 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET,
262 info->indexed ? info->index_bias : info->start);
263 si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
264 si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
265 #if 0
266 si_pm4_set_reg(pm4, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
267 si_pm4_set_reg(pm4, R_03CFF4_SQ_VTX_START_INST_LOC, info->start_instance);
268 #endif
269
270 if (prim == V_008958_DI_PT_LINELIST)
271 ls_mask = 1;
272 else if (prim == V_008958_DI_PT_LINESTRIP)
273 ls_mask = 2;
274 si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE,
275 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
276 rctx->pa_sc_line_stipple);
277
278 if (info->mode == PIPE_PRIM_QUADS || info->mode == PIPE_PRIM_QUAD_STRIP || info->mode == PIPE_PRIM_POLYGON) {
279 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
280 S_028814_PROVOKING_VTX_LAST(1) | rctx->pa_su_sc_mode_cntl);
281 } else {
282 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, rctx->pa_su_sc_mode_cntl);
283 }
284 si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
285 prim == PIPE_PRIM_POINTS ? rctx->pa_cl_vs_out_cntl : 0
286 /*| (rctx->rasterizer->clip_plane_enable &
287 rctx->vs_shader->shader.clip_dist_write)*/);
288 si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL, rctx->pa_cl_clip_cntl
289 /*| (rctx->vs_shader->shader.clip_dist_write ||
290 rctx->vs_shader->shader.vs_prohibit_ucps ?
291 0 : rctx->rasterizer->clip_plane_enable & 0x3F)*/);
292
293 si_pm4_set_state(rctx, draw_info, pm4);
294 return true;
295 }
296
297 static void si_update_alpha_ref(struct r600_context *rctx)
298 {
299 #if 0
300 unsigned alpha_ref;
301 struct r600_pipe_state rstate;
302
303 alpha_ref = rctx->alpha_ref;
304 rstate.nregs = 0;
305 if (rctx->export_16bpc)
306 alpha_ref &= ~0x1FFF;
307 si_pm4_set_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref);
308
309 si_pm4_set_state(rctx, TODO, pm4);
310 rctx->alpha_ref_dirty = false;
311 #endif
312 }
313
314 static void si_update_spi_map(struct r600_context *rctx)
315 {
316 struct si_shader *ps = &rctx->ps_shader->current->shader;
317 struct si_shader *vs = &rctx->vs_shader->current->shader;
318 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
319 unsigned i, j, tmp;
320
321 for (i = 0; i < ps->ninput; i++) {
322 tmp = 0;
323
324 #if 0
325 /* XXX: Flat shading hangs the GPU */
326 if (ps->input[i].name == TGSI_SEMANTIC_POSITION ||
327 ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
328 (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
329 rctx->rasterizer && rctx->rasterizer->flatshade)) {
330 tmp |= S_028644_FLAT_SHADE(1);
331 }
332 #endif
333
334 if (ps->input[i].name == TGSI_SEMANTIC_GENERIC &&
335 rctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
336 tmp |= S_028644_PT_SPRITE_TEX(1);
337 }
338
339 for (j = 0; j < vs->noutput; j++) {
340 if (ps->input[i].name == vs->output[j].name &&
341 ps->input[i].sid == vs->output[j].sid) {
342 tmp |= S_028644_OFFSET(vs->output[j].param_offset);
343 break;
344 }
345 }
346
347 if (j == vs->noutput) {
348 /* No corresponding output found, load defaults into input */
349 tmp |= S_028644_OFFSET(0x20);
350 }
351
352 si_pm4_set_reg(pm4, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp);
353 }
354
355 si_pm4_set_state(rctx, spi, pm4);
356 }
357
358 static void si_update_derived_state(struct r600_context *rctx)
359 {
360 struct pipe_context * ctx = (struct pipe_context*)rctx;
361 unsigned ps_dirty = 0;
362
363 if (!rctx->blitter->running) {
364 if (rctx->have_depth_fb || rctx->have_depth_texture)
365 si_flush_depth_textures(rctx);
366 }
367
368 si_shader_select(ctx, rctx->ps_shader, &ps_dirty);
369
370 if (rctx->alpha_ref_dirty) {
371 si_update_alpha_ref(rctx);
372 }
373
374 if (!rctx->vs_shader->current->pm4) {
375 si_pipe_shader_vs(ctx, rctx->vs_shader->current);
376 }
377
378 if (!rctx->ps_shader->current->pm4) {
379 si_pipe_shader_ps(ctx, rctx->ps_shader->current);
380 ps_dirty = 0;
381 }
382 if (!rctx->ps_shader->current->bo) {
383 if (!rctx->dummy_pixel_shader->pm4)
384 si_pipe_shader_ps(ctx, rctx->dummy_pixel_shader);
385 else
386 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
387
388 ps_dirty = 0;
389 }
390
391 if (ps_dirty) {
392 si_pm4_bind_state(rctx, ps, rctx->ps_shader->current->pm4);
393 rctx->shader_dirty = true;
394 }
395
396 if (rctx->shader_dirty) {
397 si_update_spi_map(rctx);
398 rctx->shader_dirty = false;
399 }
400 }
401
402 static void si_vertex_buffer_update(struct r600_context *rctx)
403 {
404 struct pipe_context *ctx = &rctx->context;
405 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
406 bool bound[PIPE_MAX_ATTRIBS] = {};
407 unsigned i, count;
408 uint64_t va;
409
410 si_pm4_inval_vertex_cache(pm4);
411
412 /* bind vertex buffer once */
413 count = rctx->vertex_elements->count;
414 assert(count <= 256 / 4);
415
416 si_pm4_sh_data_begin(pm4);
417 for (i = 0 ; i < count; i++) {
418 struct pipe_vertex_element *ve = &rctx->vertex_elements->elements[i];
419 struct pipe_vertex_buffer *vb;
420 struct si_resource *rbuffer;
421 unsigned offset;
422
423 if (ve->vertex_buffer_index >= rctx->nr_vertex_buffers)
424 continue;
425
426 vb = &rctx->vertex_buffer[ve->vertex_buffer_index];
427 rbuffer = (struct si_resource*)vb->buffer;
428 if (rbuffer == NULL)
429 continue;
430
431 offset = 0;
432 offset += vb->buffer_offset;
433 offset += ve->src_offset;
434
435 va = r600_resource_va(ctx->screen, (void*)rbuffer);
436 va += offset;
437
438 /* Fill in T# buffer resource description */
439 si_pm4_sh_data_add(pm4, va & 0xFFFFFFFF);
440 si_pm4_sh_data_add(pm4, (S_008F04_BASE_ADDRESS_HI(va >> 32) |
441 S_008F04_STRIDE(vb->stride)));
442 si_pm4_sh_data_add(pm4, (vb->buffer->width0 - offset) /
443 MAX2(vb->stride, 1));
444 si_pm4_sh_data_add(pm4, rctx->vertex_elements->rsrc_word3[i]);
445
446 if (!bound[ve->vertex_buffer_index]) {
447 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
448 bound[ve->vertex_buffer_index] = true;
449 }
450 }
451 si_pm4_sh_data_end(pm4, R_00B148_SPI_SHADER_USER_DATA_VS_6);
452 si_pm4_set_state(rctx, vertex_buffers, pm4);
453 }
454
455 static void si_state_draw(struct r600_context *rctx,
456 const struct pipe_draw_info *info,
457 const struct pipe_index_buffer *ib)
458 {
459 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
460
461 /* queries need some special values
462 * (this is non-zero if any query is active) */
463 if (rctx->num_cs_dw_queries_suspend) {
464 struct si_state_dsa *dsa = rctx->queued.named.dsa;
465
466 si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
467 S_028004_PERFECT_ZPASS_COUNTS(1));
468 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
469 dsa->db_render_override |
470 S_02800C_NOOP_CULL_DISABLE(1));
471 }
472
473 /* draw packet */
474 si_pm4_cmd_begin(pm4, PKT3_INDEX_TYPE);
475 if (ib->index_size == 4) {
476 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_32 | (R600_BIG_ENDIAN ?
477 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
478 } else {
479 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (R600_BIG_ENDIAN ?
480 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
481 }
482 si_pm4_cmd_end(pm4, rctx->predicate_drawing);
483
484 si_pm4_cmd_begin(pm4, PKT3_NUM_INSTANCES);
485 si_pm4_cmd_add(pm4, info->instance_count);
486 si_pm4_cmd_end(pm4, rctx->predicate_drawing);
487
488 if (info->indexed) {
489 uint64_t va;
490 va = r600_resource_va(&rctx->screen->screen, ib->buffer);
491 va += ib->offset;
492
493 si_pm4_add_bo(pm4, (struct si_resource *)ib->buffer, RADEON_USAGE_READ);
494 si_pm4_cmd_begin(pm4, PKT3_DRAW_INDEX_2);
495 si_pm4_cmd_add(pm4, (ib->buffer->width0 - ib->offset) /
496 rctx->index_buffer.index_size);
497 si_pm4_cmd_add(pm4, va);
498 si_pm4_cmd_add(pm4, (va >> 32UL) & 0xFF);
499 si_pm4_cmd_add(pm4, info->count);
500 si_pm4_cmd_add(pm4, V_0287F0_DI_SRC_SEL_DMA);
501 si_pm4_cmd_end(pm4, rctx->predicate_drawing);
502 } else {
503 si_pm4_cmd_begin(pm4, PKT3_DRAW_INDEX_AUTO);
504 si_pm4_cmd_add(pm4, info->count);
505 si_pm4_cmd_add(pm4, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
506 (info->count_from_stream_output ?
507 S_0287F0_USE_OPAQUE(1) : 0));
508 si_pm4_cmd_end(pm4, rctx->predicate_drawing);
509 }
510 si_pm4_set_state(rctx, draw, pm4);
511 }
512
513 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
514 {
515 struct r600_context *rctx = (struct r600_context *)ctx;
516 struct pipe_index_buffer ib = {};
517 uint32_t cp_coher_cntl;
518
519 if ((!info->count && (info->indexed || !info->count_from_stream_output)) ||
520 (info->indexed && !rctx->index_buffer.buffer)) {
521 return;
522 }
523
524 if (!rctx->ps_shader || !rctx->vs_shader)
525 return;
526
527 si_update_derived_state(rctx);
528 si_vertex_buffer_update(rctx);
529
530 if (info->indexed) {
531 /* Initialize the index buffer struct. */
532 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
533 ib.index_size = rctx->index_buffer.index_size;
534 ib.offset = rctx->index_buffer.offset + info->start * ib.index_size;
535
536 /* Translate or upload, if needed. */
537 r600_translate_index_buffer(rctx, &ib, info->count);
538
539 if (ib.user_buffer) {
540 r600_upload_index_buffer(rctx, &ib, info->count);
541 }
542
543 } else if (info->count_from_stream_output) {
544 r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info->count_from_stream_output);
545 }
546
547 rctx->vs_shader_so_strides = rctx->vs_shader->current->so_strides;
548
549 if (!si_update_draw_info_state(rctx, info))
550 return;
551
552 si_state_draw(rctx, info, &ib);
553
554 cp_coher_cntl = si_pm4_sync_flags(rctx);
555 if (cp_coher_cntl) {
556 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
557 si_cmd_surface_sync(pm4, cp_coher_cntl);
558 si_pm4_set_state(rctx, sync, pm4);
559 }
560
561 /* Emit states. */
562 rctx->pm4_dirty_cdwords += si_pm4_dirty_dw(rctx);
563
564 si_need_cs_space(rctx, 0, TRUE);
565
566 si_pm4_emit_dirty(rctx);
567 rctx->pm4_dirty_cdwords = 0;
568
569 #if 0
570 /* Enable stream out if needed. */
571 if (rctx->streamout_start) {
572 r600_context_streamout_begin(rctx);
573 rctx->streamout_start = FALSE;
574 }
575 #endif
576
577
578 rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY;
579
580 if (rctx->framebuffer.zsbuf)
581 {
582 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
583 ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
584 }
585
586 pipe_resource_reference(&ib.buffer, NULL);
587 }