sim/aarch64/ChangeLog

   1 2021-06-19  Mike Frysinger  <vapier@gentoo.org>
   2
   3         * aclocal.m4: Regenerate.
   4         * configure: Regenerate.
   5
   6 2021-06-19  Mike Frysinger  <vapier@gentoo.org>
   7
   8         * configure: Regenerate.
   9
  10 2021-06-18  Mike Frysinger  <vapier@gentoo.org>
  11
  12         * aclocal.m4, configure: Regenerate.
  13
  14 2021-06-18  Mike Frysinger  <vapier@gentoo.org>
  15
  16         * configure: Regenerate.
  17
  18 2021-06-18  Mike Frysinger  <vapier@gentoo.org>
  19
  20         * cpustate.c: Include sim-signal.h.
  21         * memory.c, simulator.c: Likewise.
  22
  23 2021-06-17  Mike Frysinger  <vapier@gentoo.org>
  24
  25         * configure.ac: Delete SIM_AC_OPTION_ENDIAN call.
  26         * aclocal.m4, configure: Regenerate.
  27
  28 2021-06-16  Mike Frysinger  <vapier@gentoo.org>
  29
  30         * configure: Regenerate.
  31
  32 2021-06-16  Mike Frysinger  <vapier@gentoo.org>
  33
  34         * configure: Regenerate.
  35         * config.in: Removed.
  36
  37 2021-06-15  Mike Frysinger  <vapier@gentoo.org>
  38
  39         * config.in, configure: Regenerate.
  40
  41 2021-06-14  Mike Frysinger  <vapier@gentoo.org>
  42
  43         * configure.ac: Delete call to SIM_AC_OPTION_WARNINGS.
  44         * configure: Regenerate.
  45
  46 2021-06-12  Mike Frysinger  <vapier@gentoo.org>
  47
  48         * configure.ac: Delete call to SIM_AC_OPTION_ALIGNMENT.
  49         * interp.c (sim_open): Set current_alignment.
  50
  51 2021-06-12  Mike Frysinger  <vapier@gentoo.org>
  52
  53         * aclocal.m4, config.in, configure: Regenerate.
  54
  55 2021-06-12  Mike Frysinger  <vapier@gentoo.org>
  56
  57         * config.in, configure: Regenerate.
  58
  59 2021-05-17  Mike Frysinger  <vapier@gentoo.org>
  60
  61         * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Delete.
  62
  63 2021-05-17  Mike Frysinger  <vapier@gentoo.org>
  64
  65         * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Define.
  66         (struct sim_state): Delete.
  67
  68 2021-05-16  Mike Frysinger  <vapier@gentoo.org>
  69
  70         * cpustate.c: Include defs.h.
  71         * interp.c: Replace config.h include with defs.h.
  72         * memory.c, simulator.c: Likewise.
  73         * cpustate.h, simulator.h: Delete config.h include.
  74
  75 2021-05-16  Mike Frysinger  <vapier@gentoo.org>
  76
  77         * config.in, configure: Regenerate.
  78
  79 2021-05-14  Mike Frysinger  <vapier@gentoo.org>
  80
  81         * cpustate.h: Update include path.
  82         * interp.c: Likewise.
  83
  84 2021-05-04  Mike Frysinger  <vapier@gentoo.org>
  85
  86         * configure: Regenerate.
  87
  88 2021-05-01  Mike Frysinger  <vapier@gentoo.org>
  89
  90         * config.in, configure: Regenerate.
  91
  92 2021-05-01  Mike Frysinger  <vapier@gentoo.org>
  93
  94         * cpustate.c (aarch64_set_FP_float): Change lx to PRIx64.
  95         (aarch64_set_FP_double, aarch64_set_FP_long_double,
  96         aarch64_set_vec_u64, aarch64_set_vec_s64): Likewise.
  97
  98 2021-05-01  Mike Frysinger  <vapier@gentoo.org>
  99
 100         * simulator.c (do_fcvtzu): Change UL to ULL.
 101
 102 2021-04-26  Mike Frysinger  <vapier@gentoo.org>
 103
 104         * aclocal.m4, config.in, configure: Regenerate.
 105
 106 2021-04-22  Tom Tromey  <tom@tromey.com>
 107
 108         * configure, config.in: Rebuild.
 109
 110 2021-04-22  Tom Tromey  <tom@tromey.com>
 111
 112         * configure: Rebuild.
 113
 114 2021-04-21  Mike Frysinger  <vapier@gentoo.org>
 115
 116         * aclocal.m4: Regenerate.
 117
 118 2021-04-21  Simon Marchi  <simon.marchi@polymtl.ca>
 119
 120         * configure: Regenerate.
 121
 122 2021-04-18  Mike Frysinger  <vapier@gentoo.org>
 123
 124         * configure: Regenerate.
 125
 126 2021-04-12  Mike Frysinger  <vapier@gentoo.org>
 127
 128         * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
 129
 130 2021-04-07  Jim Wilson  <jimw@sifive.com>
 131
 132         PR sim/27483
 133         * simulator.c (set_flags_for_add32): Compare uresult against
 134         itself.  Compare sresult against itself.
 135
 136 2021-04-02  Mike Frysinger  <vapier@gentoo.org>
 137
 138         * aclocal.m4, configure: Regenerate.
 139
 140 2021-02-28  Mike Frysinger  <vapier@gentoo.org>
 141
 142         * configure: Regenerate.
 143
 144 2021-02-21  Mike Frysinger  <vapier@gentoo.org>
 145
 146         * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
 147         * aclocal.m4, configure: Regenerate.
 148
 149 2021-02-13  Mike Frysinger  <vapier@gentoo.org>
 150
 151         * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
 152         * aclocal.m4, configure: Regenerate.
 153
 154 2021-02-06  Mike Frysinger  <vapier@gentoo.org>
 155
 156         * configure: Regenerate.
 157
 158 2021-01-11  Mike Frysinger  <vapier@gentoo.org>
 159
 160         * config.in, configure: Regenerate.
 161
 162 2021-01-09  Mike Frysinger  <vapier@gentoo.org>
 163
 164         * configure: Regenerate.
 165
 166 2021-01-08  Mike Frysinger  <vapier@gentoo.org>
 167
 168         * configure: Regenerate.
 169
 170 2021-01-04  Mike Frysinger  <vapier@gentoo.org>
 171
 172         * configure: Regenerate.
 173
 174 2020-02-06  Carlo Bramini  <carlo_bramini@users.sourceforge.net>
 175
 176         PR sim/25318
 177         * simulator.c (blr): Read destination register before calling
 178         aarch64_save_LR.
 179
 180 2019-03-28  Andrew Burgess  <andrew.burgess@embecosm.com>
 181
 182         * cpustate.c: Add 'libiberty.h' include.
 183         * interp.c: Add 'sim-assert.h' include.
 184
 185 2017-09-06  John Baldwin  <jhb@FreeBSD.org>
 186
 187         * configure: Regenerate.
 188
 189 2017-04-22  Jim Wilson  <jim.wilson@linaro.org>
 190
 191         * simulator.c (vec_load): Add M argument.  Rewrite to iterate over
 192         registers based on structure size.
 193         (LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load.
 194         (LD1_1): Replace with call to vec_load.
 195         (vec_store): Add new M argument.  Rewrite to iterate over registers
 196         based on structure size.
 197         (ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store.
 198         (ST1_1): Replace with call to vec_store.
 199
 200 2017-04-08  Jim Wilson  <jim.wilson@linaro.org>
 201
 202         * simulator.c (do_vec_FCVTL): New.
 203         (do_vec_op1): Call do_vec_FCVTL.
 204
 205         * simulator.c (do_scalar_FCMGE_zero, do_scalar_FCMLE_zero,
 206         do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero, do_scalar_FCMLT_zero): New.
 207         (do_scalar_vec): Add calls to new functions.
 208
 209 2017-03-25  Jim Wilson  <jim.wilson@linaro.org>
 210
 211         * simulator.c (set_flags_for_add32): Cast result to uint32_t in carry
 212         flag check.
 213
 214 2017-03-03  Jim Wilson  <jim.wilson@linaro.org>
 215
 216         * simulator.c (mul64hi): Shift carry left by 32.
 217         (smulh): Change signum to negate.  If negate, invert result, and add
 218         carry bit if low part of multiply result is zero.
 219
 220 2017-02-25  Jim Wilson  <jim.wilson@linaro.org>
 221
 222         * simulator.c (do_vec_SMOV_into_scalar): New.
 223         (do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar.
 224         Rewritten.
 225         (do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted.
 226         (do_vec_op1): Move do_vec_TRN call and do_vec_UZP call.  Add
 227         do_vec_SMOV_into_scalar call.  Delete do_vec_MOV_into_scalar and
 228         do_vec_UMOV calls.  Add do_vec_UMOV_into_scalar call.
 229
 230         * simulator.c (popcount): New.
 231         (do_vec_CNT): New.
 232         (do_vec_op1): Add do_vec_CNT call.
 233
 234 2017-02-19  Jim Wilson  <jim.wilson@linaro.org>
 235
 236         * simulator.c (do_vec_ADDV): Mov val declaration inside each case,
 237         with type set to input type size.
 238         (do_vec_xtl): Change bias from 3 to 4 for byte case.
 239
 240 2017-02-14  Jim Wilson  <jim.wilson@linaro.org>
 241
 242         * simulator.c (do_vec_MLA): Rewrite switch body.
 243
 244         * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
 245         2.  Move test_false if inside loop.  Fix logic for computing result
 246         stored to vd.
 247
 248         * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
 249         (do_vec_LDn_single, do_vec_STn_single): New.
 250         (do_vec_LDnR): Add and set new nregs var.  Replace switch on nregs with
 251         loop over nregs using new var n.  Add n times size to address in loop.
 252         Add n to vd in loop.
 253         (do_vec_load_store): Add comment for instruction bit 24.  New var
 254         single to hold instruction bit 24.  Add new code to use single.  Move
 255         ldnr support inside single if statements.  Fix ldnr register counts
 256         inside post if statement.  Change HALT_NYI calls to HALT_UNALLOC.
 257
 258 2017-01-23  Jim Wilson  <jim.wilson@linaro.org>
 259
 260         * simulator.c (do_vec_compare): Add case 0x23 for CMTST.
 261
 262 2017-01-17  Jim Wilson  <jim.wilson@linaro.org>
 263
 264         * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
 265         aarch64_set_reg_u64.  In case 2, call HALT_UNALLOC if not full.  In
 266         case 3, call HALT_UNALLOC unconditionally.
 267         (do_vec_XTN): Delete shifts.  In case 2, change index from i + 4 to
 268         i + 2.  Delete if on bias, change index to i + bias * X.
 269
 270 2017-01-09  Jim Wilson  <jim.wilson@linaro.org>
 271
 272         * simulator.c (do_vec_UZP): Rewrite.
 273
 274 2017-01-04  Jim Wilson  <jim.wilson@linaro.org>
 275
 276         * cpustate.c: Include math.h.
 277         (aarch64_set_FP_float): Use signbit to check for signed zero.
 278         (aarch64_set_FP_double): Likewise.
 279         * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
 280         (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
 281         args same size as third arg.
 282         (fmaxnm): Use isnan instead of fpclassify.
 283         (fminnm, dmaxnm, dminnm): Likewise.
 284         (do_vec_MLS): Reverse order of subtraction operands.
 285         (dexSimpleFPCondSelect): Call aarch64_get_FP_double or
 286         aarch64_get_FP_float to get source register contents.
 287         (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
 288         DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
 289         DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
 290         (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
 291         raise_exception calls.
 292
 293 2016-12-21  Jim Wilson  <jim.wilson@linaro.org>
 294
 295         * simulator.c (set_flags_for_float_compare): Add code to handle Inf.
 296         Add comment to document NaN issue.
 297         (set_flags_for_double_compare): Likewise.
 298
 299 2016-12-13  Jim Wilson  <jim.wilson@linaro.org>
 300
 301         * simulator.c (NEG, POS): Move before set_flags_for_add64.
 302         (set_flags_for_add64): Replace with a modified copy of
 303         set_flags_for_sub64.
 304
 305 2016-12-03  Jim Wilson  <jim.wilson@linaro.org>
 306
 307         * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
 308         (dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
 309
 310 2016-12-01  Jim Wilson  <jim.wilson@linaro.org>
 311
 312         * simulator.c (fsturs): Switch use of rn and st variables.
 313         (fsturd, fsturq): Likewise
 314
 315 2016-08-15  Mike Frysinger  <vapier@gentoo.org>
 316
 317         * interp.c: Include bfd.h.
 318         (symcount, symtab, aarch64_get_sym_value): Delete.
 319         (remove_useless_symbols): Change count type to long.
 320         (aarch64_get_func): Add SIM_DESC to arg list.  Add symcount
 321         and symtab local variables.
 322         (sim_create_inferior): Delete storage.  Replace symbol code
 323         with a call to trace_load_symbols.
 324         * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h
 325         includes.
 326         (aarch64_get_heap_start): Change aarch64_get_sym_value to
 327         trace_sym_value.
 328         * memory.h: Delete bfd.h include.
 329         (mem_add_blk): Delete unused prototype.
 330         * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func.
 331         * simulator.c (aarch64_get_func): Add SIM_DESC to arg list.
 332         (aarch64_get_sym_value): Delete.
 333
 334 2016-08-12  Nick Clifton  <nickc@redhat.com>
 335
 336         * simulator.c (aarch64_step): Revert pervious delta.
 337         (aarch64_run): Call sim_events_tick after each
 338         instruction is simulated, and if necessary call
 339         sim_events_process.
 340         * simulator.h: Revert previous delta.
 341
 342 2016-08-11  Nick Clifton  <nickc@redhat.com>
 343
 344         * interp.c (sim_create_inferior): Allow for being called with a
 345         NULL abfd parameter.  If a bfd is provided, initialise the sim
 346         with that start address.
 347         * simulator.c (HALT_NYI): Just print out the numeric value of the
 348         instruction when not tracing.
 349         (aarch64_step): Change from static to global.
 350         * simulator.h: Add a prototype for aarch64_step().
 351
 352 2016-07-27  Alan Modra  <amodra@gmail.com>
 353
 354         * memory.c: Don't include libbfd.h.
 355
 356 2016-07-21  Nick Clifton  <nickc@redhat.com>
 357
 358         * simulator.c (fsqrts): Use sqrtf rather than sqrt.
 359
 360 2016-06-30  Jim Wilson  <jim.wilson@linaro.org>
 361
 362         * cpustate.h: Include config.h.
 363         (union GRegisterValue): Add WORDS_BIGENDIAN check.  For big endian code
 364         use anonymous structs to align members.
 365         * simulator.c (aarch64_step): Use sim_core_read_buffer and
 366         endian_le2h_4 to read instruction from pc.
 367
 368 2016-05-06  Nick Clifton  <nickc@redhat.com>
 369
 370         * simulator.c (do_FMLA_by_element): New function.
 371         (do_vec_op2): Call it.
 372
 373 2016-04-27  Nick Clifton  <nickc@redhat.com>
 374
 375         * simulator.c: Add TRACE_DECODE statements to all emulation
 376         functions.
 377
 378 2016-03-30  Nick Clifton  <nickc@redhat.com>
 379
 380         * cpustate.c (aarch64_set_reg_s32): New function.
 381         (aarch64_set_reg_u32): New function.
 382         (aarch64_get_FP_half): Place half precision value into the correct
 383         slot of the union.
 384         (aarch64_set_FP_half): Likewise.
 385         * cpustate.h: Add prototypes for aarch64_set_reg_s32 and
 386         aarch64_set_reg_u32.
 387         * memory.c (FETCH_FUNC): Cast the read value to the access type
 388         before converting it to the return type.  Rename to FETCH_FUNC64.
 389         (FETCH_FUNC32): New macro.  Duplicates FETCH_FUNC64 but for 32-bit
 390         accesses.  Use for 32-bit memory access functions.
 391         * simulator.c (ldrsb_wb): Use sign extension not zero extension.
 392         (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
 393         (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
 394         (ldrsh_scale_ext, ldrsw_abs): Likewise.
 395         (ldrh32_abs): Store 32 bit value not 64-bits.
 396         (ldrh32_wb, ldrh32_scale_ext): Likewise.
 397         (do_vec_MOV_immediate): Fix computation of val.
 398         (do_vec_MVNI): Likewise.
 399         (DO_VEC_WIDENING_MUL): New macro.
 400         (do_vec_mull): Use new macro.
 401         (do_vec_mul): Use new macro.
 402         (do_vec_MLA): Read values before writing.
 403         (do_vec_xtl): Likewise.
 404         (do_vec_SSHL): Select correct shift value.
 405         (do_vec_USHL): Likewise.
 406         (do_scalar_UCVTF): New function.
 407         (do_scalar_vec): Call new function.
 408         (store_pair_u64): Treat reads of SP as reads of XZR.
 409
 410 2016-03-29  Nick Clifton  <nickc@redhat.com>
 411
 412         * cpustate.c: Remove space after asterisk in function parameters.
 413         * decode.h (greg): Delete unused function.
 414         (vreg, shift, extension, scaling, writeback, condcode): Likewise.
 415         * simulator.c: Use INSTR macro in more places.
 416         (HALT_NYI): Use sim_io_eprintf in place of fprintf.
 417         Remove extraneous whitespace.
 418
 419 2016-03-23  Nick Clifton  <nickc@redhat.com>
 420
 421         * cpustate.c (aarch64_get_FP_half): New function.  Read a vector
 422         register as a half precision floating point number.
 423         (aarch64_set_FP_half): New function.  Similar, but for setting
 424         a half precision register.
 425         (aarch64_get_thread_id): New function.  Returns the value of the
 426         CPU's TPIDR register.
 427         (aarch64_get_FPCR): New function.  Returns the value of the CPU's
 428         floating point control register.
 429         (aarch64_set_FPCR): New function.  Set the value of the CPU's FPCR
 430         register.
 431         * cpustate.h: Add prototypes for new functions.
 432         * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
 433         * memory.c: Use unaligned core access functions for all memory
 434         reads and writes.
 435         * simulator.c (HALT_NYI): Generate an error message if tracing
 436         will not tell the user why the simulator is halting.
 437         (HALT_UNREACHABLE): Delete.  Delete (unneeded) uses of the macro.
 438         (INSTR): New time-saver macro.
 439         (fldrb_abs): New function.  Loads an 8-bit value using a scaled
 440         offset.
 441         (fldrh_abs): New function.  Likewise for 16-bit values.
 442         (do_vec_SSHL): Allow for negative shift values.
 443         (do_vec_USHL): Likewise.
 444         (do_vec_SHL): Correct computation of shift amount.
 445         (do_vec_SSHR_USHR): Correct decision of signed vs unsigned
 446         shifts and computation of shift value.
 447         (clz): New function.  Counts leading zero bits.
 448         (do_vec_CLZ): New function.  Implements CLZ (vector).
 449         (do_vec_MOV_element): Call do_vec_CLZ.
 450         (dexSimpleFPCondCompare): Implement.
 451         (do_FCVT_half_to_single): New function.  Implements one of the
 452         FCVT operations.
 453         (do_FCVT_half_to_double): New function.  Likewise.
 454         (do_FCVT_single_to_half): New function.  Likewise.
 455         (do_FCVT_double_to_half): New function.  Likewise.
 456         (dexSimpleFPDataProc1Source): Call new FCVT functions.
 457         (do_scalar_SHL): Handle negative shifts.
 458         (do_scalar_shift): Handle SSHR.
 459         (do_scalar_USHL): New function.
 460         (do_double_add): Simplify to just performing a double precision
 461         add operation.  Move remaining code into...
 462         (do_scalar_vec): ... New function.
 463         (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
 464         functions.
 465         (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
 466         registers.
 467         (system_set): New function.
 468         (do_MSR_immediate): New function.  Stub for now.
 469         (do_MSR_reg): New function.  Likewise. Partially implements MSR
 470         instruction.
 471         (do_SYS): New function.  Stub for now,
 472         (dexSystem): Call new functions.
 473
 474 2016-03-18  Nick Clifton  <nickc@redhat.com>
 475
 476         * cpustate.c: Remove spurious spaces from TRACE strings.
 477         Print hex equivalents of floats and doubles.
 478         Check element number against array size when accessing vector
 479         registers.
 480         (GET_VEC_ELEMENT): Fix off by one error checking for an invalid
 481         element index.
 482         (SET_VEC_ELEMENT): Likewise.
 483         (GET_VEC_ELEMENT): And fix thinko using macro arguments.
 484
 485         * memory.c: Trace memory reads when --trace-memory is enabled.
 486         Remove float and double load and store functions.
 487         * memory.h (aarch64_get_mem_float): Delete prototype.
 488         (aarch64_get_mem_double): Likewise.
 489         (aarch64_set_mem_float): Likewise.
 490         (aarch64_set_mem_double): Likewise.
 491         * simulator (IS_SET): Always return either 0 or 1.
 492         (IS_CLEAR): Likewise.
 493         (fldrs_pcrel): Load and store floats using 32-bit memory accesses
 494         and doubles using 64-bit memory accesses.
 495         (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
 496         (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
 497         (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
 498         (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
 499         (store_pair_double, load_pair_float, load_pair_double): Likewise.
 500         (do_vec_MUL_by_element): New function.
 501         (do_vec_op2): Call do_vec_MUL_by_element.
 502         (do_scalar_NEG): New function.
 503         (do_double_add): Call do_scalar_NEG.
 504
 505 2016-03-03  Nick Clifton  <nickc@redhat.com>
 506
 507         * simulator.c (set_flags_for_sub32): Correct type of signbit.
 508         (CondCompare): Swap interpretation of bit 30.
 509         (DO_ADDP): Delete macro.
 510         (do_vec_ADDP): Copy source registers before starting to update
 511         destination register.
 512         (do_vec_FADDP): Likewise.
 513         (do_vec_load_store): Fix computation of sizeof_operation.
 514         (rbit64): Fix type of constant.
 515         (aarch64_step): When displaying insn value, display all 32 bits.
 516
 517 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 518
 519         * config.in, configure: Regenerate.
 520
 521 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 522
 523         * configure: Regenerate.
 524
 525 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 526
 527         * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
 528         * configure: Regenerate.
 529
 530 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 531
 532         * configure: Regenerate.
 533
 534 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 535
 536         * configure: Regenerate.
 537
 538 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 539
 540         * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
 541         * configure: Regenerate.
 542
 543 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 544
 545         * configure: Regenerate.
 546
 547 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 548
 549         * configure: Regenerate.
 550
 551 2016-01-09  Mike Frysinger  <vapier@gentoo.org>
 552
 553         * config.in, configure: Regenerate.
 554
 555 2016-01-06  Mike Frysinger  <vapier@gentoo.org>
 556
 557         * interp.c (sim_create_inferior): Mark argv and env const.
 558         (sim_open): Mark argv const.
 559
 560 2016-01-05  Mike Frysinger  <vapier@gentoo.org>
 561
 562         * interp.c: Delete dis-asm.h include.
 563         (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
 564         (sim_create_inferior): Delete disassemble init logic.
 565         (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
 566         (sim_open): Delete sim_add_option_table call.
 567         * memory.c (mem_error): Delete disas check.
 568         * simulator.c: Delete dis-asm.h include.
 569         (disas): Delete.
 570         (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
 571         (HALT_NYI): Likewise.
 572         (handle_halt): Delete disas call.
 573         (aarch64_step): Replace disas logic with TRACE_DISASM.
 574         * simulator.h: Delete dis-asm.h include.
 575         (aarch64_print_insn): Delete.
 576
 577 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 578
 579         * simulator.c (MAX, MIN): Delete.
 580         (do_vec_maxv): Change MAX to max and MIN to min.
 581         (do_vec_fminmaxV): Likewise.
 582
 583 2016-01-04  Tristan Gingold  <gingold@adacore.com>
 584
 585         * simulator.c: Remove syscall.h include.
 586
 587 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 588
 589         * configure: Regenerate.
 590
 591 2016-01-03  Mike Frysinger  <vapier@gentoo.org>
 592
 593         * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
 594         * configure: Regenerate.
 595
 596 2016-01-02  Mike Frysinger  <vapier@gentoo.org>
 597
 598         * configure: Regenerate.
 599
 600 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 601
 602         * interp.c (sim_dis_read): Change private_data to application_data.
 603         (sim_create_inferior): Likewise.
 604
 605 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 606
 607         * Makefile.in (SIM_OBJS): Delete sim-hload.o.
 608
 609 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 610
 611         * config.in, configure: Regenerate.
 612
 613 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 614
 615         * interp.c (sim_create_inferior): Update comment and argv check.
 616
 617 2015-12-14  Nick Clifton  <nickc@redhat.com>
 618
 619         * simulator.c (system_get): New function.  Provides read
 620         access to the dczid system register.
 621         (do_mrs): New function - implements the MRS instruction.
 622         (dexSystem): Call do_mrs for the MRS instruction.  Halt on
 623         unimplemented system instructions.
 624
 625 2015-11-24  Nick Clifton  <nickc@redhat.com>
 626
 627         * configure.ac: New configure template.
 628         * aclocal.m4: Generate.
 629         * config.in: Generate.
 630         * configure: Generate.
 631         * cpustate.c: New file - functions for accessing AArch64 registers.
 632         * cpustate.h: New header.
 633         * decode.h: New header.
 634         * interp.c: New file - interface between GDB and simulator.
 635         * Makefile.in: New makefile template.
 636         * memory.c: New file - functions for simulating aarch64 memory
 637         accesses.
 638         * memory.h: New header.
 639         * sim-main.h: New header.
 640         * simulator.c: New file - aarch64 simulator functions.
 641         * simulator.h: New header.