sim/aarch64/ChangeLog

   1 2017-02-14  Jim Wilson  <jim.wilson@linaro.org>
   2
   3         * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
   4         2.  Move test_false if inside loop.  Fix logic for computing result
   5         stored to vd.
   6
   7         * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
   8         (do_vec_LDn_single, do_vec_STn_single): New.
   9         (do_vec_LDnR): Add and set new nregs var.  Replace switch on nregs with
  10         loop over nregs using new var n.  Add n times size to address in loop.
  11         Add n to vd in loop.
  12         (do_vec_load_store): Add comment for instruction bit 24.  New var
  13         single to hold instruction bit 24.  Add new code to use single.  Move
  14         ldnr support inside single if statements.  Fix ldnr register counts
  15         inside post if statement.  Change HALT_NYI calls to HALT_UNALLOC.
  16
  17 2017-01-23  Jim Wilson  <jim.wilson@linaro.org>
  18
  19         * simulator.c (do_vec_compare): Add case 0x23 for CMTST.
  20
  21 2017-01-17  Jim Wilson  <jim.wilson@linaro.org>
  22
  23         * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
  24         aarch64_set_reg_u64.  In case 2, call HALT_UNALLOC if not full.  In
  25         case 3, call HALT_UNALLOC unconditionally.
  26         (do_vec_XTN): Delete shifts.  In case 2, change index from i + 4 to
  27         i + 2.  Delete if on bias, change index to i + bias * X.
  28
  29 2017-01-09  Jim Wilson  <jim.wilson@linaro.org>
  30
  31         * simulator.c (do_vec_UZP): Rewrite.
  32
  33 2017-01-04  Jim Wilson  <jim.wilson@linaro.org>
  34
  35         * cpustate.c: Include math.h.
  36         (aarch64_set_FP_float): Use signbit to check for signed zero.
  37         (aarch64_set_FP_double): Likewise.
  38         * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
  39         (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
  40         args same size as third arg.
  41         (fmaxnm): Use isnan instead of fpclassify.
  42         (fminnm, dmaxnm, dminnm): Likewise.
  43         (do_vec_MLS): Reverse order of subtraction operands.
  44         (dexSimpleFPCondSelect): Call aarch64_get_FP_double or
  45         aarch64_get_FP_float to get source register contents.
  46         (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
  47         DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
  48         DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
  49         (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
  50         raise_exception calls.
  51
  52 2016-12-21  Jim Wilson  <jim.wilson@linaro.org>
  53
  54         * simulator.c (set_flags_for_float_compare): Add code to handle Inf.
  55         Add comment to document NaN issue.
  56         (set_flags_for_double_compare): Likewise.
  57
  58 2016-12-13  Jim Wilson  <jim.wilson@linaro.org>
  59
  60         * simulator.c (NEG, POS): Move before set_flags_for_add64.
  61         (set_flags_for_add64): Replace with a modified copy of
  62         set_flags_for_sub64.
  63
  64 2016-12-03  Jim Wilson  <jim.wilson@linaro.org>
  65
  66         * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
  67         (dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
  68
  69 2016-12-01  Jim Wilson  <jim.wilson@linaro.org>
  70
  71         * simulator.c (fsturs): Switch use of rn and st variables.
  72         (fsturd, fsturq): Likewise
  73
  74 2016-08-15  Mike Frysinger  <vapier@gentoo.org>
  75
  76         * interp.c: Include bfd.h.
  77         (symcount, symtab, aarch64_get_sym_value): Delete.
  78         (remove_useless_symbols): Change count type to long.
  79         (aarch64_get_func): Add SIM_DESC to arg list.  Add symcount
  80         and symtab local variables.
  81         (sim_create_inferior): Delete storage.  Replace symbol code
  82         with a call to trace_load_symbols.
  83         * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h
  84         includes.
  85         (aarch64_get_heap_start): Change aarch64_get_sym_value to
  86         trace_sym_value.
  87         * memory.h: Delete bfd.h include.
  88         (mem_add_blk): Delete unused prototype.
  89         * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func.
  90         * simulator.c (aarch64_get_func): Add SIM_DESC to arg list.
  91         (aarch64_get_sym_value): Delete.
  92
  93 2016-08-12  Nick Clifton  <nickc@redhat.com>
  94
  95         * simulator.c (aarch64_step): Revert pervious delta.
  96         (aarch64_run): Call sim_events_tick after each
  97         instruction is simulated, and if necessary call
  98         sim_events_process.
  99         * simulator.h: Revert previous delta.
 100
 101 2016-08-11  Nick Clifton  <nickc@redhat.com>
 102
 103         * interp.c (sim_create_inferior): Allow for being called with a
 104         NULL abfd parameter.  If a bfd is provided, initialise the sim
 105         with that start address.
 106         * simulator.c (HALT_NYI): Just print out the numeric value of the
 107         instruction when not tracing.
 108         (aarch64_step): Change from static to global.
 109         * simulator.h: Add a prototype for aarch64_step().
 110
 111 2016-07-27  Alan Modra  <amodra@gmail.com>
 112
 113         * memory.c: Don't include libbfd.h.
 114
 115 2016-07-21  Nick Clifton  <nickc@redhat.com>
 116
 117         * simulator.c (fsqrts): Use sqrtf rather than sqrt.
 118
 119 2016-06-30  Jim Wilson  <jim.wilson@linaro.org>
 120
 121         * cpustate.h: Include config.h.
 122         (union GRegisterValue): Add WORDS_BIGENDIAN check.  For big endian code
 123         use anonymous structs to align members.
 124         * simulator.c (aarch64_step): Use sim_core_read_buffer and
 125         endian_le2h_4 to read instruction from pc.
 126
 127 2016-05-06  Nick Clifton  <nickc@redhat.com>
 128
 129         * simulator.c (do_FMLA_by_element): New function.
 130         (do_vec_op2): Call it.
 131
 132 2016-04-27  Nick Clifton  <nickc@redhat.com>
 133
 134         * simulator.c: Add TRACE_DECODE statements to all emulation
 135         functions.
 136
 137 2016-03-30  Nick Clifton  <nickc@redhat.com>
 138
 139         * cpustate.c (aarch64_set_reg_s32): New function.
 140         (aarch64_set_reg_u32): New function.
 141         (aarch64_get_FP_half): Place half precision value into the correct
 142         slot of the union.
 143         (aarch64_set_FP_half): Likewise.
 144         * cpustate.h: Add prototypes for aarch64_set_reg_s32 and
 145         aarch64_set_reg_u32.
 146         * memory.c (FETCH_FUNC): Cast the read value to the access type
 147         before converting it to the return type.  Rename to FETCH_FUNC64.
 148         (FETCH_FUNC32): New macro.  Duplicates FETCH_FUNC64 but for 32-bit
 149         accesses.  Use for 32-bit memory access functions.
 150         * simulator.c (ldrsb_wb): Use sign extension not zero extension.
 151         (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
 152         (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
 153         (ldrsh_scale_ext, ldrsw_abs): Likewise.
 154         (ldrh32_abs): Store 32 bit value not 64-bits.
 155         (ldrh32_wb, ldrh32_scale_ext): Likewise.
 156         (do_vec_MOV_immediate): Fix computation of val.
 157         (do_vec_MVNI): Likewise.
 158         (DO_VEC_WIDENING_MUL): New macro.
 159         (do_vec_mull): Use new macro.
 160         (do_vec_mul): Use new macro.
 161         (do_vec_MLA): Read values before writing.
 162         (do_vec_xtl): Likewise.
 163         (do_vec_SSHL): Select correct shift value.
 164         (do_vec_USHL): Likewise.
 165         (do_scalar_UCVTF): New function.
 166         (do_scalar_vec): Call new function.
 167         (store_pair_u64): Treat reads of SP as reads of XZR.
 168
 169 2016-03-29  Nick Clifton  <nickc@redhat.com>
 170
 171         * cpustate.c: Remove space after asterisk in function parameters.
 172         * decode.h (greg): Delete unused function.
 173         (vreg, shift, extension, scaling, writeback, condcode): Likewise.
 174         * simulator.c: Use INSTR macro in more places.
 175         (HALT_NYI): Use sim_io_eprintf in place of fprintf.
 176         Remove extraneous whitespace.
 177
 178 2016-03-23  Nick Clifton  <nickc@redhat.com>
 179
 180         * cpustate.c (aarch64_get_FP_half): New function.  Read a vector
 181         register as a half precision floating point number.
 182         (aarch64_set_FP_half): New function.  Similar, but for setting
 183         a half precision register.
 184         (aarch64_get_thread_id): New function.  Returns the value of the
 185         CPU's TPIDR register.
 186         (aarch64_get_FPCR): New function.  Returns the value of the CPU's
 187         floating point control register.
 188         (aarch64_set_FPCR): New function.  Set the value of the CPU's FPCR
 189         register.
 190         * cpustate.h: Add prototypes for new functions.
 191         * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
 192         * memory.c: Use unaligned core access functions for all memory
 193         reads and writes.
 194         * simulator.c (HALT_NYI): Generate an error message if tracing
 195         will not tell the user why the simulator is halting.
 196         (HALT_UNREACHABLE): Delete.  Delete (unneeded) uses of the macro.
 197         (INSTR): New time-saver macro.
 198         (fldrb_abs): New function.  Loads an 8-bit value using a scaled
 199         offset.
 200         (fldrh_abs): New function.  Likewise for 16-bit values.
 201         (do_vec_SSHL): Allow for negative shift values.
 202         (do_vec_USHL): Likewise.
 203         (do_vec_SHL): Correct computation of shift amount.
 204         (do_vec_SSHR_USHR): Correct decision of signed vs unsigned
 205         shifts and computation of shift value.
 206         (clz): New function.  Counts leading zero bits.
 207         (do_vec_CLZ): New function.  Implements CLZ (vector).
 208         (do_vec_MOV_element): Call do_vec_CLZ.
 209         (dexSimpleFPCondCompare): Implement.
 210         (do_FCVT_half_to_single): New function.  Implements one of the
 211         FCVT operations.
 212         (do_FCVT_half_to_double): New function.  Likewise.
 213         (do_FCVT_single_to_half): New function.  Likewise.
 214         (do_FCVT_double_to_half): New function.  Likewise.
 215         (dexSimpleFPDataProc1Source): Call new FCVT functions.
 216         (do_scalar_SHL): Handle negative shifts.
 217         (do_scalar_shift): Handle SSHR.
 218         (do_scalar_USHL): New function.
 219         (do_double_add): Simplify to just performing a double precision
 220         add operation.  Move remaining code into...
 221         (do_scalar_vec): ... New function.
 222         (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
 223         functions.
 224         (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
 225         registers.
 226         (system_set): New function.
 227         (do_MSR_immediate): New function.  Stub for now.
 228         (do_MSR_reg): New function.  Likewise. Partially implements MSR
 229         instruction.
 230         (do_SYS): New function.  Stub for now,
 231         (dexSystem): Call new functions.
 232
 233 2016-03-18  Nick Clifton  <nickc@redhat.com>
 234
 235         * cpustate.c: Remove spurious spaces from TRACE strings.
 236         Print hex equivalents of floats and doubles.
 237         Check element number against array size when accessing vector
 238         registers.
 239         (GET_VEC_ELEMENT): Fix off by one error checking for an invalid
 240         element index.
 241         (SET_VEC_ELEMENT): Likewise.
 242         (GET_VEC_ELEMENT): And fix thinko using macro arguments.
 243
 244         * memory.c: Trace memory reads when --trace-memory is enabled.
 245         Remove float and double load and store functions.
 246         * memory.h (aarch64_get_mem_float): Delete prototype.
 247         (aarch64_get_mem_double): Likewise.
 248         (aarch64_set_mem_float): Likewise.
 249         (aarch64_set_mem_double): Likewise.
 250         * simulator (IS_SET): Always return either 0 or 1.
 251         (IS_CLEAR): Likewise.
 252         (fldrs_pcrel): Load and store floats using 32-bit memory accesses
 253         and doubles using 64-bit memory accesses.
 254         (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
 255         (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
 256         (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
 257         (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
 258         (store_pair_double, load_pair_float, load_pair_double): Likewise.
 259         (do_vec_MUL_by_element): New function.
 260         (do_vec_op2): Call do_vec_MUL_by_element.
 261         (do_scalar_NEG): New function.
 262         (do_double_add): Call do_scalar_NEG.
 263
 264 2016-03-03  Nick Clifton  <nickc@redhat.com>
 265
 266         * simulator.c (set_flags_for_sub32): Correct type of signbit.
 267         (CondCompare): Swap interpretation of bit 30.
 268         (DO_ADDP): Delete macro.
 269         (do_vec_ADDP): Copy source registers before starting to update
 270         destination register.
 271         (do_vec_FADDP): Likewise.
 272         (do_vec_load_store): Fix computation of sizeof_operation.
 273         (rbit64): Fix type of constant.
 274         (aarch64_step): When displaying insn value, display all 32 bits.
 275
 276 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 277
 278         * config.in, configure: Regenerate.
 279
 280 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 281
 282         * configure: Regenerate.
 283
 284 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 285
 286         * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
 287         * configure: Regenerate.
 288
 289 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 290
 291         * configure: Regenerate.
 292
 293 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 294
 295         * configure: Regenerate.
 296
 297 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 298
 299         * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
 300         * configure: Regenerate.
 301
 302 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 303
 304         * configure: Regenerate.
 305
 306 2016-01-10  Mike Frysinger  <vapier@gentoo.org>
 307
 308         * configure: Regenerate.
 309
 310 2016-01-09  Mike Frysinger  <vapier@gentoo.org>
 311
 312         * config.in, configure: Regenerate.
 313
 314 2016-01-06  Mike Frysinger  <vapier@gentoo.org>
 315
 316         * interp.c (sim_create_inferior): Mark argv and env const.
 317         (sim_open): Mark argv const.
 318
 319 2016-01-05  Mike Frysinger  <vapier@gentoo.org>
 320
 321         * interp.c: Delete dis-asm.h include.
 322         (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
 323         (sim_create_inferior): Delete disassemble init logic.
 324         (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
 325         (sim_open): Delete sim_add_option_table call.
 326         * memory.c (mem_error): Delete disas check.
 327         * simulator.c: Delete dis-asm.h include.
 328         (disas): Delete.
 329         (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
 330         (HALT_NYI): Likewise.
 331         (handle_halt): Delete disas call.
 332         (aarch64_step): Replace disas logic with TRACE_DISASM.
 333         * simulator.h: Delete dis-asm.h include.
 334         (aarch64_print_insn): Delete.
 335
 336 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 337
 338         * simulator.c (MAX, MIN): Delete.
 339         (do_vec_maxv): Change MAX to max and MIN to min.
 340         (do_vec_fminmaxV): Likewise.
 341
 342 2016-01-04  Tristan Gingold  <gingold@adacore.com>
 343
 344         * simulator.c: Remove syscall.h include.
 345
 346 2016-01-04  Mike Frysinger  <vapier@gentoo.org>
 347
 348         * configure: Regenerate.
 349
 350 2016-01-03  Mike Frysinger  <vapier@gentoo.org>
 351
 352         * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
 353         * configure: Regenerate.
 354
 355 2016-01-02  Mike Frysinger  <vapier@gentoo.org>
 356
 357         * configure: Regenerate.
 358
 359 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 360
 361         * interp.c (sim_dis_read): Change private_data to application_data.
 362         (sim_create_inferior): Likewise.
 363
 364 2015-12-27  Mike Frysinger  <vapier@gentoo.org>
 365
 366         * Makefile.in (SIM_OBJS): Delete sim-hload.o.
 367
 368 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 369
 370         * config.in, configure: Regenerate.
 371
 372 2015-12-26  Mike Frysinger  <vapier@gentoo.org>
 373
 374         * interp.c (sim_create_inferior): Update comment and argv check.
 375
 376 2015-12-14  Nick Clifton  <nickc@redhat.com>
 377
 378         * simulator.c (system_get): New function.  Provides read
 379         access to the dczid system register.
 380         (do_mrs): New function - implements the MRS instruction.
 381         (dexSystem): Call do_mrs for the MRS instruction.  Halt on
 382         unimplemented system instructions.
 383
 384 2015-11-24  Nick Clifton  <nickc@redhat.com>
 385
 386         * configure.ac: New configure template.
 387         * aclocal.m4: Generate.
 388         * config.in: Generate.
 389         * configure: Generate.
 390         * cpustate.c: New file - functions for accessing AArch64 registers.
 391         * cpustate.h: New header.
 392         * decode.h: New header.
 393         * interp.c: New file - interface between GDB and simulator.
 394         * Makefile.in: New makefile template.
 395         * memory.c: New file - functions for simulating aarch64 memory
 396         accesses.
 397         * memory.h: New header.
 398         * sim-main.h: New header.
 399         * simulator.c: New file - aarch64 simulator functions.
 400         * simulator.h: New header.