1 /* cpustate.h -- Prototypes for AArch64 simulator functions.
3 Copyright (C) 2015-2021 Free Software Foundation, Inc.
5 Contributed by Red Hat.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 /* This must come before any other includes. */
29 #include "sim-signal.h"
31 #include "simulator.h"
32 #include "libiberty.h"
34 /* Some operands are allowed to access the stack pointer (reg 31).
35 For others a read from r31 always returns 0, and a write to r31 is ignored. */
36 #define reg_num(reg) (((reg) == R31 && !r31_is_sp) ? 32 : (reg))
39 aarch64_set_reg_u64 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
, uint64_t val
)
41 if (reg
== R31
&& ! r31_is_sp
)
43 TRACE_REGISTER (cpu
, "GR[31] NOT CHANGED!");
47 if (val
!= cpu
->gr
[reg
].u64
)
49 "GR[%2d] changes from %16" PRIx64
" to %16" PRIx64
,
50 reg
, cpu
->gr
[reg
].u64
, val
);
52 cpu
->gr
[reg
].u64
= val
;
56 aarch64_set_reg_s64 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
, int64_t val
)
58 if (reg
== R31
&& ! r31_is_sp
)
60 TRACE_REGISTER (cpu
, "GR[31] NOT CHANGED!");
64 if (val
!= cpu
->gr
[reg
].s64
)
66 "GR[%2d] changes from %16" PRIx64
" to %16" PRIx64
,
67 reg
, cpu
->gr
[reg
].s64
, val
);
69 cpu
->gr
[reg
].s64
= val
;
73 aarch64_get_reg_u64 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
75 return cpu
->gr
[reg_num(reg
)].u64
;
79 aarch64_get_reg_s64 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
81 return cpu
->gr
[reg_num(reg
)].s64
;
85 aarch64_get_reg_u32 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
87 return cpu
->gr
[reg_num(reg
)].u32
;
91 aarch64_get_reg_s32 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
93 return cpu
->gr
[reg_num(reg
)].s32
;
97 aarch64_set_reg_s32 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
, int32_t val
)
99 if (reg
== R31
&& ! r31_is_sp
)
101 TRACE_REGISTER (cpu
, "GR[31] NOT CHANGED!");
105 if (val
!= cpu
->gr
[reg
].s32
)
106 TRACE_REGISTER (cpu
, "GR[%2d] changes from %8x to %8x",
107 reg
, cpu
->gr
[reg
].s32
, val
);
109 /* The ARM ARM states that (C1.2.4):
110 When the data size is 32 bits, the lower 32 bits of the
111 register are used and the upper 32 bits are ignored on
112 a read and cleared to zero on a write.
113 We simulate this by first clearing the whole 64-bits and
114 then writing to the 32-bit value in the GRegister union. */
115 cpu
->gr
[reg
].s64
= 0;
116 cpu
->gr
[reg
].s32
= val
;
120 aarch64_set_reg_u32 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
, uint32_t val
)
122 if (reg
== R31
&& ! r31_is_sp
)
124 TRACE_REGISTER (cpu
, "GR[31] NOT CHANGED!");
128 if (val
!= cpu
->gr
[reg
].u32
)
129 TRACE_REGISTER (cpu
, "GR[%2d] changes from %8x to %8x",
130 reg
, cpu
->gr
[reg
].u32
, val
);
132 cpu
->gr
[reg
].u64
= 0;
133 cpu
->gr
[reg
].u32
= val
;
137 aarch64_get_reg_u16 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
139 return cpu
->gr
[reg_num(reg
)].u16
;
143 aarch64_get_reg_s16 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
145 return cpu
->gr
[reg_num(reg
)].s16
;
149 aarch64_get_reg_u8 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
151 return cpu
->gr
[reg_num(reg
)].u8
;
155 aarch64_get_reg_s8 (sim_cpu
*cpu
, GReg reg
, int r31_is_sp
)
157 return cpu
->gr
[reg_num(reg
)].s8
;
161 aarch64_get_PC (sim_cpu
*cpu
)
167 aarch64_get_next_PC (sim_cpu
*cpu
)
173 aarch64_set_next_PC (sim_cpu
*cpu
, uint64_t next
)
175 if (next
!= cpu
->nextpc
+ 4)
177 "NextPC changes from %16" PRIx64
" to %16" PRIx64
,
184 aarch64_set_next_PC_by_offset (sim_cpu
*cpu
, int64_t offset
)
186 if (cpu
->pc
+ offset
!= cpu
->nextpc
+ 4)
188 "NextPC changes from %16" PRIx64
" to %16" PRIx64
,
189 cpu
->nextpc
, cpu
->pc
+ offset
);
191 cpu
->nextpc
= cpu
->pc
+ offset
;
194 /* Install nextpc as current pc. */
196 aarch64_update_PC (sim_cpu
*cpu
)
198 cpu
->pc
= cpu
->nextpc
;
199 /* Rezero the register we hand out when asked for ZR just in case it
200 was used as the destination for a write by the previous
202 cpu
->gr
[32].u64
= 0UL;
205 /* This instruction can be used to save the next PC to LR
206 just before installing a branch PC. */
208 aarch64_save_LR (sim_cpu
*cpu
)
210 if (cpu
->gr
[LR
].u64
!= cpu
->nextpc
)
212 "LR changes from %16" PRIx64
" to %16" PRIx64
,
213 cpu
->gr
[LR
].u64
, cpu
->nextpc
);
215 cpu
->gr
[LR
].u64
= cpu
->nextpc
;
219 decode_cpsr (FlagMask flags
)
221 switch (flags
& CPSR_ALL_FLAGS
)
224 case 0: return "----";
225 case 1: return "---V";
226 case 2: return "--C-";
227 case 3: return "--CV";
228 case 4: return "-Z--";
229 case 5: return "-Z-V";
230 case 6: return "-ZC-";
231 case 7: return "-ZCV";
232 case 8: return "N---";
233 case 9: return "N--V";
234 case 10: return "N-C-";
235 case 11: return "N-CV";
236 case 12: return "NZ--";
237 case 13: return "NZ-V";
238 case 14: return "NZC-";
239 case 15: return "NZCV";
243 /* Retrieve the CPSR register as an int. */
245 aarch64_get_CPSR (sim_cpu
*cpu
)
250 /* Set the CPSR register as an int. */
252 aarch64_set_CPSR (sim_cpu
*cpu
, uint32_t new_flags
)
254 if (TRACE_REGISTER_P (cpu
))
256 if (cpu
->CPSR
!= new_flags
)
258 "CPSR changes from %s to %s",
259 decode_cpsr (cpu
->CPSR
), decode_cpsr (new_flags
));
262 "CPSR stays at %s", decode_cpsr (cpu
->CPSR
));
265 cpu
->CPSR
= new_flags
& CPSR_ALL_FLAGS
;
268 /* Read a specific subset of the CPSR as a bit pattern. */
270 aarch64_get_CPSR_bits (sim_cpu
*cpu
, FlagMask mask
)
272 return cpu
->CPSR
& mask
;
275 /* Assign a specific subset of the CPSR as a bit pattern. */
277 aarch64_set_CPSR_bits (sim_cpu
*cpu
, uint32_t mask
, uint32_t value
)
279 uint32_t old_flags
= cpu
->CPSR
;
281 mask
&= CPSR_ALL_FLAGS
;
283 cpu
->CPSR
|= (value
& mask
);
285 if (old_flags
!= cpu
->CPSR
)
287 "CPSR changes from %s to %s",
288 decode_cpsr (old_flags
), decode_cpsr (cpu
->CPSR
));
291 /* Test the value of a single CPSR returned as non-zero or zero. */
293 aarch64_test_CPSR_bit (sim_cpu
*cpu
, FlagMask bit
)
295 return cpu
->CPSR
& bit
;
298 /* Set a single flag in the CPSR. */
300 aarch64_set_CPSR_bit (sim_cpu
*cpu
, FlagMask bit
)
302 uint32_t old_flags
= cpu
->CPSR
;
304 cpu
->CPSR
|= (bit
& CPSR_ALL_FLAGS
);
306 if (old_flags
!= cpu
->CPSR
)
308 "CPSR changes from %s to %s",
309 decode_cpsr (old_flags
), decode_cpsr (cpu
->CPSR
));
312 /* Clear a single flag in the CPSR. */
314 aarch64_clear_CPSR_bit (sim_cpu
*cpu
, FlagMask bit
)
316 uint32_t old_flags
= cpu
->CPSR
;
318 cpu
->CPSR
&= ~(bit
& CPSR_ALL_FLAGS
);
320 if (old_flags
!= cpu
->CPSR
)
322 "CPSR changes from %s to %s",
323 decode_cpsr (old_flags
), decode_cpsr (cpu
->CPSR
));
327 aarch64_get_FP_half (sim_cpu
*cpu
, VReg reg
)
336 u
.h
[1] = cpu
->fr
[reg
].h
[0];
342 aarch64_get_FP_float (sim_cpu
*cpu
, VReg reg
)
344 return cpu
->fr
[reg
].s
;
348 aarch64_get_FP_double (sim_cpu
*cpu
, VReg reg
)
350 return cpu
->fr
[reg
].d
;
354 aarch64_get_FP_long_double (sim_cpu
*cpu
, VReg reg
, FRegister
*a
)
356 a
->v
[0] = cpu
->fr
[reg
].v
[0];
357 a
->v
[1] = cpu
->fr
[reg
].v
[1];
361 aarch64_set_FP_half (sim_cpu
*cpu
, VReg reg
, float val
)
370 cpu
->fr
[reg
].h
[0] = u
.h
[1];
371 cpu
->fr
[reg
].h
[1] = 0;
376 aarch64_set_FP_float (sim_cpu
*cpu
, VReg reg
, float val
)
378 if (val
!= cpu
->fr
[reg
].s
379 /* Handle +/- zero. */
380 || signbit (val
) != signbit (cpu
->fr
[reg
].s
))
386 "FR[%d].s changes from %f to %f [hex: %0" PRIx64
"]",
387 reg
, cpu
->fr
[reg
].s
, val
, v
.v
[0]);
390 cpu
->fr
[reg
].s
= val
;
394 aarch64_set_FP_double (sim_cpu
*cpu
, VReg reg
, double val
)
396 if (val
!= cpu
->fr
[reg
].d
397 /* Handle +/- zero. */
398 || signbit (val
) != signbit (cpu
->fr
[reg
].d
))
404 "FR[%d].d changes from %f to %f [hex: %0" PRIx64
"]",
405 reg
, cpu
->fr
[reg
].d
, val
, v
.v
[0]);
407 cpu
->fr
[reg
].d
= val
;
411 aarch64_set_FP_long_double (sim_cpu
*cpu
, VReg reg
, FRegister a
)
413 if (cpu
->fr
[reg
].v
[0] != a
.v
[0]
414 || cpu
->fr
[reg
].v
[1] != a
.v
[1])
416 "FR[%d].q changes from [%0" PRIx64
" %0" PRIx64
"] to [%0"
417 PRIx64
" %0" PRIx64
"] ",
419 cpu
->fr
[reg
].v
[0], cpu
->fr
[reg
].v
[1],
422 cpu
->fr
[reg
].v
[0] = a
.v
[0];
423 cpu
->fr
[reg
].v
[1] = a
.v
[1];
426 #define GET_VEC_ELEMENT(REG, ELEMENT, FIELD) \
429 if (ELEMENT >= ARRAY_SIZE (cpu->fr[0].FIELD)) \
431 TRACE_REGISTER (cpu, \
432 "Internal SIM error: invalid element number: %d ",\
434 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, aarch64_get_PC (cpu), \
435 sim_stopped, SIM_SIGBUS); \
437 return cpu->fr[REG].FIELD [ELEMENT]; \
442 aarch64_get_vec_u64 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
444 GET_VEC_ELEMENT (reg
, element
, v
);
448 aarch64_get_vec_u32 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
450 GET_VEC_ELEMENT (reg
, element
, w
);
454 aarch64_get_vec_u16 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
456 GET_VEC_ELEMENT (reg
, element
, h
);
460 aarch64_get_vec_u8 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
462 GET_VEC_ELEMENT (reg
, element
, b
);
466 aarch64_get_vec_s64 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
468 GET_VEC_ELEMENT (reg
, element
, V
);
472 aarch64_get_vec_s32 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
474 GET_VEC_ELEMENT (reg
, element
, W
);
478 aarch64_get_vec_s16 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
480 GET_VEC_ELEMENT (reg
, element
, H
);
484 aarch64_get_vec_s8 (sim_cpu
*cpu
, VReg reg
, unsigned element
)
486 GET_VEC_ELEMENT (reg
, element
, B
);
490 aarch64_get_vec_float (sim_cpu
*cpu
, VReg reg
, unsigned element
)
492 GET_VEC_ELEMENT (reg
, element
, S
);
496 aarch64_get_vec_double (sim_cpu
*cpu
, VReg reg
, unsigned element
)
498 GET_VEC_ELEMENT (reg
, element
, D
);
502 #define SET_VEC_ELEMENT(REG, ELEMENT, VAL, FIELD, PRINTER) \
505 if (ELEMENT >= ARRAY_SIZE (cpu->fr[0].FIELD)) \
507 TRACE_REGISTER (cpu, \
508 "Internal SIM error: invalid element number: %d ",\
510 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, aarch64_get_PC (cpu), \
511 sim_stopped, SIM_SIGBUS); \
513 if (VAL != cpu->fr[REG].FIELD [ELEMENT]) \
514 TRACE_REGISTER (cpu, \
515 "VR[%2d]." #FIELD " [%d] changes from " PRINTER \
516 " to " PRINTER , REG, \
517 ELEMENT, cpu->fr[REG].FIELD [ELEMENT], VAL); \
519 cpu->fr[REG].FIELD [ELEMENT] = VAL; \
524 aarch64_set_vec_u64 (sim_cpu
*cpu
, VReg reg
, unsigned element
, uint64_t val
)
526 SET_VEC_ELEMENT (reg
, element
, val
, v
, "%16" PRIx64
);
530 aarch64_set_vec_u32 (sim_cpu
*cpu
, VReg reg
, unsigned element
, uint32_t val
)
532 SET_VEC_ELEMENT (reg
, element
, val
, w
, "%8x");
536 aarch64_set_vec_u16 (sim_cpu
*cpu
, VReg reg
, unsigned element
, uint16_t val
)
538 SET_VEC_ELEMENT (reg
, element
, val
, h
, "%4x");
542 aarch64_set_vec_u8 (sim_cpu
*cpu
, VReg reg
, unsigned element
, uint8_t val
)
544 SET_VEC_ELEMENT (reg
, element
, val
, b
, "%x");
548 aarch64_set_vec_s64 (sim_cpu
*cpu
, VReg reg
, unsigned element
, int64_t val
)
550 SET_VEC_ELEMENT (reg
, element
, val
, V
, "%16" PRIx64
);
554 aarch64_set_vec_s32 (sim_cpu
*cpu
, VReg reg
, unsigned element
, int32_t val
)
556 SET_VEC_ELEMENT (reg
, element
, val
, W
, "%8x");
560 aarch64_set_vec_s16 (sim_cpu
*cpu
, VReg reg
, unsigned element
, int16_t val
)
562 SET_VEC_ELEMENT (reg
, element
, val
, H
, "%4x");
566 aarch64_set_vec_s8 (sim_cpu
*cpu
, VReg reg
, unsigned element
, int8_t val
)
568 SET_VEC_ELEMENT (reg
, element
, val
, B
, "%x");
572 aarch64_set_vec_float (sim_cpu
*cpu
, VReg reg
, unsigned element
, float val
)
574 SET_VEC_ELEMENT (reg
, element
, val
, S
, "%f");
578 aarch64_set_vec_double (sim_cpu
*cpu
, VReg reg
, unsigned element
, double val
)
580 SET_VEC_ELEMENT (reg
, element
, val
, D
, "%f");
584 aarch64_set_FPSR (sim_cpu
*cpu
, uint32_t value
)
586 if (cpu
->FPSR
!= value
)
588 "FPSR changes from %x to %x", cpu
->FPSR
, value
);
590 cpu
->FPSR
= value
& FPSR_ALL_FPSRS
;
594 aarch64_get_FPSR (sim_cpu
*cpu
)
600 aarch64_set_FPSR_bits (sim_cpu
*cpu
, uint32_t mask
, uint32_t value
)
602 uint32_t old_FPSR
= cpu
->FPSR
;
604 mask
&= FPSR_ALL_FPSRS
;
606 cpu
->FPSR
|= (value
& mask
);
608 if (cpu
->FPSR
!= old_FPSR
)
610 "FPSR changes from %x to %x", old_FPSR
, cpu
->FPSR
);
614 aarch64_get_FPSR_bits (sim_cpu
*cpu
, uint32_t mask
)
616 mask
&= FPSR_ALL_FPSRS
;
617 return cpu
->FPSR
& mask
;
621 aarch64_test_FPSR_bit (sim_cpu
*cpu
, FPSRMask flag
)
623 return cpu
->FPSR
& flag
;
627 aarch64_get_thread_id (sim_cpu
*cpu
)
633 aarch64_get_FPCR (sim_cpu
*cpu
)
639 aarch64_set_FPCR (sim_cpu
*cpu
, uint32_t val
)
641 if (cpu
->FPCR
!= val
)
643 "FPCR changes from %x to %x", cpu
->FPCR
, val
);