1 /* armdefs.h -- ARMulator common definitions: ARM6 Instruction Emulator.
2 Copyright (C) 1994 Advanced RISC Machines Ltd.
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 3 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, see <http://www.gnu.org/licenses/>. */
29 typedef uint32_t ARMword
;
30 typedef int32_t ARMsword
;
31 typedef uint64_t ARMdword
;
32 typedef int64_t ARMsdword
;
33 typedef struct ARMul_State ARMul_State
;
35 typedef unsigned ARMul_CPInits (ARMul_State
* state
);
36 typedef unsigned ARMul_CPExits (ARMul_State
* state
);
37 typedef unsigned ARMul_LDCs (ARMul_State
* state
, unsigned type
,
38 ARMword instr
, ARMword value
);
39 typedef unsigned ARMul_STCs (ARMul_State
* state
, unsigned type
,
40 ARMword instr
, ARMword
* value
);
41 typedef unsigned ARMul_MRCs (ARMul_State
* state
, unsigned type
,
42 ARMword instr
, ARMword
* value
);
43 typedef unsigned ARMul_MCRs (ARMul_State
* state
, unsigned type
,
44 ARMword instr
, ARMword value
);
45 typedef unsigned ARMul_CDPs (ARMul_State
* state
, unsigned type
,
47 typedef unsigned ARMul_CPReads (ARMul_State
* state
, unsigned reg
,
49 typedef unsigned ARMul_CPWrites (ARMul_State
* state
, unsigned reg
,
54 ARMword Emulate
; /* to start and stop emulation */
55 unsigned EndCondition
; /* reason for stopping */
56 unsigned ErrorCode
; /* type of illegal instruction */
57 ARMword Reg
[16]; /* the current register file */
58 ARMword RegBank
[7][16]; /* all the registers */
59 /* 40 bit accumulator. We always keep this 64 bits wide,
60 and move only 40 bits out of it in an MRA insn. */
62 ARMword Cpsr
; /* the current psr */
63 ARMword Spsr
[7]; /* the exception psr's */
64 ARMword NFlag
, ZFlag
, CFlag
, VFlag
, IFFlags
; /* dummy flags for speed */
67 ARMword TFlag
; /* Thumb state */
69 ARMword Bank
; /* the current register bank */
70 ARMword Mode
; /* the current mode */
71 ARMword instr
, pc
, temp
; /* saved register state */
72 ARMword loaded
, decoded
; /* saved pipeline state */
73 unsigned long NumScycles
, NumNcycles
, NumIcycles
, NumCcycles
, NumFcycles
; /* emulated cycles used */
74 unsigned long NumInstrs
; /* the number of instructions executed */
76 unsigned VectorCatch
; /* caught exception mask */
77 unsigned CallDebug
; /* set to call the debugger */
78 unsigned CanWatch
; /* set by memory interface if its willing to suffer the
79 overhead of checking for watchpoints on each memory
81 unsigned MemReadDebug
, MemWriteDebug
;
82 unsigned long StopHandle
;
84 unsigned char *MemDataPtr
; /* admin data */
85 unsigned char *MemInPtr
; /* the Data In bus */
86 unsigned char *MemOutPtr
; /* the Data Out bus (which you may not need */
87 unsigned char *MemSparePtr
; /* extra space */
90 unsigned char *OSptr
; /* OS Handle */
91 char *CommandLine
; /* Command Line from ARMsd */
93 ARMul_CPInits
*CPInit
[16]; /* coprocessor initialisers */
94 ARMul_CPExits
*CPExit
[16]; /* coprocessor finalisers */
95 ARMul_LDCs
*LDC
[16]; /* LDC instruction */
96 ARMul_STCs
*STC
[16]; /* STC instruction */
97 ARMul_MRCs
*MRC
[16]; /* MRC instruction */
98 ARMul_MCRs
*MCR
[16]; /* MCR instruction */
99 ARMul_CDPs
*CDP
[16]; /* CDP instruction */
100 ARMul_CPReads
*CPRead
[16]; /* Read CP register */
101 ARMul_CPWrites
*CPWrite
[16]; /* Write CP register */
102 unsigned char *CPData
[16]; /* Coprocessor data */
103 unsigned char const *CPRegWords
[16]; /* map of coprocessor register sizes */
104 unsigned long LastTime
; /* Value of last call to ARMul_Time() */
105 ARMword CP14R0_CCD
; /* used to count 64 clock cycles with CP14 R0 bit
108 unsigned EventSet
; /* the number of events in the queue */
109 unsigned long Now
; /* time to the nearest cycle */
110 struct EventNode
**EventPtr
; /* the event list */
112 unsigned Exception
; /* enable the next four values */
113 unsigned Debug
; /* show instructions as they are executed */
114 unsigned NresetSig
; /* reset the processor */
124 ARMword Vector
; /* synthesize aborts in cycle modes */
125 ARMword Aborted
; /* sticky flag for aborts */
126 ARMword Reseted
; /* sticky flag for Reset */
127 ARMword Inted
, LastInted
; /* sticky flags for interrupts */
128 ARMword Base
; /* extra hand for base writeback */
129 ARMword AbortAddr
; /* to keep track of Prefetch aborts */
131 const struct Dbg_HostosInterface
*hostif
;
133 unsigned is_v4
; /* Are we emulating a v4 architecture (or higher) ? */
134 unsigned is_v5
; /* Are we emulating a v5 architecture ? */
135 unsigned is_v5e
; /* Are we emulating a v5e architecture ? */
136 unsigned is_v6
; /* Are we emulating a v6 architecture ? */
137 unsigned is_XScale
; /* Are we emulating an XScale architecture ? */
138 unsigned is_iWMMXt
; /* Are we emulating an iWMMXt co-processor ? */
139 unsigned is_ep9312
; /* Are we emulating a Cirrus Maverick co-processor ? */
140 unsigned verbose
; /* Print various messages like the banner */
143 #define ResetPin NresetSig
144 #define FIQPin NfiqSig
145 #define IRQPin NirqSig
146 #define AbortPin abortSig
147 #define TransPin NtransSig
148 #define BigEndPin bigendSig
149 #define Prog32Pin prog32Sig
150 #define Data32Pin data32Sig
151 #define LateAbortPin lateabtSig
153 /***************************************************************************\
154 * Properties of ARM we know about *
155 \***************************************************************************/
158 #define ARM_Fix26_Prop 0x01
159 #define ARM_Nexec_Prop 0x02
160 #define ARM_Debug_Prop 0x10
161 #define ARM_Isync_Prop ARM_Debug_Prop
162 #define ARM_Lock_Prop 0x20
163 #define ARM_v4_Prop 0x40
164 #define ARM_v5_Prop 0x80
165 #define ARM_v5e_Prop 0x100
166 #define ARM_XScale_Prop 0x200
167 #define ARM_ep9312_Prop 0x400
168 #define ARM_iWMMXt_Prop 0x800
169 #define ARM_v6_Prop 0x1000
171 /***************************************************************************\
172 * Macros to extract instruction fields *
173 \***************************************************************************/
175 #define BIT(n) ( (ARMword)(instr>>(n))&1) /* bit n of instruction */
176 #define BITS(m,n) ( (ARMword)(instr<<(31-(n))) >> ((31-(n))+(m)) ) /* bits m to n of instr */
177 #define TOPBITS(n) (instr >> (n)) /* bits 31 to n of instr */
179 /***************************************************************************\
180 * The hardware vector addresses *
181 \***************************************************************************/
184 #define ARMUndefinedInstrV 4L
186 #define ARMPrefetchAbortV 12L
187 #define ARMDataAbortV 16L
188 #define ARMAddrExceptnV 20L
191 #define ARMErrorV 32L /* This is an offset, not an address ! */
193 #define ARMul_ResetV ARMResetV
194 #define ARMul_UndefinedInstrV ARMUndefinedInstrV
195 #define ARMul_SWIV ARMSWIV
196 #define ARMul_PrefetchAbortV ARMPrefetchAbortV
197 #define ARMul_DataAbortV ARMDataAbortV
198 #define ARMul_AddrExceptnV ARMAddrExceptnV
199 #define ARMul_IRQV ARMIRQV
200 #define ARMul_FIQV ARMFIQV
202 /***************************************************************************\
203 * Mode and Bank Constants *
204 \***************************************************************************/
206 #define USER26MODE 0L
210 #define USER32MODE 16L
211 #define FIQ32MODE 17L
212 #define IRQ32MODE 18L
213 #define SVC32MODE 19L
214 #define ABORT32MODE 23L
215 #define UNDEF32MODE 27L
216 #define SYSTEMMODE 31L
218 #define ARM32BITMODE (state->Mode > 3)
219 #define ARM26BITMODE (state->Mode <= 3)
220 #define ARMMODE (state->Mode)
221 #define ARMul_MODEBITS 0x1fL
222 #define ARMul_MODE32BIT ARM32BITMODE
223 #define ARMul_MODE26BIT ARM26BITMODE
232 #define SYSTEMBANK USERBANK
234 #define BANK_CAN_ACCESS_SPSR(bank) \
235 ((bank) != USERBANK && (bank) != SYSTEMBANK && (bank) != DUMMYBANK)
237 /***************************************************************************\
238 * Definitons of things in the emulator *
239 \***************************************************************************/
241 extern void ARMul_EmulateInit (void);
242 extern ARMul_State
*ARMul_NewState (void);
243 extern void ARMul_Reset (ARMul_State
* state
);
244 extern ARMword
ARMul_DoProg (ARMul_State
* state
);
245 extern ARMword
ARMul_DoInstr (ARMul_State
* state
);
247 /***************************************************************************\
248 * Definitons of things for event handling *
249 \***************************************************************************/
251 extern void ARMul_ScheduleEvent (ARMul_State
* state
, unsigned long delay
,
252 unsigned (*func
) ());
253 extern void ARMul_EnvokeEvent (ARMul_State
* state
);
254 extern unsigned long ARMul_Time (ARMul_State
* state
);
256 /***************************************************************************\
257 * Useful support routines *
258 \***************************************************************************/
260 extern ARMword
ARMul_GetReg (ARMul_State
* state
, unsigned mode
,
262 extern void ARMul_SetReg (ARMul_State
* state
, unsigned mode
, unsigned reg
,
264 extern ARMword
ARMul_GetPC (ARMul_State
* state
);
265 extern ARMword
ARMul_GetNextPC (ARMul_State
* state
);
266 extern void ARMul_SetPC (ARMul_State
* state
, ARMword value
);
267 extern ARMword
ARMul_GetR15 (ARMul_State
* state
);
268 extern void ARMul_SetR15 (ARMul_State
* state
, ARMword value
);
270 extern ARMword
ARMul_GetCPSR (ARMul_State
* state
);
271 extern void ARMul_SetCPSR (ARMul_State
* state
, ARMword value
);
272 extern ARMword
ARMul_GetSPSR (ARMul_State
* state
, ARMword mode
);
273 extern void ARMul_SetSPSR (ARMul_State
* state
, ARMword mode
, ARMword value
);
275 /***************************************************************************\
276 * Definitons of things to handle aborts *
277 \***************************************************************************/
279 extern void ARMul_Abort (ARMul_State
* state
, ARMword address
);
280 #define ARMul_ABORTWORD 0xefffffff /* SWI -1 */
281 #define ARMul_PREFETCHABORT(address) if (state->AbortAddr == 1) \
282 state->AbortAddr = (address & ~3L)
283 #define ARMul_DATAABORT(address) state->abortSig = HIGH ; \
284 state->Aborted = ARMul_DataAbortV ;
285 #define ARMul_CLEARABORT state->abortSig = LOW
287 /***************************************************************************\
288 * Definitons of things in the memory interface *
289 \***************************************************************************/
291 extern unsigned ARMul_MemoryInit (ARMul_State
* state
,
292 unsigned long initmemsize
);
293 extern void ARMul_MemoryExit (ARMul_State
* state
);
295 extern ARMword
ARMul_LoadInstrS (ARMul_State
* state
, ARMword address
,
297 extern ARMword
ARMul_LoadInstrN (ARMul_State
* state
, ARMword address
,
299 extern ARMword
ARMul_ReLoadInstr (ARMul_State
* state
, ARMword address
,
302 extern ARMword
ARMul_LoadWordS (ARMul_State
* state
, ARMword address
);
303 extern ARMword
ARMul_LoadWordN (ARMul_State
* state
, ARMword address
);
304 extern ARMword
ARMul_LoadHalfWord (ARMul_State
* state
, ARMword address
);
305 extern ARMword
ARMul_LoadByte (ARMul_State
* state
, ARMword address
);
307 extern void ARMul_StoreWordS (ARMul_State
* state
, ARMword address
,
309 extern void ARMul_StoreWordN (ARMul_State
* state
, ARMword address
,
311 extern void ARMul_StoreHalfWord (ARMul_State
* state
, ARMword address
,
313 extern void ARMul_StoreByte (ARMul_State
* state
, ARMword address
,
316 extern ARMword
ARMul_SwapWord (ARMul_State
* state
, ARMword address
,
318 extern ARMword
ARMul_SwapByte (ARMul_State
* state
, ARMword address
,
321 extern void ARMul_Icycles (ARMul_State
* state
, unsigned number
,
323 extern void ARMul_Ccycles (ARMul_State
* state
, unsigned number
,
326 extern ARMword
ARMul_ReadWord (ARMul_State
* state
, ARMword address
);
327 extern ARMword
ARMul_ReadByte (ARMul_State
* state
, ARMword address
);
328 extern ARMword
ARMul_SafeReadByte (ARMul_State
* state
, ARMword address
);
329 extern void ARMul_WriteWord (ARMul_State
* state
, ARMword address
,
331 extern void ARMul_WriteByte (ARMul_State
* state
, ARMword address
,
333 extern void ARMul_SafeWriteByte (ARMul_State
* state
, ARMword address
,
336 extern ARMword
ARMul_MemAccess (ARMul_State
* state
, ARMword
, ARMword
,
337 ARMword
, ARMword
, ARMword
, ARMword
, ARMword
,
338 ARMword
, ARMword
, ARMword
);
340 /***************************************************************************\
341 * Definitons of things in the co-processor interface *
342 \***************************************************************************/
344 #define ARMul_FIRST 0
345 #define ARMul_TRANSFER 1
348 #define ARMul_INTERRUPT 4
353 #define ARMul_CP13_R0_FIQ 0x1
354 #define ARMul_CP13_R0_IRQ 0x2
355 #define ARMul_CP13_R8_PMUS 0x1
357 #define ARMul_CP14_R0_ENABLE 0x0001
358 #define ARMul_CP14_R0_CLKRST 0x0004
359 #define ARMul_CP14_R0_CCD 0x0008
360 #define ARMul_CP14_R0_INTEN0 0x0010
361 #define ARMul_CP14_R0_INTEN1 0x0020
362 #define ARMul_CP14_R0_INTEN2 0x0040
363 #define ARMul_CP14_R0_FLAG0 0x0100
364 #define ARMul_CP14_R0_FLAG1 0x0200
365 #define ARMul_CP14_R0_FLAG2 0x0400
366 #define ARMul_CP14_R10_MOE_IB 0x0004
367 #define ARMul_CP14_R10_MOE_DB 0x0008
368 #define ARMul_CP14_R10_MOE_BT 0x000c
369 #define ARMul_CP15_R1_ENDIAN 0x0080
370 #define ARMul_CP15_R1_ALIGN 0x0002
371 #define ARMul_CP15_R5_X 0x0400
372 #define ARMul_CP15_R5_ST_ALIGN 0x0001
373 #define ARMul_CP15_R5_IMPRE 0x0406
374 #define ARMul_CP15_R5_MMU_EXCPT 0x0400
375 #define ARMul_CP15_DBCON_M 0x0100
376 #define ARMul_CP15_DBCON_E1 0x000c
377 #define ARMul_CP15_DBCON_E0 0x0003
379 extern unsigned ARMul_CoProInit (ARMul_State
* state
);
380 extern void ARMul_CoProExit (ARMul_State
* state
);
381 extern void ARMul_CoProAttach (ARMul_State
* state
, unsigned number
,
382 ARMul_CPInits
* init
, ARMul_CPExits
* exit
,
383 ARMul_LDCs
* ldc
, ARMul_STCs
* stc
,
384 ARMul_MRCs
* mrc
, ARMul_MCRs
* mcr
,
386 ARMul_CPReads
* read
, ARMul_CPWrites
* write
);
387 extern void ARMul_CoProDetach (ARMul_State
* state
, unsigned number
);
388 extern void XScale_check_memacc (ARMul_State
* state
, ARMword
* address
,
390 extern void XScale_set_fsr_far (ARMul_State
* state
, ARMword fsr
, ARMword far
);
391 extern int XScale_debug_moe (ARMul_State
* state
, int moe
);
393 /***************************************************************************\
394 * Definitons of things in the host environment *
395 \***************************************************************************/
397 extern unsigned ARMul_OSInit (ARMul_State
* state
);
398 extern void ARMul_OSExit (ARMul_State
* state
);
399 extern unsigned ARMul_OSHandleSWI (ARMul_State
* state
, ARMword number
);
400 extern ARMword
ARMul_OSLastErrorP (ARMul_State
* state
);
402 extern ARMword
ARMul_Debug (ARMul_State
* state
, ARMword pc
, ARMword instr
);
403 extern unsigned ARMul_OSException (ARMul_State
* state
, ARMword vector
,
407 /***************************************************************************\
408 * Host-dependent stuff *
409 \***************************************************************************/
412 pascal void SpinCursor (short increment
); /* copied from CursorCtl.h */
413 # define HOURGLASS SpinCursor( 1 )
414 # define HOURGLASS_RATE 1023 /* 2^n - 1 */
417 extern void ARMul_UndefInstr (ARMul_State
*, ARMword
);
418 extern void ARMul_FixCPSR (ARMul_State
*, ARMword
, ARMword
);
419 extern void ARMul_FixSPSR (ARMul_State
*, ARMword
, ARMword
);
420 extern void ARMul_ConsolePrint (ARMul_State
*, const char *, ...);
421 extern void ARMul_SelectProcessor (ARMul_State
*, unsigned);