1 /* armsupp.c -- ARMulator support code: ARM6 Instruction Emulator.
2 Copyright (C) 1994 Advanced RISC Machines Ltd.
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
22 /***************************************************************************\
23 * Definitions for the support routines *
24 \***************************************************************************/
26 ARMword
ARMul_GetReg (ARMul_State
* state
, unsigned mode
, unsigned reg
);
27 void ARMul_SetReg (ARMul_State
* state
, unsigned mode
, unsigned reg
,
29 ARMword
ARMul_GetPC (ARMul_State
* state
);
30 ARMword
ARMul_GetNextPC (ARMul_State
* state
);
31 void ARMul_SetPC (ARMul_State
* state
, ARMword value
);
32 ARMword
ARMul_GetR15 (ARMul_State
* state
);
33 void ARMul_SetR15 (ARMul_State
* state
, ARMword value
);
35 ARMword
ARMul_GetCPSR (ARMul_State
* state
);
36 void ARMul_SetCPSR (ARMul_State
* state
, ARMword value
);
37 ARMword
ARMul_GetSPSR (ARMul_State
* state
, ARMword mode
);
38 void ARMul_SetSPSR (ARMul_State
* state
, ARMword mode
, ARMword value
);
40 void ARMul_CPSRAltered (ARMul_State
* state
);
41 void ARMul_R15Altered (ARMul_State
* state
);
43 ARMword
ARMul_SwitchMode (ARMul_State
* state
, ARMword oldmode
,
45 static ARMword
ModeToBank (ARMul_State
* state
, ARMword mode
);
47 unsigned ARMul_NthReg (ARMword instr
, unsigned number
);
49 void ARMul_NegZero (ARMul_State
* state
, ARMword result
);
50 void ARMul_AddCarry (ARMul_State
* state
, ARMword a
, ARMword b
,
52 void ARMul_AddOverflow (ARMul_State
* state
, ARMword a
, ARMword b
,
54 void ARMul_SubCarry (ARMul_State
* state
, ARMword a
, ARMword b
,
56 void ARMul_SubOverflow (ARMul_State
* state
, ARMword a
, ARMword b
,
59 void ARMul_LDC (ARMul_State
* state
, ARMword instr
, ARMword address
);
60 void ARMul_STC (ARMul_State
* state
, ARMword instr
, ARMword address
);
61 void ARMul_MCR (ARMul_State
* state
, ARMword instr
, ARMword source
);
62 ARMword
ARMul_MRC (ARMul_State
* state
, ARMword instr
);
63 void ARMul_CDP (ARMul_State
* state
, ARMword instr
);
64 unsigned IntPending (ARMul_State
* state
);
66 ARMword
ARMul_Align (ARMul_State
* state
, ARMword address
, ARMword data
);
68 void ARMul_ScheduleEvent (ARMul_State
* state
, unsigned long delay
,
70 void ARMul_EnvokeEvent (ARMul_State
* state
);
71 unsigned long ARMul_Time (ARMul_State
* state
);
72 static void EnvokeList (ARMul_State
* state
, unsigned long from
,
76 { /* An event list node */
77 unsigned (*func
) (); /* The function to call */
78 struct EventNode
*next
;
81 /***************************************************************************\
82 * This routine returns the value of a register from a mode. *
83 \***************************************************************************/
86 ARMul_GetReg (ARMul_State
* state
, unsigned mode
, unsigned reg
)
89 if (mode
!= state
->Mode
)
90 return (state
->RegBank
[ModeToBank (state
, (ARMword
) mode
)][reg
]);
92 return (state
->Reg
[reg
]);
95 /***************************************************************************\
96 * This routine sets the value of a register for a mode. *
97 \***************************************************************************/
100 ARMul_SetReg (ARMul_State
* state
, unsigned mode
, unsigned reg
, ARMword value
)
103 if (mode
!= state
->Mode
)
104 state
->RegBank
[ModeToBank (state
, (ARMword
) mode
)][reg
] = value
;
106 state
->Reg
[reg
] = value
;
109 /***************************************************************************\
110 * This routine returns the value of the PC, mode independently. *
111 \***************************************************************************/
114 ARMul_GetPC (ARMul_State
* state
)
116 if (state
->Mode
> SVC26MODE
)
117 return (state
->Reg
[15]);
122 /***************************************************************************\
123 * This routine returns the value of the PC, mode independently. *
124 \***************************************************************************/
127 ARMul_GetNextPC (ARMul_State
* state
)
129 if (state
->Mode
> SVC26MODE
)
130 return (state
->Reg
[15] + isize
);
132 return ((state
->Reg
[15] + isize
) & R15PCBITS
);
135 /***************************************************************************\
136 * This routine sets the value of the PC. *
137 \***************************************************************************/
140 ARMul_SetPC (ARMul_State
* state
, ARMword value
)
143 state
->Reg
[15] = value
& PCBITS
;
145 state
->Reg
[15] = R15CCINTMODE
| (value
& R15PCBITS
);
149 /***************************************************************************\
150 * This routine returns the value of register 15, mode independently. *
151 \***************************************************************************/
154 ARMul_GetR15 (ARMul_State
* state
)
156 if (state
->Mode
> SVC26MODE
)
157 return (state
->Reg
[15]);
159 return (R15PC
| ECC
| ER15INT
| EMODE
);
162 /***************************************************************************\
163 * This routine sets the value of Register 15. *
164 \***************************************************************************/
167 ARMul_SetR15 (ARMul_State
* state
, ARMword value
)
170 state
->Reg
[15] = value
& PCBITS
;
173 state
->Reg
[15] = value
;
174 ARMul_R15Altered (state
);
179 /***************************************************************************\
180 * This routine returns the value of the CPSR *
181 \***************************************************************************/
184 ARMul_GetCPSR (ARMul_State
* state
)
189 /***************************************************************************\
190 * This routine sets the value of the CPSR *
191 \***************************************************************************/
194 ARMul_SetCPSR (ARMul_State
* state
, ARMword value
)
197 SETPSR (state
->Cpsr
, value
);
198 ARMul_CPSRAltered (state
);
201 /***************************************************************************\
202 * This routine does all the nasty bits involved in a write to the CPSR, *
203 * including updating the register bank, given a MSR instruction. *
204 \***************************************************************************/
207 ARMul_FixCPSR (ARMul_State
* state
, ARMword instr
, ARMword rhs
)
210 if (state
->Bank
== USERBANK
)
211 { /* Only write flags in user mode */
214 SETCC (state
->Cpsr
, rhs
);
218 { /* Not a user mode */
219 if (BITS (16, 19) == 9)
220 SETPSR (state
->Cpsr
, rhs
);
222 SETINTMODE (state
->Cpsr
, rhs
);
224 SETCC (state
->Cpsr
, rhs
);
226 ARMul_CPSRAltered (state
);
229 /***************************************************************************\
230 * Get an SPSR from the specified mode *
231 \***************************************************************************/
234 ARMul_GetSPSR (ARMul_State
* state
, ARMword mode
)
236 ARMword bank
= ModeToBank (state
, mode
& MODEBITS
);
237 if (bank
== USERBANK
|| bank
== DUMMYBANK
)
240 return (state
->Spsr
[bank
]);
243 /***************************************************************************\
244 * This routine does a write to an SPSR *
245 \***************************************************************************/
248 ARMul_SetSPSR (ARMul_State
* state
, ARMword mode
, ARMword value
)
250 ARMword bank
= ModeToBank (state
, mode
& MODEBITS
);
251 if (bank
!= USERBANK
&& bank
!= DUMMYBANK
)
252 state
->Spsr
[bank
] = value
;
255 /***************************************************************************\
256 * This routine does a write to the current SPSR, given an MSR instruction *
257 \***************************************************************************/
260 ARMul_FixSPSR (ARMul_State
* state
, ARMword instr
, ARMword rhs
)
262 if (state
->Bank
!= USERBANK
&& state
->Bank
!= DUMMYBANK
)
264 if (BITS (16, 19) == 9)
265 SETPSR (state
->Spsr
[state
->Bank
], rhs
);
267 SETINTMODE (state
->Spsr
[state
->Bank
], rhs
);
269 SETCC (state
->Spsr
[state
->Bank
], rhs
);
273 /***************************************************************************\
274 * This routine updates the state of the emulator after the Cpsr has been *
275 * changed. Both the processor flags and register bank are updated. *
276 \***************************************************************************/
279 ARMul_CPSRAltered (ARMul_State
* state
)
283 if (state
->prog32Sig
== LOW
)
284 state
->Cpsr
&= (CCBITS
| INTBITS
| R15MODEBITS
);
285 oldmode
= state
->Mode
;
286 if (state
->Mode
!= (state
->Cpsr
& MODEBITS
))
289 ARMul_SwitchMode (state
, state
->Mode
, state
->Cpsr
& MODEBITS
);
290 state
->NtransSig
= (state
->Mode
& 3) ? HIGH
: LOW
;
293 ASSIGNINT (state
->Cpsr
& INTBITS
);
294 ASSIGNN ((state
->Cpsr
& NBIT
) != 0);
295 ASSIGNZ ((state
->Cpsr
& ZBIT
) != 0);
296 ASSIGNC ((state
->Cpsr
& CBIT
) != 0);
297 ASSIGNV ((state
->Cpsr
& VBIT
) != 0);
299 ASSIGNT ((state
->Cpsr
& TBIT
) != 0);
302 if (oldmode
> SVC26MODE
)
304 if (state
->Mode
<= SVC26MODE
)
306 state
->Emulate
= CHANGEMODE
;
307 state
->Reg
[15] = ECC
| ER15INT
| EMODE
| R15PC
;
312 if (state
->Mode
> SVC26MODE
)
314 state
->Emulate
= CHANGEMODE
;
315 state
->Reg
[15] = R15PC
;
318 state
->Reg
[15] = ECC
| ER15INT
| EMODE
| R15PC
;
323 /***************************************************************************\
324 * This routine updates the state of the emulator after register 15 has *
325 * been changed. Both the processor flags and register bank are updated. *
326 * This routine should only be called from a 26 bit mode. *
327 \***************************************************************************/
330 ARMul_R15Altered (ARMul_State
* state
)
332 if (state
->Mode
!= R15MODE
)
334 state
->Mode
= ARMul_SwitchMode (state
, state
->Mode
, R15MODE
);
335 state
->NtransSig
= (state
->Mode
& 3) ? HIGH
: LOW
;
337 if (state
->Mode
> SVC26MODE
)
338 state
->Emulate
= CHANGEMODE
;
339 ASSIGNR15INT (R15INT
);
340 ASSIGNN ((state
->Reg
[15] & NBIT
) != 0);
341 ASSIGNZ ((state
->Reg
[15] & ZBIT
) != 0);
342 ASSIGNC ((state
->Reg
[15] & CBIT
) != 0);
343 ASSIGNV ((state
->Reg
[15] & VBIT
) != 0);
346 /***************************************************************************\
347 * This routine controls the saving and restoring of registers across mode *
348 * changes. The regbank matrix is largely unused, only rows 13 and 14 are *
349 * used across all modes, 8 to 14 are used for FIQ, all others use the USER *
350 * column. It's easier this way. old and new parameter are modes numbers. *
351 * Notice the side effect of changing the Bank variable. *
352 \***************************************************************************/
355 ARMul_SwitchMode (ARMul_State
* state
, ARMword oldmode
, ARMword newmode
)
359 oldmode
= ModeToBank (state
, oldmode
);
360 state
->Bank
= ModeToBank (state
, newmode
);
361 if (oldmode
!= state
->Bank
)
362 { /* really need to do it */
364 { /* save away the old registers */
370 if (state
->Bank
== FIQBANK
)
371 for (i
= 8; i
< 13; i
++)
372 state
->RegBank
[USERBANK
][i
] = state
->Reg
[i
];
373 state
->RegBank
[oldmode
][13] = state
->Reg
[13];
374 state
->RegBank
[oldmode
][14] = state
->Reg
[14];
377 for (i
= 8; i
< 15; i
++)
378 state
->RegBank
[FIQBANK
][i
] = state
->Reg
[i
];
381 for (i
= 8; i
< 15; i
++)
382 state
->RegBank
[DUMMYBANK
][i
] = 0;
387 { /* restore the new registers */
393 if (oldmode
== FIQBANK
)
394 for (i
= 8; i
< 13; i
++)
395 state
->Reg
[i
] = state
->RegBank
[USERBANK
][i
];
396 state
->Reg
[13] = state
->RegBank
[state
->Bank
][13];
397 state
->Reg
[14] = state
->RegBank
[state
->Bank
][14];
400 for (i
= 8; i
< 15; i
++)
401 state
->Reg
[i
] = state
->RegBank
[FIQBANK
][i
];
404 for (i
= 8; i
< 15; i
++)
412 /***************************************************************************\
413 * Given a processor mode, this routine returns the register bank that *
414 * will be accessed in that mode. *
415 \***************************************************************************/
418 ModeToBank (ARMul_State
* state ATTRIBUTE_UNUSED
, ARMword mode
)
420 static ARMword bankofmode
[] = { USERBANK
, FIQBANK
, IRQBANK
, SVCBANK
,
421 DUMMYBANK
, DUMMYBANK
, DUMMYBANK
, DUMMYBANK
,
422 DUMMYBANK
, DUMMYBANK
, DUMMYBANK
, DUMMYBANK
,
423 DUMMYBANK
, DUMMYBANK
, DUMMYBANK
, DUMMYBANK
,
424 USERBANK
, FIQBANK
, IRQBANK
, SVCBANK
,
425 DUMMYBANK
, DUMMYBANK
, DUMMYBANK
, ABORTBANK
,
426 DUMMYBANK
, DUMMYBANK
, DUMMYBANK
, UNDEFBANK
429 if (mode
> UNDEF32MODE
)
432 return (bankofmode
[mode
]);
435 /***************************************************************************\
436 * Returns the register number of the nth register in a reg list. *
437 \***************************************************************************/
440 ARMul_NthReg (ARMword instr
, unsigned number
)
444 for (bit
= 0, upto
= 0; upto
<= number
; bit
++)
450 /***************************************************************************\
451 * Assigns the N and Z flags depending on the value of result *
452 \***************************************************************************/
455 ARMul_NegZero (ARMul_State
* state
, ARMword result
)
462 else if (result
== 0)
474 /* Compute whether an addition of A and B, giving RESULT, overflowed. */
476 AddOverflow (ARMword a
, ARMword b
, ARMword result
)
478 return ((NEG (a
) && NEG (b
) && POS (result
))
479 || (POS (a
) && POS (b
) && NEG (result
)));
482 /* Compute whether a subtraction of A and B, giving RESULT, overflowed. */
484 SubOverflow (ARMword a
, ARMword b
, ARMword result
)
486 return ((NEG (a
) && POS (b
) && POS (result
))
487 || (POS (a
) && NEG (b
) && NEG (result
)));
490 /***************************************************************************\
491 * Assigns the C flag after an addition of a and b to give result *
492 \***************************************************************************/
495 ARMul_AddCarry (ARMul_State
* state
, ARMword a
, ARMword b
, ARMword result
)
497 ASSIGNC ((NEG (a
) && NEG (b
)) ||
498 (NEG (a
) && POS (result
)) || (NEG (b
) && POS (result
)));
501 /***************************************************************************\
502 * Assigns the V flag after an addition of a and b to give result *
503 \***************************************************************************/
506 ARMul_AddOverflow (ARMul_State
* state
, ARMword a
, ARMword b
, ARMword result
)
508 ASSIGNV (AddOverflow (a
, b
, result
));
511 /***************************************************************************\
512 * Assigns the C flag after an subtraction of a and b to give result *
513 \***************************************************************************/
516 ARMul_SubCarry (ARMul_State
* state
, ARMword a
, ARMword b
, ARMword result
)
518 ASSIGNC ((NEG (a
) && POS (b
)) ||
519 (NEG (a
) && POS (result
)) || (POS (b
) && POS (result
)));
522 /***************************************************************************\
523 * Assigns the V flag after an subtraction of a and b to give result *
524 \***************************************************************************/
527 ARMul_SubOverflow (ARMul_State
* state
, ARMword a
, ARMword b
, ARMword result
)
529 ASSIGNV (SubOverflow (a
, b
, result
));
532 /***************************************************************************\
533 * This function does the work of generating the addresses used in an *
534 * LDC instruction. The code here is always post-indexed, it's up to the *
535 * caller to get the input address correct and to handle base register *
536 * modification. It also handles the Busy-Waiting. *
537 \***************************************************************************/
540 ARMul_LDC (ARMul_State
* state
, ARMword instr
, ARMword address
)
546 if (ADDREXCEPT (address
))
548 INTERNALABORT (address
);
550 cpab
= (state
->LDC
[CPNum
]) (state
, ARMul_FIRST
, instr
, 0);
551 while (cpab
== ARMul_BUSY
)
553 ARMul_Icycles (state
, 1, 0);
554 if (IntPending (state
))
556 cpab
= (state
->LDC
[CPNum
]) (state
, ARMul_INTERRUPT
, instr
, 0);
560 cpab
= (state
->LDC
[CPNum
]) (state
, ARMul_BUSY
, instr
, 0);
562 if (cpab
== ARMul_CANT
)
567 cpab
= (state
->LDC
[CPNum
]) (state
, ARMul_TRANSFER
, instr
, 0);
568 data
= ARMul_LoadWordN (state
, address
);
571 LSBase
= state
->Base
;
572 cpab
= (state
->LDC
[CPNum
]) (state
, ARMul_DATA
, instr
, data
);
573 while (cpab
== ARMul_INC
)
576 data
= ARMul_LoadWordN (state
, address
);
577 cpab
= (state
->LDC
[CPNum
]) (state
, ARMul_DATA
, instr
, data
);
579 if (state
->abortSig
|| state
->Aborted
)
585 /***************************************************************************\
586 * This function does the work of generating the addresses used in an *
587 * STC instruction. The code here is always post-indexed, it's up to the *
588 * caller to get the input address correct and to handle base register *
589 * modification. It also handles the Busy-Waiting. *
590 \***************************************************************************/
593 ARMul_STC (ARMul_State
* state
, ARMword instr
, ARMword address
)
599 if (ADDREXCEPT (address
) || VECTORACCESS (address
))
601 INTERNALABORT (address
);
603 cpab
= (state
->STC
[CPNum
]) (state
, ARMul_FIRST
, instr
, &data
);
604 while (cpab
== ARMul_BUSY
)
606 ARMul_Icycles (state
, 1, 0);
607 if (IntPending (state
))
609 cpab
= (state
->STC
[CPNum
]) (state
, ARMul_INTERRUPT
, instr
, 0);
613 cpab
= (state
->STC
[CPNum
]) (state
, ARMul_BUSY
, instr
, &data
);
615 if (cpab
== ARMul_CANT
)
621 if (ADDREXCEPT (address
) || VECTORACCESS (address
))
623 INTERNALABORT (address
);
628 LSBase
= state
->Base
;
629 cpab
= (state
->STC
[CPNum
]) (state
, ARMul_DATA
, instr
, &data
);
630 ARMul_StoreWordN (state
, address
, data
);
631 while (cpab
== ARMul_INC
)
634 cpab
= (state
->STC
[CPNum
]) (state
, ARMul_DATA
, instr
, &data
);
635 ARMul_StoreWordN (state
, address
, data
);
637 if (state
->abortSig
|| state
->Aborted
)
643 /***************************************************************************\
644 * This function does the Busy-Waiting for an MCR instruction. *
645 \***************************************************************************/
648 ARMul_MCR (ARMul_State
* state
, ARMword instr
, ARMword source
)
652 cpab
= (state
->MCR
[CPNum
]) (state
, ARMul_FIRST
, instr
, source
);
653 while (cpab
== ARMul_BUSY
)
655 ARMul_Icycles (state
, 1, 0);
656 if (IntPending (state
))
658 cpab
= (state
->MCR
[CPNum
]) (state
, ARMul_INTERRUPT
, instr
, 0);
662 cpab
= (state
->MCR
[CPNum
]) (state
, ARMul_BUSY
, instr
, source
);
664 if (cpab
== ARMul_CANT
)
665 ARMul_Abort (state
, ARMul_UndefinedInstrV
);
669 ARMul_Ccycles (state
, 1, 0);
673 /***************************************************************************\
674 * This function does the Busy-Waiting for an MRC instruction. *
675 \***************************************************************************/
678 ARMul_MRC (ARMul_State
* state
, ARMword instr
)
683 cpab
= (state
->MRC
[CPNum
]) (state
, ARMul_FIRST
, instr
, &result
);
684 while (cpab
== ARMul_BUSY
)
686 ARMul_Icycles (state
, 1, 0);
687 if (IntPending (state
))
689 cpab
= (state
->MRC
[CPNum
]) (state
, ARMul_INTERRUPT
, instr
, 0);
693 cpab
= (state
->MRC
[CPNum
]) (state
, ARMul_BUSY
, instr
, &result
);
695 if (cpab
== ARMul_CANT
)
697 ARMul_Abort (state
, ARMul_UndefinedInstrV
);
698 result
= ECC
; /* Parent will destroy the flags otherwise */
703 ARMul_Ccycles (state
, 1, 0);
704 ARMul_Icycles (state
, 1, 0);
709 /***************************************************************************\
710 * This function does the Busy-Waiting for an CDP instruction. *
711 \***************************************************************************/
714 ARMul_CDP (ARMul_State
* state
, ARMword instr
)
718 cpab
= (state
->CDP
[CPNum
]) (state
, ARMul_FIRST
, instr
);
719 while (cpab
== ARMul_BUSY
)
721 ARMul_Icycles (state
, 1, 0);
722 if (IntPending (state
))
724 cpab
= (state
->CDP
[CPNum
]) (state
, ARMul_INTERRUPT
, instr
);
728 cpab
= (state
->CDP
[CPNum
]) (state
, ARMul_BUSY
, instr
);
730 if (cpab
== ARMul_CANT
)
731 ARMul_Abort (state
, ARMul_UndefinedInstrV
);
736 /***************************************************************************\
737 * This function handles Undefined instructions, as CP isntruction *
738 \***************************************************************************/
741 ARMul_UndefInstr (ARMul_State
* state
, ARMword instr ATTRIBUTE_UNUSED
)
743 ARMul_Abort (state
, ARMul_UndefinedInstrV
);
746 /***************************************************************************\
747 * Return TRUE if an interrupt is pending, FALSE otherwise. *
748 \***************************************************************************/
751 IntPending (ARMul_State
* state
)
753 if (state
->Exception
)
754 { /* Any exceptions */
755 if (state
->NresetSig
== LOW
)
757 ARMul_Abort (state
, ARMul_ResetV
);
760 else if (!state
->NfiqSig
&& !FFLAG
)
762 ARMul_Abort (state
, ARMul_FIQV
);
765 else if (!state
->NirqSig
&& !IFLAG
)
767 ARMul_Abort (state
, ARMul_IRQV
);
774 /***************************************************************************\
775 * Align a word access to a non word boundary *
776 \***************************************************************************/
779 ARMul_Align (state
, address
, data
)
780 ARMul_State
* state ATTRIBUTE_UNUSED
;
784 /* This code assumes the address is really unaligned,
785 as a shift by 32 is undefined in C. */
787 address
= (address
& 3) << 3; /* get the word address */
788 return ((data
>> address
) | (data
<< (32 - address
))); /* rot right */
791 /***************************************************************************\
792 * This routine is used to call another routine after a certain number of *
793 * cycles have been executed. The first parameter is the number of cycles *
794 * delay before the function is called, the second argument is a pointer *
795 * to the function. A delay of zero doesn't work, just call the function. *
796 \***************************************************************************/
799 ARMul_ScheduleEvent (ARMul_State
* state
, unsigned long delay
,
803 struct EventNode
*event
;
805 if (state
->EventSet
++ == 0)
806 state
->Now
= ARMul_Time (state
);
807 when
= (state
->Now
+ delay
) % EVENTLISTSIZE
;
808 event
= (struct EventNode
*) malloc (sizeof (struct EventNode
));
810 event
->next
= *(state
->EventPtr
+ when
);
811 *(state
->EventPtr
+ when
) = event
;
814 /***************************************************************************\
815 * This routine is called at the beginning of every cycle, to envoke *
816 * scheduled events. *
817 \***************************************************************************/
820 ARMul_EnvokeEvent (ARMul_State
* state
)
822 static unsigned long then
;
825 state
->Now
= ARMul_Time (state
) % EVENTLISTSIZE
;
826 if (then
< state
->Now
) /* schedule events */
827 EnvokeList (state
, then
, state
->Now
);
828 else if (then
> state
->Now
)
829 { /* need to wrap around the list */
830 EnvokeList (state
, then
, EVENTLISTSIZE
- 1L);
831 EnvokeList (state
, 0L, state
->Now
);
836 EnvokeList (ARMul_State
* state
, unsigned long from
, unsigned long to
)
837 /* envokes all the entries in a range */
839 struct EventNode
*anevent
;
841 for (; from
<= to
; from
++)
843 anevent
= *(state
->EventPtr
+ from
);
846 (anevent
->func
) (state
);
848 anevent
= anevent
->next
;
850 *(state
->EventPtr
+ from
) = NULL
;
854 /***************************************************************************\
855 * This routine is returns the number of clock ticks since the last reset. *
856 \***************************************************************************/
859 ARMul_Time (ARMul_State
* state
)
861 return (state
->NumScycles
+ state
->NumNcycles
+
862 state
->NumIcycles
+ state
->NumCcycles
+ state
->NumFcycles
);