1 /* armsupp.c -- ARMulator support code: ARM6 Instruction Emulator.
2 Copyright (C) 1994 Advanced RISC Machines Ltd.
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
22 /***************************************************************************\
23 * Definitions for the support routines *
24 \***************************************************************************/
26 ARMword
ARMul_GetReg (ARMul_State
* state
, unsigned mode
, unsigned reg
);
27 void ARMul_SetReg (ARMul_State
* state
, unsigned mode
, unsigned reg
,
29 ARMword
ARMul_GetPC (ARMul_State
* state
);
30 ARMword
ARMul_GetNextPC (ARMul_State
* state
);
31 void ARMul_SetPC (ARMul_State
* state
, ARMword value
);
32 ARMword
ARMul_GetR15 (ARMul_State
* state
);
33 void ARMul_SetR15 (ARMul_State
* state
, ARMword value
);
35 ARMword
ARMul_GetCPSR (ARMul_State
* state
);
36 void ARMul_SetCPSR (ARMul_State
* state
, ARMword value
);
37 ARMword
ARMul_GetSPSR (ARMul_State
* state
, ARMword mode
);
38 void ARMul_SetSPSR (ARMul_State
* state
, ARMword mode
, ARMword value
);
40 void ARMul_CPSRAltered (ARMul_State
* state
);
41 void ARMul_R15Altered (ARMul_State
* state
);
43 ARMword
ARMul_SwitchMode (ARMul_State
* state
, ARMword oldmode
,
45 static ARMword
ModeToBank (ARMword mode
);
47 unsigned ARMul_NthReg (ARMword instr
, unsigned number
);
49 void ARMul_NegZero (ARMul_State
* state
, ARMword result
);
50 void ARMul_AddCarry (ARMul_State
* state
, ARMword a
, ARMword b
,
52 void ARMul_AddOverflow (ARMul_State
* state
, ARMword a
, ARMword b
,
54 void ARMul_SubCarry (ARMul_State
* state
, ARMword a
, ARMword b
,
56 void ARMul_SubOverflow (ARMul_State
* state
, ARMword a
, ARMword b
,
59 void ARMul_LDC (ARMul_State
* state
, ARMword instr
, ARMword address
);
60 void ARMul_STC (ARMul_State
* state
, ARMword instr
, ARMword address
);
61 void ARMul_MCR (ARMul_State
* state
, ARMword instr
, ARMword source
);
62 ARMword
ARMul_MRC (ARMul_State
* state
, ARMword instr
);
63 void ARMul_CDP (ARMul_State
* state
, ARMword instr
);
64 unsigned IntPending (ARMul_State
* state
);
66 ARMword
ARMul_Align (ARMul_State
* state
, ARMword address
, ARMword data
);
68 void ARMul_ScheduleEvent (ARMul_State
* state
, unsigned long delay
,
70 void ARMul_EnvokeEvent (ARMul_State
* state
);
71 unsigned long ARMul_Time (ARMul_State
* state
);
72 static void EnvokeList (ARMul_State
* state
, unsigned long from
,
76 { /* An event list node */
77 unsigned (*func
) (); /* The function to call */
78 struct EventNode
*next
;
81 /***************************************************************************\
82 * This routine returns the value of a register from a mode. *
83 \***************************************************************************/
86 ARMul_GetReg (ARMul_State
* state
, unsigned mode
, unsigned reg
)
89 if (mode
!= state
->Mode
)
90 return (state
->RegBank
[ModeToBank ((ARMword
) mode
)][reg
]);
92 return (state
->Reg
[reg
]);
95 /***************************************************************************\
96 * This routine sets the value of a register for a mode. *
97 \***************************************************************************/
100 ARMul_SetReg (ARMul_State
* state
, unsigned mode
, unsigned reg
, ARMword value
)
103 if (mode
!= state
->Mode
)
104 state
->RegBank
[ModeToBank ((ARMword
) mode
)][reg
] = value
;
106 state
->Reg
[reg
] = value
;
109 /***************************************************************************\
110 * This routine returns the value of the PC, mode independently. *
111 \***************************************************************************/
114 ARMul_GetPC (ARMul_State
* state
)
116 if (state
->Mode
> SVC26MODE
)
117 return (state
->Reg
[15]);
122 /***************************************************************************\
123 * This routine returns the value of the PC, mode independently. *
124 \***************************************************************************/
127 ARMul_GetNextPC (ARMul_State
* state
)
129 if (state
->Mode
> SVC26MODE
)
130 return (state
->Reg
[15] + isize
);
132 return ((state
->Reg
[15] + isize
) & R15PCBITS
);
135 /***************************************************************************\
136 * This routine sets the value of the PC. *
137 \***************************************************************************/
140 ARMul_SetPC (ARMul_State
* state
, ARMword value
)
143 state
->Reg
[15] = value
& PCBITS
;
145 state
->Reg
[15] = R15CCINTMODE
| (value
& R15PCBITS
);
149 /***************************************************************************\
150 * This routine returns the value of register 15, mode independently. *
151 \***************************************************************************/
154 ARMul_GetR15 (ARMul_State
* state
)
156 if (state
->Mode
> SVC26MODE
)
157 return (state
->Reg
[15]);
159 return (R15PC
| ECC
| ER15INT
| EMODE
);
162 /***************************************************************************\
163 * This routine sets the value of Register 15. *
164 \***************************************************************************/
167 ARMul_SetR15 (ARMul_State
* state
, ARMword value
)
170 state
->Reg
[15] = value
& PCBITS
;
173 state
->Reg
[15] = value
;
174 ARMul_R15Altered (state
);
179 /***************************************************************************\
180 * This routine returns the value of the CPSR *
181 \***************************************************************************/
184 ARMul_GetCPSR (ARMul_State
* state
)
186 return (CPSR
| state
->Cpsr
);
189 /***************************************************************************\
190 * This routine sets the value of the CPSR *
191 \***************************************************************************/
194 ARMul_SetCPSR (ARMul_State
* state
, ARMword value
)
197 ARMul_CPSRAltered (state
);
200 /***************************************************************************\
201 * This routine does all the nasty bits involved in a write to the CPSR, *
202 * including updating the register bank, given a MSR instruction. *
203 \***************************************************************************/
206 ARMul_FixCPSR (ARMul_State
* state
, ARMword instr
, ARMword rhs
)
208 state
->Cpsr
= ARMul_GetCPSR (state
);
209 if (state
->Bank
!= USERBANK
)
210 { /* In user mode, only write flags */
212 SETPSR_C (state
->Cpsr
, rhs
);
214 SETPSR_X (state
->Cpsr
, rhs
);
216 SETPSR_S (state
->Cpsr
, rhs
);
219 SETPSR_F (state
->Cpsr
, rhs
);
220 ARMul_CPSRAltered (state
);
223 /***************************************************************************\
224 * Get an SPSR from the specified mode *
225 \***************************************************************************/
228 ARMul_GetSPSR (ARMul_State
* state
, ARMword mode
)
230 ARMword bank
= ModeToBank (mode
& MODEBITS
);
232 if (! BANK_CAN_ACCESS_SPSR (bank
))
233 return ARMul_GetCPSR (state
);
235 return state
->Spsr
[bank
];
238 /***************************************************************************\
239 * This routine does a write to an SPSR *
240 \***************************************************************************/
243 ARMul_SetSPSR (ARMul_State
* state
, ARMword mode
, ARMword value
)
245 ARMword bank
= ModeToBank (mode
& MODEBITS
);
247 if (BANK_CAN_ACCESS_SPSR (bank
))
248 state
->Spsr
[bank
] = value
;
251 /***************************************************************************\
252 * This routine does a write to the current SPSR, given an MSR instruction *
253 \***************************************************************************/
256 ARMul_FixSPSR (ARMul_State
* state
, ARMword instr
, ARMword rhs
)
258 if (BANK_CAN_ACCESS_SPSR (state
->Bank
))
261 SETPSR_C (state
->Spsr
[state
->Bank
], rhs
);
263 SETPSR_X (state
->Spsr
[state
->Bank
], rhs
);
265 SETPSR_S (state
->Spsr
[state
->Bank
], rhs
);
267 SETPSR_F (state
->Spsr
[state
->Bank
], rhs
);
271 /***************************************************************************\
272 * This routine updates the state of the emulator after the Cpsr has been *
273 * changed. Both the processor flags and register bank are updated. *
274 \***************************************************************************/
277 ARMul_CPSRAltered (ARMul_State
* state
)
281 if (state
->prog32Sig
== LOW
)
282 state
->Cpsr
&= (CCBITS
| INTBITS
| R15MODEBITS
);
284 oldmode
= state
->Mode
;
286 if (state
->Mode
!= (state
->Cpsr
& MODEBITS
))
289 ARMul_SwitchMode (state
, state
->Mode
, state
->Cpsr
& MODEBITS
);
291 state
->NtransSig
= (state
->Mode
& 3) ? HIGH
: LOW
;
293 state
->Cpsr
&= ~MODEBITS
;
295 ASSIGNINT (state
->Cpsr
& INTBITS
);
296 state
->Cpsr
&= ~INTBITS
;
297 ASSIGNN ((state
->Cpsr
& NBIT
) != 0);
298 state
->Cpsr
&= ~NBIT
;
299 ASSIGNZ ((state
->Cpsr
& ZBIT
) != 0);
300 state
->Cpsr
&= ~ZBIT
;
301 ASSIGNC ((state
->Cpsr
& CBIT
) != 0);
302 state
->Cpsr
&= ~CBIT
;
303 ASSIGNV ((state
->Cpsr
& VBIT
) != 0);
304 state
->Cpsr
&= ~VBIT
;
305 ASSIGNS ((state
->Cpsr
& SBIT
) != 0);
306 state
->Cpsr
&= ~SBIT
;
308 ASSIGNT ((state
->Cpsr
& TBIT
) != 0);
309 state
->Cpsr
&= ~TBIT
;
312 if (oldmode
> SVC26MODE
)
314 if (state
->Mode
<= SVC26MODE
)
316 state
->Emulate
= CHANGEMODE
;
317 state
->Reg
[15] = ECC
| ER15INT
| EMODE
| R15PC
;
322 if (state
->Mode
> SVC26MODE
)
324 state
->Emulate
= CHANGEMODE
;
325 state
->Reg
[15] = R15PC
;
328 state
->Reg
[15] = ECC
| ER15INT
| EMODE
| R15PC
;
332 /***************************************************************************\
333 * This routine updates the state of the emulator after register 15 has *
334 * been changed. Both the processor flags and register bank are updated. *
335 * This routine should only be called from a 26 bit mode. *
336 \***************************************************************************/
339 ARMul_R15Altered (ARMul_State
* state
)
341 if (state
->Mode
!= R15MODE
)
343 state
->Mode
= ARMul_SwitchMode (state
, state
->Mode
, R15MODE
);
344 state
->NtransSig
= (state
->Mode
& 3) ? HIGH
: LOW
;
346 if (state
->Mode
> SVC26MODE
)
347 state
->Emulate
= CHANGEMODE
;
348 ASSIGNR15INT (R15INT
);
349 ASSIGNN ((state
->Reg
[15] & NBIT
) != 0);
350 ASSIGNZ ((state
->Reg
[15] & ZBIT
) != 0);
351 ASSIGNC ((state
->Reg
[15] & CBIT
) != 0);
352 ASSIGNV ((state
->Reg
[15] & VBIT
) != 0);
355 /***************************************************************************\
356 * This routine controls the saving and restoring of registers across mode *
357 * changes. The regbank matrix is largely unused, only rows 13 and 14 are *
358 * used across all modes, 8 to 14 are used for FIQ, all others use the USER *
359 * column. It's easier this way. old and new parameter are modes numbers. *
360 * Notice the side effect of changing the Bank variable. *
361 \***************************************************************************/
364 ARMul_SwitchMode (ARMul_State
* state
, ARMword oldmode
, ARMword newmode
)
370 oldbank
= ModeToBank (oldmode
);
371 newbank
= state
->Bank
= ModeToBank (newmode
);
373 if (oldbank
!= newbank
)
374 { /* really need to do it */
376 { /* save away the old registers */
382 if (newbank
== FIQBANK
)
383 for (i
= 8; i
< 13; i
++)
384 state
->RegBank
[USERBANK
][i
] = state
->Reg
[i
];
385 state
->RegBank
[oldbank
][13] = state
->Reg
[13];
386 state
->RegBank
[oldbank
][14] = state
->Reg
[14];
389 for (i
= 8; i
< 15; i
++)
390 state
->RegBank
[FIQBANK
][i
] = state
->Reg
[i
];
393 for (i
= 8; i
< 15; i
++)
394 state
->RegBank
[DUMMYBANK
][i
] = 0;
401 { /* restore the new registers */
407 if (oldbank
== FIQBANK
)
408 for (i
= 8; i
< 13; i
++)
409 state
->Reg
[i
] = state
->RegBank
[USERBANK
][i
];
410 state
->Reg
[13] = state
->RegBank
[newbank
][13];
411 state
->Reg
[14] = state
->RegBank
[newbank
][14];
414 for (i
= 8; i
< 15; i
++)
415 state
->Reg
[i
] = state
->RegBank
[FIQBANK
][i
];
418 for (i
= 8; i
< 15; i
++)
429 /***************************************************************************\
430 * Given a processor mode, this routine returns the register bank that *
431 * will be accessed in that mode. *
432 \***************************************************************************/
435 ModeToBank (ARMword mode
)
437 static ARMword bankofmode
[] =
439 USERBANK
, FIQBANK
, IRQBANK
, SVCBANK
,
440 DUMMYBANK
, DUMMYBANK
, DUMMYBANK
, DUMMYBANK
,
441 DUMMYBANK
, DUMMYBANK
, DUMMYBANK
, DUMMYBANK
,
442 DUMMYBANK
, DUMMYBANK
, DUMMYBANK
, DUMMYBANK
,
443 USERBANK
, FIQBANK
, IRQBANK
, SVCBANK
,
444 DUMMYBANK
, DUMMYBANK
, DUMMYBANK
, ABORTBANK
,
445 DUMMYBANK
, DUMMYBANK
, DUMMYBANK
, UNDEFBANK
,
446 DUMMYBANK
, DUMMYBANK
, DUMMYBANK
, SYSTEMBANK
449 if (mode
>= (sizeof (bankofmode
) / sizeof (bankofmode
[0])))
452 return bankofmode
[mode
];
455 /***************************************************************************\
456 * Returns the register number of the nth register in a reg list. *
457 \***************************************************************************/
460 ARMul_NthReg (ARMword instr
, unsigned number
)
464 for (bit
= 0, upto
= 0; upto
<= number
; bit
++)
470 /***************************************************************************\
471 * Assigns the N and Z flags depending on the value of result *
472 \***************************************************************************/
475 ARMul_NegZero (ARMul_State
* state
, ARMword result
)
482 else if (result
== 0)
494 /* Compute whether an addition of A and B, giving RESULT, overflowed. */
496 AddOverflow (ARMword a
, ARMword b
, ARMword result
)
498 return ((NEG (a
) && NEG (b
) && POS (result
))
499 || (POS (a
) && POS (b
) && NEG (result
)));
502 /* Compute whether a subtraction of A and B, giving RESULT, overflowed. */
504 SubOverflow (ARMword a
, ARMword b
, ARMword result
)
506 return ((NEG (a
) && POS (b
) && POS (result
))
507 || (POS (a
) && NEG (b
) && NEG (result
)));
510 /***************************************************************************\
511 * Assigns the C flag after an addition of a and b to give result *
512 \***************************************************************************/
515 ARMul_AddCarry (ARMul_State
* state
, ARMword a
, ARMword b
, ARMword result
)
517 ASSIGNC ((NEG (a
) && NEG (b
)) ||
518 (NEG (a
) && POS (result
)) || (NEG (b
) && POS (result
)));
521 /***************************************************************************\
522 * Assigns the V flag after an addition of a and b to give result *
523 \***************************************************************************/
526 ARMul_AddOverflow (ARMul_State
* state
, ARMword a
, ARMword b
, ARMword result
)
528 ASSIGNV (AddOverflow (a
, b
, result
));
531 /***************************************************************************\
532 * Assigns the C flag after an subtraction of a and b to give result *
533 \***************************************************************************/
536 ARMul_SubCarry (ARMul_State
* state
, ARMword a
, ARMword b
, ARMword result
)
538 ASSIGNC ((NEG (a
) && POS (b
)) ||
539 (NEG (a
) && POS (result
)) || (POS (b
) && POS (result
)));
542 /***************************************************************************\
543 * Assigns the V flag after an subtraction of a and b to give result *
544 \***************************************************************************/
547 ARMul_SubOverflow (ARMul_State
* state
, ARMword a
, ARMword b
, ARMword result
)
549 ASSIGNV (SubOverflow (a
, b
, result
));
552 /***************************************************************************\
553 * This function does the work of generating the addresses used in an *
554 * LDC instruction. The code here is always post-indexed, it's up to the *
555 * caller to get the input address correct and to handle base register *
556 * modification. It also handles the Busy-Waiting. *
557 \***************************************************************************/
560 ARMul_LDC (ARMul_State
* state
, ARMword instr
, ARMword address
)
566 if (ADDREXCEPT (address
))
568 INTERNALABORT (address
);
570 cpab
= (state
->LDC
[CPNum
]) (state
, ARMul_FIRST
, instr
, 0);
571 while (cpab
== ARMul_BUSY
)
573 ARMul_Icycles (state
, 1, 0);
574 if (IntPending (state
))
576 cpab
= (state
->LDC
[CPNum
]) (state
, ARMul_INTERRUPT
, instr
, 0);
580 cpab
= (state
->LDC
[CPNum
]) (state
, ARMul_BUSY
, instr
, 0);
582 if (cpab
== ARMul_CANT
)
587 cpab
= (state
->LDC
[CPNum
]) (state
, ARMul_TRANSFER
, instr
, 0);
588 data
= ARMul_LoadWordN (state
, address
);
591 LSBase
= state
->Base
;
592 cpab
= (state
->LDC
[CPNum
]) (state
, ARMul_DATA
, instr
, data
);
593 while (cpab
== ARMul_INC
)
596 data
= ARMul_LoadWordN (state
, address
);
597 cpab
= (state
->LDC
[CPNum
]) (state
, ARMul_DATA
, instr
, data
);
599 if (state
->abortSig
|| state
->Aborted
)
605 /***************************************************************************\
606 * This function does the work of generating the addresses used in an *
607 * STC instruction. The code here is always post-indexed, it's up to the *
608 * caller to get the input address correct and to handle base register *
609 * modification. It also handles the Busy-Waiting. *
610 \***************************************************************************/
613 ARMul_STC (ARMul_State
* state
, ARMword instr
, ARMword address
)
619 if (ADDREXCEPT (address
) || VECTORACCESS (address
))
621 INTERNALABORT (address
);
623 cpab
= (state
->STC
[CPNum
]) (state
, ARMul_FIRST
, instr
, &data
);
624 while (cpab
== ARMul_BUSY
)
626 ARMul_Icycles (state
, 1, 0);
627 if (IntPending (state
))
629 cpab
= (state
->STC
[CPNum
]) (state
, ARMul_INTERRUPT
, instr
, 0);
633 cpab
= (state
->STC
[CPNum
]) (state
, ARMul_BUSY
, instr
, &data
);
635 if (cpab
== ARMul_CANT
)
641 if (ADDREXCEPT (address
) || VECTORACCESS (address
))
643 INTERNALABORT (address
);
648 LSBase
= state
->Base
;
649 cpab
= (state
->STC
[CPNum
]) (state
, ARMul_DATA
, instr
, &data
);
650 ARMul_StoreWordN (state
, address
, data
);
651 while (cpab
== ARMul_INC
)
654 cpab
= (state
->STC
[CPNum
]) (state
, ARMul_DATA
, instr
, &data
);
655 ARMul_StoreWordN (state
, address
, data
);
657 if (state
->abortSig
|| state
->Aborted
)
663 /***************************************************************************\
664 * This function does the Busy-Waiting for an MCR instruction. *
665 \***************************************************************************/
668 ARMul_MCR (ARMul_State
* state
, ARMword instr
, ARMword source
)
672 cpab
= (state
->MCR
[CPNum
]) (state
, ARMul_FIRST
, instr
, source
);
674 while (cpab
== ARMul_BUSY
)
676 ARMul_Icycles (state
, 1, 0);
678 if (IntPending (state
))
680 cpab
= (state
->MCR
[CPNum
]) (state
, ARMul_INTERRUPT
, instr
, 0);
684 cpab
= (state
->MCR
[CPNum
]) (state
, ARMul_BUSY
, instr
, source
);
687 if (cpab
== ARMul_CANT
)
688 ARMul_Abort (state
, ARMul_UndefinedInstrV
);
692 ARMul_Ccycles (state
, 1, 0);
696 /***************************************************************************\
697 * This function does the Busy-Waiting for an MRC instruction. *
698 \***************************************************************************/
701 ARMul_MRC (ARMul_State
* state
, ARMword instr
)
706 cpab
= (state
->MRC
[CPNum
]) (state
, ARMul_FIRST
, instr
, &result
);
707 while (cpab
== ARMul_BUSY
)
709 ARMul_Icycles (state
, 1, 0);
710 if (IntPending (state
))
712 cpab
= (state
->MRC
[CPNum
]) (state
, ARMul_INTERRUPT
, instr
, 0);
716 cpab
= (state
->MRC
[CPNum
]) (state
, ARMul_BUSY
, instr
, &result
);
718 if (cpab
== ARMul_CANT
)
720 ARMul_Abort (state
, ARMul_UndefinedInstrV
);
721 result
= ECC
; /* Parent will destroy the flags otherwise */
726 ARMul_Ccycles (state
, 1, 0);
727 ARMul_Icycles (state
, 1, 0);
732 /***************************************************************************\
733 * This function does the Busy-Waiting for an CDP instruction. *
734 \***************************************************************************/
737 ARMul_CDP (ARMul_State
* state
, ARMword instr
)
741 cpab
= (state
->CDP
[CPNum
]) (state
, ARMul_FIRST
, instr
);
742 while (cpab
== ARMul_BUSY
)
744 ARMul_Icycles (state
, 1, 0);
745 if (IntPending (state
))
747 cpab
= (state
->CDP
[CPNum
]) (state
, ARMul_INTERRUPT
, instr
);
751 cpab
= (state
->CDP
[CPNum
]) (state
, ARMul_BUSY
, instr
);
753 if (cpab
== ARMul_CANT
)
754 ARMul_Abort (state
, ARMul_UndefinedInstrV
);
759 /***************************************************************************\
760 * This function handles Undefined instructions, as CP isntruction *
761 \***************************************************************************/
764 ARMul_UndefInstr (ARMul_State
* state
, ARMword instr ATTRIBUTE_UNUSED
)
766 ARMul_Abort (state
, ARMul_UndefinedInstrV
);
769 /***************************************************************************\
770 * Return TRUE if an interrupt is pending, FALSE otherwise. *
771 \***************************************************************************/
774 IntPending (ARMul_State
* state
)
776 if (state
->Exception
)
777 { /* Any exceptions */
778 if (state
->NresetSig
== LOW
)
780 ARMul_Abort (state
, ARMul_ResetV
);
783 else if (!state
->NfiqSig
&& !FFLAG
)
785 ARMul_Abort (state
, ARMul_FIQV
);
788 else if (!state
->NirqSig
&& !IFLAG
)
790 ARMul_Abort (state
, ARMul_IRQV
);
797 /***************************************************************************\
798 * Align a word access to a non word boundary *
799 \***************************************************************************/
802 ARMul_Align (state
, address
, data
)
803 ARMul_State
* state ATTRIBUTE_UNUSED
;
807 /* This code assumes the address is really unaligned,
808 as a shift by 32 is undefined in C. */
810 address
= (address
& 3) << 3; /* get the word address */
811 return ((data
>> address
) | (data
<< (32 - address
))); /* rot right */
814 /***************************************************************************\
815 * This routine is used to call another routine after a certain number of *
816 * cycles have been executed. The first parameter is the number of cycles *
817 * delay before the function is called, the second argument is a pointer *
818 * to the function. A delay of zero doesn't work, just call the function. *
819 \***************************************************************************/
822 ARMul_ScheduleEvent (ARMul_State
* state
, unsigned long delay
,
826 struct EventNode
*event
;
828 if (state
->EventSet
++ == 0)
829 state
->Now
= ARMul_Time (state
);
830 when
= (state
->Now
+ delay
) % EVENTLISTSIZE
;
831 event
= (struct EventNode
*) malloc (sizeof (struct EventNode
));
833 event
->next
= *(state
->EventPtr
+ when
);
834 *(state
->EventPtr
+ when
) = event
;
837 /***************************************************************************\
838 * This routine is called at the beginning of every cycle, to envoke *
839 * scheduled events. *
840 \***************************************************************************/
843 ARMul_EnvokeEvent (ARMul_State
* state
)
845 static unsigned long then
;
848 state
->Now
= ARMul_Time (state
) % EVENTLISTSIZE
;
849 if (then
< state
->Now
) /* schedule events */
850 EnvokeList (state
, then
, state
->Now
);
851 else if (then
> state
->Now
)
852 { /* need to wrap around the list */
853 EnvokeList (state
, then
, EVENTLISTSIZE
- 1L);
854 EnvokeList (state
, 0L, state
->Now
);
859 EnvokeList (ARMul_State
* state
, unsigned long from
, unsigned long to
)
860 /* envokes all the entries in a range */
862 struct EventNode
*anevent
;
864 for (; from
<= to
; from
++)
866 anevent
= *(state
->EventPtr
+ from
);
869 (anevent
->func
) (state
);
871 anevent
= anevent
->next
;
873 *(state
->EventPtr
+ from
) = NULL
;
877 /***************************************************************************\
878 * This routine is returns the number of clock ticks since the last reset. *
879 \***************************************************************************/
882 ARMul_Time (ARMul_State
* state
)
884 return (state
->NumScycles
+ state
->NumNcycles
+
885 state
->NumIcycles
+ state
->NumCcycles
+ state
->NumFcycles
);