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29 #ifndef __BASE_CPU_HH__
30 #define __BASE_CPU_HH__
35 #include "sim_object.hh"
37 #include "isa_traits.hh" // for Addr
46 class BaseCPU : public SimObject
52 uint8_t interrupts[NumInterruptLevels];
56 virtual void post_interrupt(int int_num, int index);
57 virtual void clear_interrupt(int int_num, int index);
58 virtual void clear_interrupts();
60 bool check_interrupt(int int_num) const {
61 if (int_num > NumInterruptLevels)
62 panic("int_num out of bounds\n");
64 return interrupts[int_num] != 0;
67 bool check_interrupts() const { return intstatus != 0; }
68 uint64_t intr_status() const { return intstatus; }
70 Tick getFreq() const { return frequency; }
74 std::vector<ExecContext *> contexts;
77 virtual void execCtxStatusChg() {}
82 BaseCPU(const std::string &_name, int _number_of_threads,
83 Counter max_insts_any_thread, Counter max_insts_all_threads,
87 BaseCPU(const std::string &_name, int _number_of_threads,
88 Counter max_insts_any_thread = 0,
89 Counter max_insts_all_threads = 0);
94 virtual void regStats();
96 /// Number of threads we're actually simulating (<= SMT_MAX_THREADS).
97 /// This is a constant for the duration of the simulation.
98 int number_of_threads;
100 /// Vector of per-thread instruction-based event queues. Used for
101 /// scheduling events based on number of instructions committed by
102 /// a particular thread.
103 EventQueue **comInsnEventQueue;
109 virtual bool filterThisInstructionPrefetch(int thread_number,
110 short asid, Addr prefetchTarget) const { return true; }
112 /// Return pointer to CPU's branch predictor (NULL if none).
113 virtual BranchPred *getBranchPred() { return NULL; };
116 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list
119 static int numSimulatedCPUs() { return cpuList.size(); }
122 #endif // __BASE_CPU_HH__