sim/bfin/TODO

   1 need to review ASTAT write behavior
   2
   3 how to model RETE and IVG0 bit in IPEND ...
   4
   5 model the loop buffer ?  this means no ifetches because they're cached.
   6 see page 4-26 in Blackfin PRM under hardware loops.
   7
   8 handle DSPID at 0xffe05000
   9
  10 CEC should handle multiple exceptions at same address.  would need
  11 exception processing to be delayed ?  at least needs a stack for
  12 the CEC to pop things off.
  13
  14 R0 = [SP++]; gets traced as R0 = [P6++];
  15
  16 merge dv-bfin_evt with dv-bfin_cec since the EVT regs are part of the CEC
  17
  18 fix single stepping over debug assert instructions in hardware
  19
  20 exception in IVG5 causes double fault ?
  21
  22 add a "file" option to the async banks to back it
  23
  24 tests:
  25         - check AN bits with Dreg subtraction
  26                 R0 = R1 - R2;
  27         - check astat bits with vector add/sub +|+
  28         - check acc with VIT_MAX and similiar insns