1 /* Blackfin External Bus Interface Unit (EBIU) Asynchronous Memory Controller
4 Copyright (C) 2010-2018 Free Software Foundation, Inc.
5 Contributed by Analog Devices, Inc.
7 This file is part of simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "dv-bfin_ebiu_amc.h"
32 bu32 bank_base
, bank_size
;
33 unsigned (*io_write
) (struct hw
*, const void *, int, address_word
,
34 unsigned, struct bfin_ebiu_amc
*, bu32
, bu32
);
35 unsigned (*io_read
) (struct hw
*, void *, int, address_word
, unsigned,
36 struct bfin_ebiu_amc
*, bu32
, void *, bu16
*, bu32
*);
39 /* Order after here is important -- matches hardware MMR layout. */
40 bu16
BFIN_MMR_16(amgctl
);
43 bu32 ambctl0
, ambctl1
;
45 bu16
BFIN_MMR_16(mode
);
46 bu16
BFIN_MMR_16(fctl
);
49 bu32 ambctl0
, ambctl1
;
52 bu32 ambctl0
, ambctl1
;
53 bu32 mbsctl
, arbstat
, mode
, fctl
;
57 #define mmr_base() offsetof(struct bfin_ebiu_amc, amgctl)
58 #define mmr_offset(mmr) (offsetof(struct bfin_ebiu_amc, mmr) - mmr_base())
59 #define mmr_idx(mmr) (mmr_offset (mmr) / 4)
61 static const char * const bf50x_mmr_names
[] =
63 "EBIU_AMGCTL", "EBIU_AMBCTL0", "EBIU_AMBCTL1",
64 [mmr_idx (bf50x
.mode
)] = "EBIU_MODE", "EBIU_FCTL",
66 static const char * const bf53x_mmr_names
[] =
68 "EBIU_AMGCTL", "EBIU_AMBCTL0", "EBIU_AMBCTL1",
70 static const char * const bf54x_mmr_names
[] =
72 "EBIU_AMGCTL", "EBIU_AMBCTL0", "EBIU_AMBCTL1",
73 "EBIU_MSBCTL", "EBIU_ARBSTAT", "EBIU_MODE", "EBIU_FCTL",
75 static const char * const *mmr_names
;
76 #define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>")
79 bfin_ebiu_amc_write_amgctl (struct hw
*me
, struct bfin_ebiu_amc
*amc
,
82 bu32 amben_old
, amben
, addr
, i
;
84 amben_old
= min ((amc
->amgctl
>> 1) & 0x7, 4);
85 amben
= min ((amgctl
>> 1) & 0x7, 4);
87 HW_TRACE ((me
, "reattaching banks: AMGCTL 0x%04x[%u] -> 0x%04x[%u]",
88 amc
->amgctl
, amben_old
, amgctl
, amben
));
90 for (i
= 0; i
< 4; ++i
)
92 addr
= amc
->bank_base
+ i
* amc
->bank_size
;
96 HW_TRACE ((me
, "detaching bank %u (%#x base)", i
, addr
));
97 sim_core_detach (hw_system (me
), NULL
, 0, 0, addr
);
102 struct hw
*slave
= amc
->slaves
[i
];
104 HW_TRACE ((me
, "attaching bank %u (%#x base) to %s", i
, addr
,
105 slave
? hw_path (slave
) : "<floating pins>"));
107 sim_core_attach (hw_system (me
), NULL
, 0, access_read_write_exec
,
108 0, addr
, amc
->bank_size
, 0, slave
, NULL
);
112 amc
->amgctl
= amgctl
;
116 bf50x_ebiu_amc_io_write_buffer (struct hw
*me
, const void *source
, int space
,
117 address_word addr
, unsigned nr_bytes
,
118 struct bfin_ebiu_amc
*amc
, bu32 mmr_off
,
123 case mmr_offset(amgctl
):
124 if (!dv_bfin_mmr_require_16 (me
, addr
, nr_bytes
, true))
126 bfin_ebiu_amc_write_amgctl (me
, amc
, value
);
128 case mmr_offset(bf50x
.ambctl0
):
129 amc
->bf50x
.ambctl0
= value
;
131 case mmr_offset(bf50x
.ambctl1
):
132 amc
->bf50x
.ambctl1
= value
;
134 case mmr_offset(bf50x
.mode
):
135 /* XXX: implement this. */
136 if (!dv_bfin_mmr_require_16 (me
, addr
, nr_bytes
, true))
139 case mmr_offset(bf50x
.fctl
):
140 /* XXX: implement this. */
141 if (!dv_bfin_mmr_require_16 (me
, addr
, nr_bytes
, true))
145 dv_bfin_mmr_invalid (me
, addr
, nr_bytes
, true);
153 bf53x_ebiu_amc_io_write_buffer (struct hw
*me
, const void *source
, int space
,
154 address_word addr
, unsigned nr_bytes
,
155 struct bfin_ebiu_amc
*amc
, bu32 mmr_off
,
160 case mmr_offset(amgctl
):
161 if (!dv_bfin_mmr_require_16 (me
, addr
, nr_bytes
, true))
163 bfin_ebiu_amc_write_amgctl (me
, amc
, value
);
165 case mmr_offset(bf53x
.ambctl0
):
166 amc
->bf53x
.ambctl0
= value
;
168 case mmr_offset(bf53x
.ambctl1
):
169 amc
->bf53x
.ambctl1
= value
;
172 dv_bfin_mmr_invalid (me
, addr
, nr_bytes
, true);
180 bf54x_ebiu_amc_io_write_buffer (struct hw
*me
, const void *source
, int space
,
181 address_word addr
, unsigned nr_bytes
,
182 struct bfin_ebiu_amc
*amc
, bu32 mmr_off
,
187 case mmr_offset(amgctl
):
188 if (!dv_bfin_mmr_require_16 (me
, addr
, nr_bytes
, true))
190 bfin_ebiu_amc_write_amgctl (me
, amc
, value
);
192 case mmr_offset(bf54x
.ambctl0
):
193 amc
->bf54x
.ambctl0
= value
;
195 case mmr_offset(bf54x
.ambctl1
):
196 amc
->bf54x
.ambctl1
= value
;
198 case mmr_offset(bf54x
.mbsctl
):
199 /* XXX: implement this. */
201 case mmr_offset(bf54x
.arbstat
):
202 /* XXX: implement this. */
204 case mmr_offset(bf54x
.mode
):
205 /* XXX: implement this. */
207 case mmr_offset(bf54x
.fctl
):
208 /* XXX: implement this. */
211 dv_bfin_mmr_invalid (me
, addr
, nr_bytes
, true);
219 bfin_ebiu_amc_io_write_buffer (struct hw
*me
, const void *source
, int space
,
220 address_word addr
, unsigned nr_bytes
)
222 struct bfin_ebiu_amc
*amc
= hw_data (me
);
226 /* Invalid access mode is higher priority than missing register. */
227 if (!dv_bfin_mmr_require_16_32 (me
, addr
, nr_bytes
, true))
230 value
= dv_load_4 (source
);
231 mmr_off
= addr
- amc
->base
;
235 return amc
->io_write (me
, source
, space
, addr
, nr_bytes
,
236 amc
, mmr_off
, value
);
240 bf50x_ebiu_amc_io_read_buffer (struct hw
*me
, void *dest
, int space
,
241 address_word addr
, unsigned nr_bytes
,
242 struct bfin_ebiu_amc
*amc
, bu32 mmr_off
,
243 void *valuep
, bu16
*value16
, bu32
*value32
)
247 case mmr_offset(amgctl
):
248 case mmr_offset(bf50x
.fctl
):
249 if (!dv_bfin_mmr_require_16 (me
, addr
, nr_bytes
, false))
251 dv_store_2 (dest
, *value16
);
253 case mmr_offset(bf50x
.ambctl0
):
254 case mmr_offset(bf50x
.ambctl1
):
255 case mmr_offset(bf50x
.mode
):
256 dv_store_4 (dest
, *value32
);
259 dv_bfin_mmr_invalid (me
, addr
, nr_bytes
, false);
267 bf53x_ebiu_amc_io_read_buffer (struct hw
*me
, void *dest
, int space
,
268 address_word addr
, unsigned nr_bytes
,
269 struct bfin_ebiu_amc
*amc
, bu32 mmr_off
,
270 void *valuep
, bu16
*value16
, bu32
*value32
)
274 case mmr_offset(amgctl
):
275 if (!dv_bfin_mmr_require_16 (me
, addr
, nr_bytes
, false))
277 dv_store_2 (dest
, *value16
);
279 case mmr_offset(bf53x
.ambctl0
):
280 case mmr_offset(bf53x
.ambctl1
):
281 dv_store_4 (dest
, *value32
);
284 dv_bfin_mmr_invalid (me
, addr
, nr_bytes
, false);
292 bf54x_ebiu_amc_io_read_buffer (struct hw
*me
, void *dest
, int space
,
293 address_word addr
, unsigned nr_bytes
,
294 struct bfin_ebiu_amc
*amc
, bu32 mmr_off
,
295 void *valuep
, bu16
*value16
, bu32
*value32
)
299 case mmr_offset(amgctl
):
300 if (!dv_bfin_mmr_require_16 (me
, addr
, nr_bytes
, false))
302 dv_store_2 (dest
, *value16
);
304 case mmr_offset(bf54x
.ambctl0
):
305 case mmr_offset(bf54x
.ambctl1
):
306 case mmr_offset(bf54x
.mbsctl
):
307 case mmr_offset(bf54x
.arbstat
):
308 case mmr_offset(bf54x
.mode
):
309 case mmr_offset(bf54x
.fctl
):
310 dv_store_4 (dest
, *value32
);
313 dv_bfin_mmr_invalid (me
, addr
, nr_bytes
, false);
321 bfin_ebiu_amc_io_read_buffer (struct hw
*me
, void *dest
, int space
,
322 address_word addr
, unsigned nr_bytes
)
324 struct bfin_ebiu_amc
*amc
= hw_data (me
);
328 /* Invalid access mode is higher priority than missing register. */
329 if (!dv_bfin_mmr_require_16_32 (me
, addr
, nr_bytes
, false))
332 mmr_off
= addr
- amc
->base
;
333 valuep
= (void *)((unsigned long)amc
+ mmr_base() + mmr_off
);
337 return amc
->io_read (me
, dest
, space
, addr
, nr_bytes
, amc
,
338 mmr_off
, valuep
, valuep
, valuep
);
342 bfin_ebiu_amc_attach_address_callback (struct hw
*me
,
346 address_word nr_bytes
,
349 struct bfin_ebiu_amc
*amc
= hw_data (me
);
351 HW_TRACE ((me
, "attach - level=%d, space=%d, addr=0x%lx, nr_bytes=%lu, client=%s",
352 level
, space
, (unsigned long) addr
, (unsigned long) nr_bytes
, hw_path (client
)));
354 if (addr
+ nr_bytes
> ARRAY_SIZE (amc
->slaves
))
355 hw_abort (me
, "ebiu amc attaches are done in terms of banks");
358 amc
->slaves
[addr
+ nr_bytes
] = client
;
360 bfin_ebiu_amc_write_amgctl (me
, amc
, amc
->amgctl
);
364 attach_bfin_ebiu_amc_regs (struct hw
*me
, struct bfin_ebiu_amc
*amc
,
367 address_word attach_address
;
369 unsigned attach_size
;
370 reg_property_spec reg
;
372 if (hw_find_property (me
, "reg") == NULL
)
373 hw_abort (me
, "Missing \"reg\" property");
375 if (!hw_find_reg_array_property (me
, "reg", 0, ®
))
376 hw_abort (me
, "\"reg\" property must contain three addr/size entries");
378 if (hw_find_property (me
, "type") == NULL
)
379 hw_abort (me
, "Missing \"type\" property");
381 hw_unit_address_to_attach_address (hw_parent (me
),
383 &attach_space
, &attach_address
, me
);
384 hw_unit_size_to_attach_size (hw_parent (me
), ®
.size
, &attach_size
, me
);
386 if (attach_size
!= reg_size
)
387 hw_abort (me
, "\"reg\" size must be %#x", reg_size
);
389 hw_attach_address (hw_parent (me
),
390 0, attach_space
, attach_address
, attach_size
, me
);
392 amc
->base
= attach_address
;
396 bfin_ebiu_amc_finish (struct hw
*me
)
398 struct bfin_ebiu_amc
*amc
;
402 amc
= HW_ZALLOC (me
, struct bfin_ebiu_amc
);
404 set_hw_data (me
, amc
);
405 set_hw_io_read_buffer (me
, bfin_ebiu_amc_io_read_buffer
);
406 set_hw_io_write_buffer (me
, bfin_ebiu_amc_io_write_buffer
);
407 set_hw_attach_address (me
, bfin_ebiu_amc_attach_address_callback
);
409 amc
->type
= hw_find_integer_property (me
, "type");
414 amc
->io_write
= bf50x_ebiu_amc_io_write_buffer
;
415 amc
->io_read
= bf50x_ebiu_amc_io_read_buffer
;
416 mmr_names
= bf50x_mmr_names
;
417 reg_size
= sizeof (amc
->bf50x
) + 4;
419 /* Initialize the AMC. */
420 amc
->bank_base
= BFIN_EBIU_AMC_BASE
;
421 amc
->bank_size
= 1 * 1024 * 1024;
423 amc
->bf50x
.ambctl0
= 0x0000FFC2;
424 amc
->bf50x
.ambctl1
= 0x0000FFC2;
425 amc
->bf50x
.mode
= 0x0001;
426 amc
->bf50x
.fctl
= 0x0002;
429 amc
->io_write
= bf54x_ebiu_amc_io_write_buffer
;
430 amc
->io_read
= bf54x_ebiu_amc_io_read_buffer
;
431 mmr_names
= bf54x_mmr_names
;
432 reg_size
= sizeof (amc
->bf54x
) + 4;
434 /* Initialize the AMC. */
435 amc
->bank_base
= BFIN_EBIU_AMC_BASE
;
436 amc
->bank_size
= 64 * 1024 * 1024;
438 amc
->bf54x
.ambctl0
= 0xFFC2FFC2;
439 amc
->bf54x
.ambctl1
= 0xFFC2FFC2;
440 amc
->bf54x
.fctl
= 0x0006;
450 amc
->io_write
= bf53x_ebiu_amc_io_write_buffer
;
451 amc
->io_read
= bf53x_ebiu_amc_io_read_buffer
;
452 mmr_names
= bf53x_mmr_names
;
453 reg_size
= sizeof (amc
->bf53x
) + 4;
455 /* Initialize the AMC. */
456 amc
->bank_base
= BFIN_EBIU_AMC_BASE
;
457 if (amc
->type
== 561)
458 amc
->bank_size
= 64 * 1024 * 1024;
460 amc
->bank_size
= 1 * 1024 * 1024;
462 amc
->bf53x
.ambctl0
= 0xFFC2FFC2;
463 amc
->bf53x
.ambctl1
= 0xFFC2FFC2;
465 case 590 ... 599: /* BF59x has no AMC. */
467 hw_abort (me
, "no support for EBIU AMC on this Blackfin model yet");
470 attach_bfin_ebiu_amc_regs (me
, amc
, reg_size
);
472 bfin_ebiu_amc_write_amgctl (me
, amc
, amgctl
);
475 const struct hw_descriptor dv_bfin_ebiu_amc_descriptor
[] =
477 {"bfin_ebiu_amc", bfin_ebiu_amc_finish
,},