1 /* Blackfin Memory Management Unit (MMU) model.
3 Copyright (C) 2010-2012 Free Software Foundation, Inc.
4 Contributed by Analog Devices, Inc.
6 This file is part of simulators.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 void mmu_check_addr (SIM_CPU
*, bu32 addr
, bool write
, bool inst
, int size
);
25 void mmu_check_cache_addr (SIM_CPU
*, bu32 addr
, bool write
, bool inst
);
26 void mmu_process_fault (SIM_CPU
*, bu32 addr
, bool write
, bool inst
, bool unaligned
, bool miss
);
27 void mmu_log_ifault (SIM_CPU
*);
31 #define ENCPLB (1 << 1)
35 #define ENDCPLB ENCPLB
36 #define DMC_AB_SRAM 0x0
37 #define DMC_AB_CACHE 0xc
38 #define DMC_ACACHE_BSRAM 0x8
41 #define CPLB_VALID (1 << 0)
42 #define CPLB_USER_RD (1 << 2)
43 #define CPLB_USER_WR (1 << 3)
44 #define CPLB_USER_RW (CPLB_USER_RD | CPLB_USER_WR)
45 #define CPLB_SUPV_WR (1 << 4)
46 #define CPLB_L1SRAM (1 << 5)
47 #define CPLB_DA0ACC (1 << 6)
48 #define CPLB_DIRTY (1 << 7)
49 #define CPLB_L1_CHBL (1 << 12)
50 #define CPLB_WT (1 << 14)
51 #define PAGE_SIZE (3 << 16)
52 #define PAGE_SIZE_1K (0 << 16)
53 #define PAGE_SIZE_4K (1 << 16)
54 #define PAGE_SIZE_1M (2 << 16)
55 #define PAGE_SIZE_4M (3 << 16)
58 #define FAULT_CPLB0 (1 << 0)
59 #define FAULT_CPLB1 (1 << 1)
60 #define FAULT_CPLB2 (1 << 2)
61 #define FAULT_CPLB3 (1 << 3)
62 #define FAULT_CPLB4 (1 << 4)
63 #define FAULT_CPLB5 (1 << 5)
64 #define FAULT_CPLB6 (1 << 6)
65 #define FAULT_CPLB7 (1 << 7)
66 #define FAULT_CPLB8 (1 << 8)
67 #define FAULT_CPLB9 (1 << 9)
68 #define FAULT_CPLB10 (1 << 10)
69 #define FAULT_CPLB11 (1 << 11)
70 #define FAULT_CPLB12 (1 << 12)
71 #define FAULT_CPLB13 (1 << 13)
72 #define FAULT_CPLB14 (1 << 14)
73 #define FAULT_CPLB15 (1 << 15)
74 #define FAULT_READ (0 << 16)
75 #define FAULT_WRITE (1 << 16)
76 #define FAULT_USER (0 << 17)
77 #define FAULT_SUPV (1 << 17)
78 #define FAULT_DAG0 (0 << 18)
79 #define FAULT_DAG1 (1 << 18)
80 #define FAULT_ILLADDR (1 << 19)
83 #define TEST_READ (0 << 1)
84 #define TEST_WRITE (1 << 1)
85 #define TEST_TAG_ARRAY (0 << 2)
86 #define TEST_DATA_ARRAY (1 << 2)
87 #define TEST_DBANK (1 << 23)
88 #define TEST_DATA_SRAM (0 << 24)
89 #define TEST_INST_SRAM (1 << 24)