1 /* Blackfin System Interrupt Controller (SIC) model.
3 Copyright (C) 2010-2011 Free Software Foundation, Inc.
4 Contributed by Analog Devices, Inc.
6 This file is part of simulators.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
25 #include "dv-bfin_sic.h"
26 #include "dv-bfin_cec.h"
30 /* We assume first element is the base. */
33 /* Order after here is important -- matches hardware MMR layout. */
34 bu16
BFIN_MMR_16(swrst
);
35 bu16
BFIN_MMR_16(syscr
);
36 bu16
BFIN_MMR_16(rvect
); /* XXX: BF59x has a 32bit AUX_REVID here. */
40 bu32 iar0
, iar1
, iar2
, iar3
;
44 bu32 iar4
, iar5
, iar6
, iar7
;
49 bu32 iar0
, iar1
, iar2
, iar3
;
53 bu32 imask0
, imask1
, imask2
;
54 bu32 isr0
, isr1
, isr2
;
55 bu32 iwr0
, iwr1
, iwr2
;
56 bu32 iar0
, iar1
, iar2
, iar3
;
57 bu32 iar4
, iar5
, iar6
, iar7
;
58 bu32 iar8
, iar9
, iar10
, iar11
;
62 bu32 iar0
, iar1
, iar2
, iar3
;
63 bu32 iar4
, iar5
, iar6
, iar7
;
69 #define mmr_base() offsetof(struct bfin_sic, swrst)
70 #define mmr_offset(mmr) (offsetof(struct bfin_sic, mmr) - mmr_base())
71 #define mmr_idx(mmr) (mmr_offset (mmr) / 4)
73 static const char * const bf52x_mmr_names
[] =
75 "SWRST", "SYSCR", "SIC_RVECT", "SIC_IMASK0", "SIC_IAR0", "SIC_IAR1",
76 "SIC_IAR2", "SIC_IAR3", "SIC_ISR0", "SIC_IWR0",
77 [mmr_idx (bf52x
.imask1
)] = "SIC_IMASK1", "SIC_IAR4", "SIC_IAR5",
78 "SIC_IAR6", "SIC_IAR7", "SIC_ISR1", "SIC_IWR1",
80 static const char * const bf537_mmr_names
[] =
82 "SWRST", "SYSCR", "SIC_RVECT", "SIC_IMASK", "SIC_IAR0", "SIC_IAR1",
83 "SIC_IAR2", "SIC_IAR3", "SIC_ISR", "SIC_IWR",
85 static const char * const bf54x_mmr_names
[] =
87 "SWRST", "SYSCR", "SIC_RVECT", "SIC_IMASK0", "SIC_IMASK1", "SIC_IMASK2",
88 "SIC_ISR0", "SIC_ISR1", "SIC_ISR2", "SIC_IWR0", "SIC_IWR1", "SIC_IWR2",
89 "SIC_IAR0", "SIC_IAR1", "SIC_IAR2", "SIC_IAR3",
90 "SIC_IAR4", "SIC_IAR5", "SIC_IAR6", "SIC_IAR7",
91 "SIC_IAR8", "SIC_IAR9", "SIC_IAR10", "SIC_IAR11",
93 static const char * const bf561_mmr_names
[] =
95 "SWRST", "SYSCR", "SIC_RVECT", "SIC_IMASK0", "SIC_IMASK1",
96 "SIC_IAR0", "SIC_IAR1", "SIC_IAR2", "SIC_IAR3",
97 "SIC_IAR4", "SIC_IAR5", "SIC_IAR6", "SIC_IAR7",
98 "SIC_ISR0", "SIC_ISR1", "SIC_IWR0", "SIC_IWR1",
100 static const char * const *mmr_names
;
101 #define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>")
104 bfin_sic_forward_interrupts (struct hw
*me
, bu32
*isr
, bu32
*imask
, bu32
*iar
)
109 /* Process pending and unmasked interrupts. */
110 ipend
= *isr
& *imask
;
112 /* Usually none are pending unmasked, so avoid bit twiddling. */
116 for (my_port
= 0; my_port
< 32; ++my_port
)
118 bu32 iar_idx
, iar_off
, iar_val
;
119 bu32 bit
= (1 << my_port
);
121 /* This bit isn't pending, so check next one. */
125 /* The IAR registers map the System input to the Core output.
126 Every 4 bits in the IAR are used to map to IVG{7..15}. */
127 iar_idx
= my_port
/ 8;
128 iar_off
= (my_port
% 8) * 4;
129 iar_val
= (iar
[iar_idx
] & (0xf << iar_off
)) >> iar_off
;
130 HW_TRACE ((me
, "forwarding int %i to CEC", IVG7
+ iar_val
));
131 hw_port_event (me
, IVG7
+ iar_val
, 1);
136 bfin_sic_52x_forward_interrupts (struct hw
*me
, struct bfin_sic
*sic
)
138 bfin_sic_forward_interrupts (me
, &sic
->bf52x
.isr0
, &sic
->bf52x
.imask0
, &sic
->bf52x
.iar0
);
139 bfin_sic_forward_interrupts (me
, &sic
->bf52x
.isr1
, &sic
->bf52x
.imask1
, &sic
->bf52x
.iar4
);
143 bfin_sic_52x_io_write_buffer (struct hw
*me
, const void *source
, int space
,
144 address_word addr
, unsigned nr_bytes
)
146 struct bfin_sic
*sic
= hw_data (me
);
154 value
= dv_load_4 (source
);
156 value
= dv_load_2 (source
);
158 mmr_off
= addr
- sic
->base
;
159 valuep
= (void *)((unsigned long)sic
+ mmr_base() + mmr_off
);
165 /* XXX: Discard all SIC writes for now. */
168 case mmr_offset(swrst
):
169 /* XXX: This should trigger a software reset ... */
171 case mmr_offset(syscr
):
172 /* XXX: what to do ... */
174 case mmr_offset(bf52x
.imask0
):
175 case mmr_offset(bf52x
.imask1
):
176 bfin_sic_52x_forward_interrupts (me
, sic
);
179 case mmr_offset(bf52x
.iar0
) ... mmr_offset(bf52x
.iar3
):
180 case mmr_offset(bf52x
.iar4
) ... mmr_offset(bf52x
.iar7
):
181 case mmr_offset(bf52x
.iwr0
):
182 case mmr_offset(bf52x
.iwr1
):
185 case mmr_offset(bf52x
.isr0
):
186 case mmr_offset(bf52x
.isr1
):
187 /* ISR is read-only. */
190 /* XXX: Should discard other writes. */
198 bfin_sic_52x_io_read_buffer (struct hw
*me
, void *dest
, int space
,
199 address_word addr
, unsigned nr_bytes
)
201 struct bfin_sic
*sic
= hw_data (me
);
207 mmr_off
= addr
- sic
->base
;
208 valuep
= (void *)((unsigned long)sic
+ mmr_base() + mmr_off
);
216 case mmr_offset(swrst
):
217 case mmr_offset(syscr
):
218 case mmr_offset(rvect
):
219 dv_store_2 (dest
, *value16p
);
221 case mmr_offset(bf52x
.imask0
):
222 case mmr_offset(bf52x
.imask1
):
223 case mmr_offset(bf52x
.iar0
) ... mmr_offset(bf52x
.iar3
):
224 case mmr_offset(bf52x
.iar4
) ... mmr_offset(bf52x
.iar7
):
225 case mmr_offset(bf52x
.iwr0
):
226 case mmr_offset(bf52x
.iwr1
):
227 case mmr_offset(bf52x
.isr0
):
228 case mmr_offset(bf52x
.isr1
):
229 dv_store_4 (dest
, *value32p
);
233 dv_store_2 (dest
, 0);
235 dv_store_4 (dest
, 0);
243 bfin_sic_537_forward_interrupts (struct hw
*me
, struct bfin_sic
*sic
)
245 bfin_sic_forward_interrupts (me
, &sic
->bf537
.isr
, &sic
->bf537
.imask
, &sic
->bf537
.iar0
);
249 bfin_sic_537_io_write_buffer (struct hw
*me
, const void *source
, int space
,
250 address_word addr
, unsigned nr_bytes
)
252 struct bfin_sic
*sic
= hw_data (me
);
260 value
= dv_load_4 (source
);
262 value
= dv_load_2 (source
);
264 mmr_off
= addr
- sic
->base
;
265 valuep
= (void *)((unsigned long)sic
+ mmr_base() + mmr_off
);
271 /* XXX: Discard all SIC writes for now. */
274 case mmr_offset(swrst
):
275 /* XXX: This should trigger a software reset ... */
277 case mmr_offset(syscr
):
278 /* XXX: what to do ... */
280 case mmr_offset(bf537
.imask
):
281 bfin_sic_537_forward_interrupts (me
, sic
);
284 case mmr_offset(bf537
.iar0
):
285 case mmr_offset(bf537
.iar1
):
286 case mmr_offset(bf537
.iar2
):
287 case mmr_offset(bf537
.iar3
):
288 case mmr_offset(bf537
.iwr
):
291 case mmr_offset(bf537
.isr
):
292 /* ISR is read-only. */
295 /* XXX: Should discard other writes. */
303 bfin_sic_537_io_read_buffer (struct hw
*me
, void *dest
, int space
,
304 address_word addr
, unsigned nr_bytes
)
306 struct bfin_sic
*sic
= hw_data (me
);
312 mmr_off
= addr
- sic
->base
;
313 valuep
= (void *)((unsigned long)sic
+ mmr_base() + mmr_off
);
321 case mmr_offset(swrst
):
322 case mmr_offset(syscr
):
323 case mmr_offset(rvect
):
324 dv_store_2 (dest
, *value16p
);
326 case mmr_offset(bf537
.imask
):
327 case mmr_offset(bf537
.iar0
):
328 case mmr_offset(bf537
.iar1
):
329 case mmr_offset(bf537
.iar2
):
330 case mmr_offset(bf537
.iar3
):
331 case mmr_offset(bf537
.isr
):
332 case mmr_offset(bf537
.iwr
):
333 dv_store_4 (dest
, *value32p
);
337 dv_store_2 (dest
, 0);
339 dv_store_4 (dest
, 0);
347 bfin_sic_54x_forward_interrupts (struct hw
*me
, struct bfin_sic
*sic
)
349 bfin_sic_forward_interrupts (me
, &sic
->bf54x
.isr0
, &sic
->bf54x
.imask0
, &sic
->bf54x
.iar0
);
350 bfin_sic_forward_interrupts (me
, &sic
->bf54x
.isr1
, &sic
->bf54x
.imask1
, &sic
->bf54x
.iar4
);
351 bfin_sic_forward_interrupts (me
, &sic
->bf54x
.isr2
, &sic
->bf54x
.imask2
, &sic
->bf54x
.iar8
);
355 bfin_sic_54x_io_write_buffer (struct hw
*me
, const void *source
, int space
,
356 address_word addr
, unsigned nr_bytes
)
358 struct bfin_sic
*sic
= hw_data (me
);
366 value
= dv_load_4 (source
);
368 value
= dv_load_2 (source
);
370 mmr_off
= addr
- sic
->base
;
371 valuep
= (void *)((unsigned long)sic
+ mmr_base() + mmr_off
);
377 /* XXX: Discard all SIC writes for now. */
380 case mmr_offset(swrst
):
381 /* XXX: This should trigger a software reset ... */
383 case mmr_offset(syscr
):
384 /* XXX: what to do ... */
386 case mmr_offset(bf54x
.imask0
) ... mmr_offset(bf54x
.imask2
):
387 bfin_sic_54x_forward_interrupts (me
, sic
);
390 case mmr_offset(bf54x
.iar0
) ... mmr_offset(bf54x
.iar11
):
391 case mmr_offset(bf54x
.iwr0
) ... mmr_offset(bf54x
.iwr2
):
394 case mmr_offset(bf54x
.isr0
) ... mmr_offset(bf54x
.isr2
):
395 /* ISR is read-only. */
398 /* XXX: Should discard other writes. */
406 bfin_sic_54x_io_read_buffer (struct hw
*me
, void *dest
, int space
,
407 address_word addr
, unsigned nr_bytes
)
409 struct bfin_sic
*sic
= hw_data (me
);
415 mmr_off
= addr
- sic
->base
;
416 valuep
= (void *)((unsigned long)sic
+ mmr_base() + mmr_off
);
424 case mmr_offset(swrst
):
425 case mmr_offset(syscr
):
426 case mmr_offset(rvect
):
427 dv_store_2 (dest
, *value16p
);
429 case mmr_offset(bf54x
.imask0
) ... mmr_offset(bf54x
.imask2
):
430 case mmr_offset(bf54x
.iar0
) ... mmr_offset(bf54x
.iar11
):
431 case mmr_offset(bf54x
.iwr0
) ... mmr_offset(bf54x
.iwr2
):
432 case mmr_offset(bf54x
.isr0
) ... mmr_offset(bf54x
.isr2
):
433 dv_store_4 (dest
, *value32p
);
437 dv_store_2 (dest
, 0);
439 dv_store_4 (dest
, 0);
447 bfin_sic_561_forward_interrupts (struct hw
*me
, struct bfin_sic
*sic
)
449 bfin_sic_forward_interrupts (me
, &sic
->bf561
.isr0
, &sic
->bf561
.imask0
, &sic
->bf561
.iar0
);
450 bfin_sic_forward_interrupts (me
, &sic
->bf561
.isr1
, &sic
->bf561
.imask1
, &sic
->bf561
.iar4
);
454 bfin_sic_561_io_write_buffer (struct hw
*me
, const void *source
, int space
,
455 address_word addr
, unsigned nr_bytes
)
457 struct bfin_sic
*sic
= hw_data (me
);
465 value
= dv_load_4 (source
);
467 value
= dv_load_2 (source
);
469 mmr_off
= addr
- sic
->base
;
470 valuep
= (void *)((unsigned long)sic
+ mmr_base() + mmr_off
);
476 /* XXX: Discard all SIC writes for now. */
479 case mmr_offset(swrst
):
480 /* XXX: This should trigger a software reset ... */
482 case mmr_offset(syscr
):
483 /* XXX: what to do ... */
485 case mmr_offset(bf561
.imask0
):
486 case mmr_offset(bf561
.imask1
):
487 bfin_sic_561_forward_interrupts (me
, sic
);
490 case mmr_offset(bf561
.iar0
) ... mmr_offset(bf561
.iar3
):
491 case mmr_offset(bf561
.iar4
) ... mmr_offset(bf561
.iar7
):
492 case mmr_offset(bf561
.iwr0
):
493 case mmr_offset(bf561
.iwr1
):
496 case mmr_offset(bf561
.isr0
):
497 case mmr_offset(bf561
.isr1
):
498 /* ISR is read-only. */
501 /* XXX: Should discard other writes. */
509 bfin_sic_561_io_read_buffer (struct hw
*me
, void *dest
, int space
,
510 address_word addr
, unsigned nr_bytes
)
512 struct bfin_sic
*sic
= hw_data (me
);
518 mmr_off
= addr
- sic
->base
;
519 valuep
= (void *)((unsigned long)sic
+ mmr_base() + mmr_off
);
527 case mmr_offset(swrst
):
528 case mmr_offset(syscr
):
529 case mmr_offset(rvect
):
530 dv_store_2 (dest
, *value16p
);
532 case mmr_offset(bf561
.imask0
):
533 case mmr_offset(bf561
.imask1
):
534 case mmr_offset(bf561
.iar0
) ... mmr_offset(bf561
.iar3
):
535 case mmr_offset(bf561
.iar4
) ... mmr_offset(bf561
.iar7
):
536 case mmr_offset(bf561
.iwr0
):
537 case mmr_offset(bf561
.iwr1
):
538 case mmr_offset(bf561
.isr0
):
539 case mmr_offset(bf561
.isr1
):
540 dv_store_4 (dest
, *value32p
);
544 dv_store_2 (dest
, 0);
546 dv_store_4 (dest
, 0);
553 /* XXX: This doesn't handle DMA<->peripheral mappings. */
554 #define BFIN_SIC_TO_CEC_PORTS \
555 { "ivg7", IVG7, 0, output_port, }, \
556 { "ivg8", IVG8, 0, output_port, }, \
557 { "ivg9", IVG9, 0, output_port, }, \
558 { "ivg10", IVG10, 0, output_port, }, \
559 { "ivg11", IVG11, 0, output_port, }, \
560 { "ivg12", IVG12, 0, output_port, }, \
561 { "ivg13", IVG13, 0, output_port, }, \
562 { "ivg14", IVG14, 0, output_port, }, \
563 { "ivg15", IVG15, 0, output_port, },
565 /* Give each SIC its own base to make it easier to extract the pin at
566 runtime. The pin is used as its bit position in the SIC MMRs. */
567 #define ENC(sic, pin) (((sic) << 8) + (pin))
568 #define DEC_PIN(pin) ((pin) % 0x100)
569 #define DEC_SIC(pin) ((pin) >> 8)
571 static const struct hw_port_descriptor bfin_sic_50x_ports
[] =
573 BFIN_SIC_TO_CEC_PORTS
575 { "pll", ENC(0, 0), 0, input_port
, },
576 { "dma_stat", ENC(0, 1), 0, input_port
, },
577 { "ppi@0", ENC(0, 2), 0, input_port
, },
578 { "sport@0_stat", ENC(0, 3), 0, input_port
, },
579 { "sport@1_stat", ENC(0, 4), 0, input_port
, },
580 { "uart2@0_stat", ENC(0, 5), 0, input_port
, },
581 { "uart2@1_stat", ENC(0, 6), 0, input_port
, },
582 { "spi@0", ENC(0, 7), 0, input_port
, },
583 { "spi@1", ENC(0, 8), 0, input_port
, },
584 { "can_stat", ENC(0, 9), 0, input_port
, },
585 { "rsi_int0", ENC(0, 10), 0, input_port
, },
586 /*{ "reserved", ENC(0, 11), 0, input_port, },*/
587 { "counter@0", ENC(0, 12), 0, input_port
, },
588 { "counter@1", ENC(0, 13), 0, input_port
, },
589 { "dma@0", ENC(0, 14), 0, input_port
, },
590 { "dma@1", ENC(0, 15), 0, input_port
, },
591 { "dma@2", ENC(0, 16), 0, input_port
, },
592 { "dma@3", ENC(0, 17), 0, input_port
, },
593 { "dma@4", ENC(0, 18), 0, input_port
, },
594 { "dma@5", ENC(0, 19), 0, input_port
, },
595 { "dma@6", ENC(0, 20), 0, input_port
, },
596 { "dma@7", ENC(0, 21), 0, input_port
, },
597 { "dma@8", ENC(0, 22), 0, input_port
, },
598 { "dma@9", ENC(0, 23), 0, input_port
, },
599 { "dma@10", ENC(0, 24), 0, input_port
, },
600 { "dma@11", ENC(0, 25), 0, input_port
, },
601 { "can_rx", ENC(0, 26), 0, input_port
, },
602 { "can_tx", ENC(0, 27), 0, input_port
, },
603 { "twi@0", ENC(0, 28), 0, input_port
, },
604 { "portf_irq_a", ENC(0, 29), 0, input_port
, },
605 { "portf_irq_b", ENC(0, 30), 0, input_port
, },
606 /*{ "reserved", ENC(0, 31), 0, input_port, },*/
608 { "gptimer@0", ENC(1, 0), 0, input_port
, },
609 { "gptimer@1", ENC(1, 1), 0, input_port
, },
610 { "gptimer@2", ENC(1, 2), 0, input_port
, },
611 { "gptimer@3", ENC(1, 3), 0, input_port
, },
612 { "gptimer@4", ENC(1, 4), 0, input_port
, },
613 { "gptimer@5", ENC(1, 5), 0, input_port
, },
614 { "gptimer@6", ENC(1, 6), 0, input_port
, },
615 { "gptimer@7", ENC(1, 7), 0, input_port
, },
616 { "portg_irq_a", ENC(1, 8), 0, input_port
, },
617 { "portg_irq_b", ENC(1, 9), 0, input_port
, },
618 { "mdma@0", ENC(1, 10), 0, input_port
, },
619 { "mdma@1", ENC(1, 11), 0, input_port
, },
620 { "wdog", ENC(1, 12), 0, input_port
, },
621 { "porth_irq_a", ENC(1, 13), 0, input_port
, },
622 { "porth_irq_b", ENC(1, 14), 0, input_port
, },
623 { "acm_stat", ENC(1, 15), 0, input_port
, },
624 { "acm_int", ENC(1, 16), 0, input_port
, },
625 /*{ "reserved", ENC(1, 17), 0, input_port, },*/
626 /*{ "reserved", ENC(1, 18), 0, input_port, },*/
627 { "pwm@0_trip", ENC(1, 19), 0, input_port
, },
628 { "pwm@0_sync", ENC(1, 20), 0, input_port
, },
629 { "pwm@1_trip", ENC(1, 21), 0, input_port
, },
630 { "pwm@1_sync", ENC(1, 22), 0, input_port
, },
631 { "rsi_int1", ENC(1, 23), 0, input_port
, },
635 static const struct hw_port_descriptor bfin_sic_51x_ports
[] =
637 BFIN_SIC_TO_CEC_PORTS
639 { "pll", ENC(0, 0), 0, input_port
, },
640 { "dma_stat", ENC(0, 1), 0, input_port
, },
641 { "dmar0_block", ENC(0, 2), 0, input_port
, },
642 { "dmar1_block", ENC(0, 3), 0, input_port
, },
643 { "dmar0_over", ENC(0, 4), 0, input_port
, },
644 { "dmar1_over", ENC(0, 5), 0, input_port
, },
645 { "ppi@0", ENC(0, 6), 0, input_port
, },
646 { "emac_stat", ENC(0, 7), 0, input_port
, },
647 { "sport@0_stat", ENC(0, 8), 0, input_port
, },
648 { "sport@1_stat", ENC(0, 9), 0, input_port
, },
649 { "ptp_err", ENC(0, 10), 0, input_port
, },
650 /*{ "reserved", ENC(0, 11), 0, input_port, },*/
651 { "uart@0_stat", ENC(0, 12), 0, input_port
, },
652 { "uart@1_stat", ENC(0, 13), 0, input_port
, },
653 { "rtc", ENC(0, 14), 0, input_port
, },
654 { "dma@0", ENC(0, 15), 0, input_port
, },
655 { "dma@3", ENC(0, 16), 0, input_port
, },
656 { "dma@4", ENC(0, 17), 0, input_port
, },
657 { "dma@5", ENC(0, 18), 0, input_port
, },
658 { "dma@6", ENC(0, 19), 0, input_port
, },
659 { "twi@0", ENC(0, 20), 0, input_port
, },
660 { "dma@7", ENC(0, 21), 0, input_port
, },
661 { "dma@8", ENC(0, 22), 0, input_port
, },
662 { "dma@9", ENC(0, 23), 0, input_port
, },
663 { "dma@10", ENC(0, 24), 0, input_port
, },
664 { "dma@11", ENC(0, 25), 0, input_port
, },
665 { "otp", ENC(0, 26), 0, input_port
, },
666 { "counter", ENC(0, 27), 0, input_port
, },
667 { "dma@1", ENC(0, 28), 0, input_port
, },
668 { "porth_irq_a", ENC(0, 29), 0, input_port
, },
669 { "dma@2", ENC(0, 30), 0, input_port
, },
670 { "porth_irq_b", ENC(0, 31), 0, input_port
, },
672 { "gptimer@0", ENC(1, 0), 0, input_port
, },
673 { "gptimer@1", ENC(1, 1), 0, input_port
, },
674 { "gptimer@2", ENC(1, 2), 0, input_port
, },
675 { "gptimer@3", ENC(1, 3), 0, input_port
, },
676 { "gptimer@4", ENC(1, 4), 0, input_port
, },
677 { "gptimer@5", ENC(1, 5), 0, input_port
, },
678 { "gptimer@6", ENC(1, 6), 0, input_port
, },
679 { "gptimer@7", ENC(1, 7), 0, input_port
, },
680 { "portg_irq_a", ENC(1, 8), 0, input_port
, },
681 { "portg_irq_b", ENC(1, 9), 0, input_port
, },
682 { "mdma@0", ENC(1, 10), 0, input_port
, },
683 { "mdma@1", ENC(1, 11), 0, input_port
, },
684 { "wdog", ENC(1, 12), 0, input_port
, },
685 { "portf_irq_a", ENC(1, 13), 0, input_port
, },
686 { "portf_irq_b", ENC(1, 14), 0, input_port
, },
687 { "spi@0", ENC(1, 15), 0, input_port
, },
688 { "spi@1", ENC(1, 16), 0, input_port
, },
689 /*{ "reserved", ENC(1, 17), 0, input_port, },*/
690 /*{ "reserved", ENC(1, 18), 0, input_port, },*/
691 { "rsi_int0", ENC(1, 19), 0, input_port
, },
692 { "rsi_int1", ENC(1, 20), 0, input_port
, },
693 { "pwm_trip", ENC(1, 21), 0, input_port
, },
694 { "pwm_sync", ENC(1, 22), 0, input_port
, },
695 { "ptp_stat", ENC(1, 23), 0, input_port
, },
699 static const struct hw_port_descriptor bfin_sic_52x_ports
[] =
701 BFIN_SIC_TO_CEC_PORTS
703 { "pll", ENC(0, 0), 0, input_port
, },
704 { "dma_stat", ENC(0, 1), 0, input_port
, },
705 { "dmar0_block", ENC(0, 2), 0, input_port
, },
706 { "dmar1_block", ENC(0, 3), 0, input_port
, },
707 { "dmar0_over", ENC(0, 4), 0, input_port
, },
708 { "dmar1_over", ENC(0, 5), 0, input_port
, },
709 { "ppi@0", ENC(0, 6), 0, input_port
, },
710 { "emac_stat", ENC(0, 7), 0, input_port
, },
711 { "sport@0_stat", ENC(0, 8), 0, input_port
, },
712 { "sport@1_stat", ENC(0, 9), 0, input_port
, },
713 /*{ "reserved", ENC(0, 10), 0, input_port, },*/
714 /*{ "reserved", ENC(0, 11), 0, input_port, },*/
715 { "uart@0_stat", ENC(0, 12), 0, input_port
, },
716 { "uart@1_stat", ENC(0, 13), 0, input_port
, },
717 { "rtc", ENC(0, 14), 0, input_port
, },
718 { "dma@0", ENC(0, 15), 0, input_port
, },
719 { "dma@3", ENC(0, 16), 0, input_port
, },
720 { "dma@4", ENC(0, 17), 0, input_port
, },
721 { "dma@5", ENC(0, 18), 0, input_port
, },
722 { "dma@6", ENC(0, 19), 0, input_port
, },
723 { "twi@0", ENC(0, 20), 0, input_port
, },
724 { "dma@7", ENC(0, 21), 0, input_port
, },
725 { "dma@8", ENC(0, 22), 0, input_port
, },
726 { "dma@9", ENC(0, 23), 0, input_port
, },
727 { "dma@10", ENC(0, 24), 0, input_port
, },
728 { "dma@11", ENC(0, 25), 0, input_port
, },
729 { "otp", ENC(0, 26), 0, input_port
, },
730 { "counter", ENC(0, 27), 0, input_port
, },
731 { "dma@1", ENC(0, 28), 0, input_port
, },
732 { "porth_irq_a", ENC(0, 29), 0, input_port
, },
733 { "dma@2", ENC(0, 30), 0, input_port
, },
734 { "porth_irq_b", ENC(0, 31), 0, input_port
, },
736 { "gptimer@0", ENC(1, 0), 0, input_port
, },
737 { "gptimer@1", ENC(1, 1), 0, input_port
, },
738 { "gptimer@2", ENC(1, 2), 0, input_port
, },
739 { "gptimer@3", ENC(1, 3), 0, input_port
, },
740 { "gptimer@4", ENC(1, 4), 0, input_port
, },
741 { "gptimer@5", ENC(1, 5), 0, input_port
, },
742 { "gptimer@6", ENC(1, 6), 0, input_port
, },
743 { "gptimer@7", ENC(1, 7), 0, input_port
, },
744 { "portg_irq_a", ENC(1, 8), 0, input_port
, },
745 { "portg_irq_b", ENC(1, 9), 0, input_port
, },
746 { "mdma@0", ENC(1, 10), 0, input_port
, },
747 { "mdma@1", ENC(1, 11), 0, input_port
, },
748 { "wdog", ENC(1, 12), 0, input_port
, },
749 { "portf_irq_a", ENC(1, 13), 0, input_port
, },
750 { "portf_irq_b", ENC(1, 14), 0, input_port
, },
751 { "spi@0", ENC(1, 15), 0, input_port
, },
752 { "nfc_stat", ENC(1, 16), 0, input_port
, },
753 { "hostdp_stat", ENC(1, 17), 0, input_port
, },
754 { "hostdp_done", ENC(1, 18), 0, input_port
, },
755 { "usb_int0", ENC(1, 20), 0, input_port
, },
756 { "usb_int1", ENC(1, 21), 0, input_port
, },
757 { "usb_int2", ENC(1, 22), 0, input_port
, },
762 bfin_sic_52x_port_event (struct hw
*me
, int my_port
, struct hw
*source
,
763 int source_port
, int level
)
765 struct bfin_sic
*sic
= hw_data (me
);
766 bu32 idx
= DEC_SIC (my_port
);
767 bu32 pin
= DEC_PIN (my_port
);
770 HW_TRACE ((me
, "processing system int from %i (SIC %u pin %u)",
773 /* SIC only exists to forward interrupts from the system to the CEC. */
776 case 0: sic
->bf52x
.isr0
|= bit
; break;
777 case 1: sic
->bf52x
.isr1
|= bit
; break;
780 /* XXX: Handle SIC wakeup source ?
781 if (sic->bf52x.iwr0 & bit)
783 if (sic->bf52x.iwr1 & bit)
787 bfin_sic_52x_forward_interrupts (me
, sic
);
790 static const struct hw_port_descriptor bfin_sic_533_ports
[] =
792 BFIN_SIC_TO_CEC_PORTS
793 { "pll", ENC(0, 0), 0, input_port
, },
794 { "dma_stat", ENC(0, 1), 0, input_port
, },
795 { "ppi@0", ENC(0, 2), 0, input_port
, },
796 { "sport@0_stat", ENC(0, 3), 0, input_port
, },
797 { "sport@1_stat", ENC(0, 4), 0, input_port
, },
798 { "spi@0", ENC(0, 5), 0, input_port
, },
799 { "uart@0_stat", ENC(0, 6), 0, input_port
, },
800 { "rtc", ENC(0, 7), 0, input_port
, },
801 { "dma@0", ENC(0, 8), 0, input_port
, },
802 { "dma@1", ENC(0, 9), 0, input_port
, },
803 { "dma@2", ENC(0, 10), 0, input_port
, },
804 { "dma@3", ENC(0, 11), 0, input_port
, },
805 { "dma@4", ENC(0, 12), 0, input_port
, },
806 { "dma@5", ENC(0, 13), 0, input_port
, },
807 { "dma@6", ENC(0, 14), 0, input_port
, },
808 { "dma@7", ENC(0, 15), 0, input_port
, },
809 { "gptimer@0", ENC(0, 16), 0, input_port
, },
810 { "gptimer@1", ENC(0, 17), 0, input_port
, },
811 { "gptimer@2", ENC(0, 18), 0, input_port
, },
812 { "portf_irq_a", ENC(0, 19), 0, input_port
, },
813 { "portf_irq_b", ENC(0, 20), 0, input_port
, },
814 { "mdma@0", ENC(0, 21), 0, input_port
, },
815 { "mdma@1", ENC(0, 22), 0, input_port
, },
816 { "wdog", ENC(0, 23), 0, input_port
, },
820 /* The encoding here is uglier due to multiple sources being muxed into
821 the same interrupt line. So give each pin an arbitrary "SIC" so that
822 the resulting id is unique across all ports. */
823 static const struct hw_port_descriptor bfin_sic_537_ports
[] =
825 BFIN_SIC_TO_CEC_PORTS
826 { "pll", ENC(0, 0), 0, input_port
, },
827 { "dma_stat", ENC(0, 1), 0, input_port
, },
828 { "dmar0_block", ENC(1, 1), 0, input_port
, },
829 { "dmar1_block", ENC(2, 1), 0, input_port
, },
830 { "dmar0_over", ENC(3, 1), 0, input_port
, },
831 { "dmar1_over", ENC(4, 1), 0, input_port
, },
832 { "can_stat", ENC(0, 2), 0, input_port
, },
833 { "emac_stat", ENC(1, 2), 0, input_port
, },
834 { "sport@0_stat", ENC(2, 2), 0, input_port
, },
835 { "sport@1_stat", ENC(3, 2), 0, input_port
, },
836 { "ppi@0", ENC(4, 2), 0, input_port
, },
837 { "spi@0", ENC(5, 2), 0, input_port
, },
838 { "uart@0_stat", ENC(6, 2), 0, input_port
, },
839 { "uart@1_stat", ENC(7, 2), 0, input_port
, },
840 { "rtc", ENC(0, 3), 0, input_port
, },
841 { "dma@0", ENC(0, 4), 0, input_port
, },
842 { "dma@3", ENC(0, 5), 0, input_port
, },
843 { "dma@4", ENC(0, 6), 0, input_port
, },
844 { "dma@5", ENC(0, 7), 0, input_port
, },
845 { "dma@6", ENC(0, 8), 0, input_port
, },
846 { "twi@0", ENC(0, 9), 0, input_port
, },
847 { "dma@7", ENC(0, 10), 0, input_port
, },
848 { "dma@8", ENC(0, 11), 0, input_port
, },
849 { "dma@9", ENC(0, 12), 0, input_port
, },
850 { "dma@10", ENC(0, 13), 0, input_port
, },
851 { "dma@11", ENC(0, 14), 0, input_port
, },
852 { "can_rx", ENC(0, 15), 0, input_port
, },
853 { "can_tx", ENC(0, 16), 0, input_port
, },
854 { "dma@1", ENC(0, 17), 0, input_port
, },
855 { "porth_irq_a", ENC(1, 17), 0, input_port
, },
856 { "dma@2", ENC(0, 18), 0, input_port
, },
857 { "porth_irq_b", ENC(1, 18), 0, input_port
, },
858 { "gptimer@0", ENC(0, 19), 0, input_port
, },
859 { "gptimer@1", ENC(0, 20), 0, input_port
, },
860 { "gptimer@2", ENC(0, 21), 0, input_port
, },
861 { "gptimer@3", ENC(0, 22), 0, input_port
, },
862 { "gptimer@4", ENC(0, 23), 0, input_port
, },
863 { "gptimer@5", ENC(0, 24), 0, input_port
, },
864 { "gptimer@6", ENC(0, 25), 0, input_port
, },
865 { "gptimer@7", ENC(0, 26), 0, input_port
, },
866 { "portf_irq_a", ENC(0, 27), 0, input_port
, },
867 { "portg_irq_a", ENC(1, 27), 0, input_port
, },
868 { "portg_irq_b", ENC(0, 28), 0, input_port
, },
869 { "mdma@0", ENC(0, 29), 0, input_port
, },
870 { "mdma@1", ENC(0, 30), 0, input_port
, },
871 { "wdog", ENC(0, 31), 0, input_port
, },
872 { "portf_irq_b", ENC(1, 31), 0, input_port
, },
877 bfin_sic_537_port_event (struct hw
*me
, int my_port
, struct hw
*source
,
878 int source_port
, int level
)
880 struct bfin_sic
*sic
= hw_data (me
);
881 bu32 idx
= DEC_SIC (my_port
);
882 bu32 pin
= DEC_PIN (my_port
);
885 HW_TRACE ((me
, "processing system int from %i (SIC %u pin %u)",
888 /* SIC only exists to forward interrupts from the system to the CEC. */
889 sic
->bf537
.isr
|= bit
;
891 /* XXX: Handle SIC wakeup source ?
892 if (sic->bf537.iwr & bit)
896 bfin_sic_537_forward_interrupts (me
, sic
);
899 static const struct hw_port_descriptor bfin_sic_538_ports
[] =
901 BFIN_SIC_TO_CEC_PORTS
903 { "pll", ENC(0, 0), 0, input_port
, },
904 { "dmac@0_stat", ENC(0, 1), 0, input_port
, },
905 { "ppi@0", ENC(0, 2), 0, input_port
, },
906 { "sport@0_stat", ENC(0, 3), 0, input_port
, },
907 { "sport@1_stat", ENC(0, 4), 0, input_port
, },
908 { "spi@0", ENC(0, 5), 0, input_port
, },
909 { "uart@0_stat", ENC(0, 6), 0, input_port
, },
910 { "rtc", ENC(0, 7), 0, input_port
, },
911 { "dma@0", ENC(0, 8), 0, input_port
, },
912 { "dma@1", ENC(0, 9), 0, input_port
, },
913 { "dma@2", ENC(0, 10), 0, input_port
, },
914 { "dma@3", ENC(0, 11), 0, input_port
, },
915 { "dma@4", ENC(0, 12), 0, input_port
, },
916 { "dma@5", ENC(0, 13), 0, input_port
, },
917 { "dma@6", ENC(0, 14), 0, input_port
, },
918 { "dma@7", ENC(0, 15), 0, input_port
, },
919 { "gptimer@0", ENC(0, 16), 0, input_port
, },
920 { "gptimer@1", ENC(0, 17), 0, input_port
, },
921 { "gptimer@2", ENC(0, 18), 0, input_port
, },
922 { "portf_irq_a", ENC(0, 19), 0, input_port
, },
923 { "portf_irq_b", ENC(0, 20), 0, input_port
, },
924 { "mdma@0", ENC(0, 21), 0, input_port
, },
925 { "mdma@1", ENC(0, 22), 0, input_port
, },
926 { "wdog", ENC(0, 23), 0, input_port
, },
927 { "dmac@1_stat", ENC(0, 24), 0, input_port
, },
928 { "sport@2_stat", ENC(0, 25), 0, input_port
, },
929 { "sport@3_stat", ENC(0, 26), 0, input_port
, },
930 /*{ "reserved", ENC(0, 27), 0, input_port, },*/
931 { "spi@1", ENC(0, 28), 0, input_port
, },
932 { "spi@2", ENC(0, 29), 0, input_port
, },
933 { "uart@1_stat", ENC(0, 30), 0, input_port
, },
934 { "uart@2_stat", ENC(0, 31), 0, input_port
, },
936 { "can_stat", ENC(1, 0), 0, input_port
, },
937 { "dma@8", ENC(1, 1), 0, input_port
, },
938 { "dma@9", ENC(1, 2), 0, input_port
, },
939 { "dma@10", ENC(1, 3), 0, input_port
, },
940 { "dma@11", ENC(1, 4), 0, input_port
, },
941 { "dma@12", ENC(1, 5), 0, input_port
, },
942 { "dma@13", ENC(1, 6), 0, input_port
, },
943 { "dma@14", ENC(1, 7), 0, input_port
, },
944 { "dma@15", ENC(1, 8), 0, input_port
, },
945 { "dma@16", ENC(1, 9), 0, input_port
, },
946 { "dma@17", ENC(1, 10), 0, input_port
, },
947 { "dma@18", ENC(1, 11), 0, input_port
, },
948 { "dma@19", ENC(1, 12), 0, input_port
, },
949 { "twi@0", ENC(1, 13), 0, input_port
, },
950 { "twi@1", ENC(1, 14), 0, input_port
, },
951 { "can_rx", ENC(1, 15), 0, input_port
, },
952 { "can_tx", ENC(1, 16), 0, input_port
, },
953 { "mdma@2", ENC(1, 17), 0, input_port
, },
954 { "mdma@3", ENC(1, 18), 0, input_port
, },
958 static const struct hw_port_descriptor bfin_sic_54x_ports
[] =
960 BFIN_SIC_TO_CEC_PORTS
962 { "pll", ENC(0, 0), 0, input_port
, },
963 { "dmac@0_stat", ENC(0, 1), 0, input_port
, },
964 { "eppi@0", ENC(0, 2), 0, input_port
, },
965 { "sport@0_stat", ENC(0, 3), 0, input_port
, },
966 { "sport@1_stat", ENC(0, 4), 0, input_port
, },
967 { "spi@0", ENC(0, 5), 0, input_port
, },
968 { "uart2@0_stat", ENC(0, 6), 0, input_port
, },
969 { "rtc", ENC(0, 7), 0, input_port
, },
970 { "dma@12", ENC(0, 8), 0, input_port
, },
971 { "dma@0", ENC(0, 9), 0, input_port
, },
972 { "dma@1", ENC(0, 10), 0, input_port
, },
973 { "dma@2", ENC(0, 11), 0, input_port
, },
974 { "dma@3", ENC(0, 12), 0, input_port
, },
975 { "dma@4", ENC(0, 13), 0, input_port
, },
976 { "dma@6", ENC(0, 14), 0, input_port
, },
977 { "dma@7", ENC(0, 15), 0, input_port
, },
978 { "gptimer@8", ENC(0, 16), 0, input_port
, },
979 { "gptimer@9", ENC(0, 17), 0, input_port
, },
980 { "gptimer@10", ENC(0, 18), 0, input_port
, },
981 { "pint@0", ENC(0, 19), 0, input_port
, },
982 { "pint@1", ENC(0, 20), 0, input_port
, },
983 { "mdma@0", ENC(0, 21), 0, input_port
, },
984 { "mdma@1", ENC(0, 22), 0, input_port
, },
985 { "wdog", ENC(0, 23), 0, input_port
, },
986 { "dmac@1_stat", ENC(0, 24), 0, input_port
, },
987 { "sport@2_stat", ENC(0, 25), 0, input_port
, },
988 { "sport@3_stat", ENC(0, 26), 0, input_port
, },
989 { "mxvr", ENC(0, 27), 0, input_port
, },
990 { "spi@1", ENC(0, 28), 0, input_port
, },
991 { "spi@2", ENC(0, 29), 0, input_port
, },
992 { "uart2@1_stat", ENC(0, 30), 0, input_port
, },
993 { "uart2@2_stat", ENC(0, 31), 0, input_port
, },
995 { "can@0_stat", ENC(1, 0), 0, input_port
, },
996 { "dma@18", ENC(1, 1), 0, input_port
, },
997 { "dma@19", ENC(1, 2), 0, input_port
, },
998 { "dma@20", ENC(1, 3), 0, input_port
, },
999 { "dma@21", ENC(1, 4), 0, input_port
, },
1000 { "dma@13", ENC(1, 5), 0, input_port
, },
1001 { "dma@14", ENC(1, 6), 0, input_port
, },
1002 { "dma@5", ENC(1, 7), 0, input_port
, },
1003 { "dma@23", ENC(1, 8), 0, input_port
, },
1004 { "dma@8", ENC(1, 9), 0, input_port
, },
1005 { "dma@9", ENC(1, 10), 0, input_port
, },
1006 { "dma@10", ENC(1, 11), 0, input_port
, },
1007 { "dma@11", ENC(1, 12), 0, input_port
, },
1008 { "twi@0", ENC(1, 13), 0, input_port
, },
1009 { "twi@1", ENC(1, 14), 0, input_port
, },
1010 { "can@0_rx", ENC(1, 15), 0, input_port
, },
1011 { "can@0_tx", ENC(1, 16), 0, input_port
, },
1012 { "mdma@2", ENC(1, 17), 0, input_port
, },
1013 { "mdma@3", ENC(1, 18), 0, input_port
, },
1014 { "mxvr_stat", ENC(1, 19), 0, input_port
, },
1015 { "mxvr_message", ENC(1, 20), 0, input_port
, },
1016 { "mxvr_packet", ENC(1, 21), 0, input_port
, },
1017 { "eppi@1", ENC(1, 22), 0, input_port
, },
1018 { "eppi@2", ENC(1, 23), 0, input_port
, },
1019 { "uart2@3_stat", ENC(1, 24), 0, input_port
, },
1020 { "hostdp", ENC(1, 25), 0, input_port
, },
1021 /*{ "reserved", ENC(1, 26), 0, input_port, },*/
1022 { "pixc_stat", ENC(1, 27), 0, input_port
, },
1023 { "nfc", ENC(1, 28), 0, input_port
, },
1024 { "atapi", ENC(1, 29), 0, input_port
, },
1025 { "can@1_stat", ENC(1, 30), 0, input_port
, },
1026 { "dmar", ENC(1, 31), 0, input_port
, },
1028 { "dma@15", ENC(2, 0), 0, input_port
, },
1029 { "dma@16", ENC(2, 1), 0, input_port
, },
1030 { "dma@17", ENC(2, 2), 0, input_port
, },
1031 { "dma@22", ENC(2, 3), 0, input_port
, },
1032 { "counter", ENC(2, 4), 0, input_port
, },
1033 { "key", ENC(2, 5), 0, input_port
, },
1034 { "can@1_rx", ENC(2, 6), 0, input_port
, },
1035 { "can@1_tx", ENC(2, 7), 0, input_port
, },
1036 { "sdh_mask0", ENC(2, 8), 0, input_port
, },
1037 { "sdh_mask1", ENC(2, 9), 0, input_port
, },
1038 /*{ "reserved", ENC(2, 10), 0, input_port, },*/
1039 { "usb_int0", ENC(2, 11), 0, input_port
, },
1040 { "usb_int1", ENC(2, 12), 0, input_port
, },
1041 { "usb_int2", ENC(2, 13), 0, input_port
, },
1042 { "usb_dma", ENC(2, 14), 0, input_port
, },
1043 { "otpsec", ENC(2, 15), 0, input_port
, },
1044 /*{ "reserved", ENC(2, 16), 0, input_port, },*/
1045 /*{ "reserved", ENC(2, 17), 0, input_port, },*/
1046 /*{ "reserved", ENC(2, 18), 0, input_port, },*/
1047 /*{ "reserved", ENC(2, 19), 0, input_port, },*/
1048 /*{ "reserved", ENC(2, 20), 0, input_port, },*/
1049 /*{ "reserved", ENC(2, 21), 0, input_port, },*/
1050 { "gptimer@0", ENC(2, 22), 0, input_port
, },
1051 { "gptimer@1", ENC(2, 23), 0, input_port
, },
1052 { "gptimer@2", ENC(2, 24), 0, input_port
, },
1053 { "gptimer@3", ENC(2, 25), 0, input_port
, },
1054 { "gptimer@4", ENC(2, 26), 0, input_port
, },
1055 { "gptimer@5", ENC(2, 27), 0, input_port
, },
1056 { "gptimer@6", ENC(2, 28), 0, input_port
, },
1057 { "gptimer@7", ENC(2, 29), 0, input_port
, },
1058 { "pint2", ENC(2, 30), 0, input_port
, },
1059 { "pint3", ENC(2, 31), 0, input_port
, },
1064 bfin_sic_54x_port_event (struct hw
*me
, int my_port
, struct hw
*source
,
1065 int source_port
, int level
)
1067 struct bfin_sic
*sic
= hw_data (me
);
1068 bu32 idx
= DEC_SIC (my_port
);
1069 bu32 pin
= DEC_PIN (my_port
);
1070 bu32 bit
= 1 << pin
;
1072 HW_TRACE ((me
, "processing system int from %i (SIC %u pin %u)",
1073 my_port
, idx
, pin
));
1075 /* SIC only exists to forward interrupts from the system to the CEC. */
1078 case 0: sic
->bf54x
.isr0
|= bit
; break;
1079 case 1: sic
->bf54x
.isr1
|= bit
; break;
1080 case 2: sic
->bf54x
.isr2
|= bit
; break;
1083 /* XXX: Handle SIC wakeup source ?
1084 if (sic->bf54x.iwr0 & bit)
1086 if (sic->bf54x.iwr1 & bit)
1088 if (sic->bf54x.iwr2 & bit)
1092 bfin_sic_54x_forward_interrupts (me
, sic
);
1095 static const struct hw_port_descriptor bfin_sic_561_ports
[] =
1097 BFIN_SIC_TO_CEC_PORTS
1099 { "pll", ENC(0, 0), 0, input_port
, },
1100 { "dmac@0_stat", ENC(0, 1), 0, input_port
, },
1101 { "dmac@1_stat", ENC(0, 2), 0, input_port
, },
1102 { "imdma_stat", ENC(0, 3), 0, input_port
, },
1103 { "ppi@0", ENC(0, 4), 0, input_port
, },
1104 { "ppi@1", ENC(0, 5), 0, input_port
, },
1105 { "sport@0_stat", ENC(0, 6), 0, input_port
, },
1106 { "sport@1_stat", ENC(0, 7), 0, input_port
, },
1107 { "spi@0", ENC(0, 8), 0, input_port
, },
1108 { "uart@0_stat", ENC(0, 9), 0, input_port
, },
1109 /*{ "reserved", ENC(0, 10), 0, input_port, },*/
1110 { "dma@12", ENC(0, 11), 0, input_port
, },
1111 { "dma@13", ENC(0, 12), 0, input_port
, },
1112 { "dma@14", ENC(0, 13), 0, input_port
, },
1113 { "dma@15", ENC(0, 14), 0, input_port
, },
1114 { "dma@16", ENC(0, 15), 0, input_port
, },
1115 { "dma@17", ENC(0, 16), 0, input_port
, },
1116 { "dma@18", ENC(0, 17), 0, input_port
, },
1117 { "dma@19", ENC(0, 18), 0, input_port
, },
1118 { "dma@20", ENC(0, 19), 0, input_port
, },
1119 { "dma@21", ENC(0, 20), 0, input_port
, },
1120 { "dma@22", ENC(0, 21), 0, input_port
, },
1121 { "dma@23", ENC(0, 22), 0, input_port
, },
1122 { "dma@0", ENC(0, 23), 0, input_port
, },
1123 { "dma@1", ENC(0, 24), 0, input_port
, },
1124 { "dma@2", ENC(0, 25), 0, input_port
, },
1125 { "dma@3", ENC(0, 26), 0, input_port
, },
1126 { "dma@4", ENC(0, 27), 0, input_port
, },
1127 { "dma@5", ENC(0, 28), 0, input_port
, },
1128 { "dma@6", ENC(0, 29), 0, input_port
, },
1129 { "dma@7", ENC(0, 30), 0, input_port
, },
1130 { "dma@8", ENC(0, 31), 0, input_port
, },
1132 { "dma@9", ENC(1, 0), 0, input_port
, },
1133 { "dma@10", ENC(1, 1), 0, input_port
, },
1134 { "dma@11", ENC(1, 2), 0, input_port
, },
1135 { "gptimer@0", ENC(1, 3), 0, input_port
, },
1136 { "gptimer@1", ENC(1, 4), 0, input_port
, },
1137 { "gptimer@2", ENC(1, 5), 0, input_port
, },
1138 { "gptimer@3", ENC(1, 6), 0, input_port
, },
1139 { "gptimer@4", ENC(1, 7), 0, input_port
, },
1140 { "gptimer@5", ENC(1, 8), 0, input_port
, },
1141 { "gptimer@6", ENC(1, 9), 0, input_port
, },
1142 { "gptimer@7", ENC(1, 10), 0, input_port
, },
1143 { "gptimer@8", ENC(1, 11), 0, input_port
, },
1144 { "gptimer@9", ENC(1, 12), 0, input_port
, },
1145 { "gptimer@10", ENC(1, 13), 0, input_port
, },
1146 { "gptimer@11", ENC(1, 14), 0, input_port
, },
1147 { "portf_irq_a", ENC(1, 15), 0, input_port
, },
1148 { "portf_irq_b", ENC(1, 16), 0, input_port
, },
1149 { "portg_irq_a", ENC(1, 17), 0, input_port
, },
1150 { "portg_irq_b", ENC(1, 18), 0, input_port
, },
1151 { "porth_irq_a", ENC(1, 19), 0, input_port
, },
1152 { "porth_irq_b", ENC(1, 20), 0, input_port
, },
1153 { "mdma@0", ENC(1, 21), 0, input_port
, },
1154 { "mdma@1", ENC(1, 22), 0, input_port
, },
1155 { "mdma@2", ENC(1, 23), 0, input_port
, },
1156 { "mdma@3", ENC(1, 24), 0, input_port
, },
1157 { "imdma@0", ENC(1, 25), 0, input_port
, },
1158 { "imdma@1", ENC(1, 26), 0, input_port
, },
1159 { "wdog", ENC(1, 27), 0, input_port
, },
1160 /*{ "reserved", ENC(1, 28), 0, input_port, },*/
1161 /*{ "reserved", ENC(1, 29), 0, input_port, },*/
1162 { "sup_irq_0", ENC(1, 30), 0, input_port
, },
1163 { "sup_irq_1", ENC(1, 31), 0, input_port
, },
1168 bfin_sic_561_port_event (struct hw
*me
, int my_port
, struct hw
*source
,
1169 int source_port
, int level
)
1171 struct bfin_sic
*sic
= hw_data (me
);
1172 bu32 idx
= DEC_SIC (my_port
);
1173 bu32 pin
= DEC_PIN (my_port
);
1174 bu32 bit
= 1 << pin
;
1176 HW_TRACE ((me
, "processing system int from %i (SIC %u pin %u)",
1177 my_port
, idx
, pin
));
1179 /* SIC only exists to forward interrupts from the system to the CEC. */
1182 case 0: sic
->bf561
.isr0
|= bit
; break;
1183 case 1: sic
->bf561
.isr1
|= bit
; break;
1186 /* XXX: Handle SIC wakeup source ?
1187 if (sic->bf561.iwr0 & bit)
1189 if (sic->bf561.iwr1 & bit)
1193 bfin_sic_561_forward_interrupts (me
, sic
);
1196 static const struct hw_port_descriptor bfin_sic_59x_ports
[] =
1198 BFIN_SIC_TO_CEC_PORTS
1199 { "pll", ENC(0, 0), 0, input_port
, },
1200 { "dma_stat", ENC(0, 1), 0, input_port
, },
1201 { "ppi@0", ENC(0, 2), 0, input_port
, },
1202 { "sport@0_stat", ENC(0, 3), 0, input_port
, },
1203 { "sport@1_stat", ENC(0, 4), 0, input_port
, },
1204 { "spi@0", ENC(0, 5), 0, input_port
, },
1205 { "spi@1", ENC(0, 6), 0, input_port
, },
1206 { "uart@0_stat", ENC(0, 7), 0, input_port
, },
1207 { "dma@0", ENC(0, 8), 0, input_port
, },
1208 { "dma@1", ENC(0, 9), 0, input_port
, },
1209 { "dma@2", ENC(0, 10), 0, input_port
, },
1210 { "dma@3", ENC(0, 11), 0, input_port
, },
1211 { "dma@4", ENC(0, 12), 0, input_port
, },
1212 { "dma@5", ENC(0, 13), 0, input_port
, },
1213 { "dma@6", ENC(0, 14), 0, input_port
, },
1214 { "dma@7", ENC(0, 15), 0, input_port
, },
1215 { "dma@8", ENC(0, 16), 0, input_port
, },
1216 { "portf_irq_a", ENC(0, 17), 0, input_port
, },
1217 { "portf_irq_b", ENC(0, 18), 0, input_port
, },
1218 { "gptimer@0", ENC(0, 19), 0, input_port
, },
1219 { "gptimer@1", ENC(0, 20), 0, input_port
, },
1220 { "gptimer@2", ENC(0, 21), 0, input_port
, },
1221 { "portg_irq_a", ENC(0, 22), 0, input_port
, },
1222 { "portg_irq_b", ENC(0, 23), 0, input_port
, },
1223 { "twi@0", ENC(0, 24), 0, input_port
, },
1224 /* XXX: 25 - 28 are supposed to be reserved; see comment in machs.c:bf592_dmac[] */
1225 { "dma@9", ENC(0, 25), 0, input_port
, },
1226 { "dma@10", ENC(0, 26), 0, input_port
, },
1227 { "dma@11", ENC(0, 27), 0, input_port
, },
1228 { "dma@12", ENC(0, 28), 0, input_port
, },
1229 /*{ "reserved", ENC(0, 25), 0, input_port, },*/
1230 /*{ "reserved", ENC(0, 26), 0, input_port, },*/
1231 /*{ "reserved", ENC(0, 27), 0, input_port, },*/
1232 /*{ "reserved", ENC(0, 28), 0, input_port, },*/
1233 { "mdma@0", ENC(0, 29), 0, input_port
, },
1234 { "mdma@1", ENC(0, 30), 0, input_port
, },
1235 { "wdog", ENC(0, 31), 0, input_port
, },
1240 attach_bfin_sic_regs (struct hw
*me
, struct bfin_sic
*sic
)
1242 address_word attach_address
;
1244 unsigned attach_size
;
1245 reg_property_spec reg
;
1247 if (hw_find_property (me
, "reg") == NULL
)
1248 hw_abort (me
, "Missing \"reg\" property");
1250 if (!hw_find_reg_array_property (me
, "reg", 0, ®
))
1251 hw_abort (me
, "\"reg\" property must contain three addr/size entries");
1253 hw_unit_address_to_attach_address (hw_parent (me
),
1255 &attach_space
, &attach_address
, me
);
1256 hw_unit_size_to_attach_size (hw_parent (me
), ®
.size
, &attach_size
, me
);
1258 if (attach_size
!= BFIN_MMR_SIC_SIZE
)
1259 hw_abort (me
, "\"reg\" size must be %#x", BFIN_MMR_SIC_SIZE
);
1261 hw_attach_address (hw_parent (me
),
1262 0, attach_space
, attach_address
, attach_size
, me
);
1264 sic
->base
= attach_address
;
1268 bfin_sic_finish (struct hw
*me
)
1270 struct bfin_sic
*sic
;
1272 sic
= HW_ZALLOC (me
, struct bfin_sic
);
1274 set_hw_data (me
, sic
);
1275 attach_bfin_sic_regs (me
, sic
);
1277 switch (hw_find_integer_property (me
, "type"))
1280 set_hw_io_read_buffer (me
, bfin_sic_52x_io_read_buffer
);
1281 set_hw_io_write_buffer (me
, bfin_sic_52x_io_write_buffer
);
1282 set_hw_ports (me
, bfin_sic_50x_ports
);
1283 set_hw_port_event (me
, bfin_sic_52x_port_event
);
1284 mmr_names
= bf52x_mmr_names
;
1286 /* Initialize the SIC. */
1287 sic
->bf52x
.imask0
= sic
->bf52x
.imask1
= 0;
1288 sic
->bf52x
.isr0
= sic
->bf52x
.isr1
= 0;
1289 sic
->bf52x
.iwr0
= sic
->bf52x
.iwr1
= 0xFFFFFFFF;
1290 sic
->bf52x
.iar0
= 0x00000000;
1291 sic
->bf52x
.iar1
= 0x22111000;
1292 sic
->bf52x
.iar2
= 0x33332222;
1293 sic
->bf52x
.iar3
= 0x44444433;
1294 sic
->bf52x
.iar4
= 0x55555555;
1295 sic
->bf52x
.iar5
= 0x06666655;
1296 sic
->bf52x
.iar6
= 0x33333003;
1297 sic
->bf52x
.iar7
= 0x00000000; /* XXX: Find and fix */
1300 set_hw_io_read_buffer (me
, bfin_sic_52x_io_read_buffer
);
1301 set_hw_io_write_buffer (me
, bfin_sic_52x_io_write_buffer
);
1302 set_hw_ports (me
, bfin_sic_51x_ports
);
1303 set_hw_port_event (me
, bfin_sic_52x_port_event
);
1304 mmr_names
= bf52x_mmr_names
;
1306 /* Initialize the SIC. */
1307 sic
->bf52x
.imask0
= sic
->bf52x
.imask1
= 0;
1308 sic
->bf52x
.isr0
= sic
->bf52x
.isr1
= 0;
1309 sic
->bf52x
.iwr0
= sic
->bf52x
.iwr1
= 0xFFFFFFFF;
1310 sic
->bf52x
.iar0
= 0x00000000;
1311 sic
->bf52x
.iar1
= 0x11000000;
1312 sic
->bf52x
.iar2
= 0x33332222;
1313 sic
->bf52x
.iar3
= 0x44444433;
1314 sic
->bf52x
.iar4
= 0x55555555;
1315 sic
->bf52x
.iar5
= 0x06666655;
1316 sic
->bf52x
.iar6
= 0x33333000;
1317 sic
->bf52x
.iar7
= 0x00000000; /* XXX: Find and fix */
1320 set_hw_io_read_buffer (me
, bfin_sic_52x_io_read_buffer
);
1321 set_hw_io_write_buffer (me
, bfin_sic_52x_io_write_buffer
);
1322 set_hw_ports (me
, bfin_sic_52x_ports
);
1323 set_hw_port_event (me
, bfin_sic_52x_port_event
);
1324 mmr_names
= bf52x_mmr_names
;
1326 /* Initialize the SIC. */
1327 sic
->bf52x
.imask0
= sic
->bf52x
.imask1
= 0;
1328 sic
->bf52x
.isr0
= sic
->bf52x
.isr1
= 0;
1329 sic
->bf52x
.iwr0
= sic
->bf52x
.iwr1
= 0xFFFFFFFF;
1330 sic
->bf52x
.iar0
= 0x00000000;
1331 sic
->bf52x
.iar1
= 0x11000000;
1332 sic
->bf52x
.iar2
= 0x33332222;
1333 sic
->bf52x
.iar3
= 0x44444433;
1334 sic
->bf52x
.iar4
= 0x55555555;
1335 sic
->bf52x
.iar5
= 0x06666655;
1336 sic
->bf52x
.iar6
= 0x33333000;
1337 sic
->bf52x
.iar7
= 0x00000000; /* XXX: Find and fix */
1340 set_hw_io_read_buffer (me
, bfin_sic_537_io_read_buffer
);
1341 set_hw_io_write_buffer (me
, bfin_sic_537_io_write_buffer
);
1342 set_hw_ports (me
, bfin_sic_533_ports
);
1343 set_hw_port_event (me
, bfin_sic_537_port_event
);
1344 mmr_names
= bf537_mmr_names
;
1346 /* Initialize the SIC. */
1347 sic
->bf537
.imask
= 0;
1349 sic
->bf537
.iwr
= 0xFFFFFFFF;
1350 sic
->bf537
.iar0
= 0x10000000;
1351 sic
->bf537
.iar1
= 0x33322221;
1352 sic
->bf537
.iar2
= 0x66655444;
1353 sic
->bf537
.iar3
= 0; /* XXX: fix this */
1358 set_hw_io_read_buffer (me
, bfin_sic_537_io_read_buffer
);
1359 set_hw_io_write_buffer (me
, bfin_sic_537_io_write_buffer
);
1360 set_hw_ports (me
, bfin_sic_537_ports
);
1361 set_hw_port_event (me
, bfin_sic_537_port_event
);
1362 mmr_names
= bf537_mmr_names
;
1364 /* Initialize the SIC. */
1365 sic
->bf537
.imask
= 0;
1367 sic
->bf537
.iwr
= 0xFFFFFFFF;
1368 sic
->bf537
.iar0
= 0x22211000;
1369 sic
->bf537
.iar1
= 0x43333332;
1370 sic
->bf537
.iar2
= 0x55555444;
1371 sic
->bf537
.iar3
= 0x66655555;
1374 set_hw_io_read_buffer (me
, bfin_sic_52x_io_read_buffer
);
1375 set_hw_io_write_buffer (me
, bfin_sic_52x_io_write_buffer
);
1376 set_hw_ports (me
, bfin_sic_538_ports
);
1377 set_hw_port_event (me
, bfin_sic_52x_port_event
);
1378 mmr_names
= bf52x_mmr_names
;
1380 /* Initialize the SIC. */
1381 sic
->bf52x
.imask0
= sic
->bf52x
.imask1
= 0;
1382 sic
->bf52x
.isr0
= sic
->bf52x
.isr1
= 0;
1383 sic
->bf52x
.iwr0
= sic
->bf52x
.iwr1
= 0xFFFFFFFF;
1384 sic
->bf52x
.iar0
= 0x10000000;
1385 sic
->bf52x
.iar1
= 0x33322221;
1386 sic
->bf52x
.iar2
= 0x66655444;
1387 sic
->bf52x
.iar3
= 0x00000000;
1388 sic
->bf52x
.iar4
= 0x32222220;
1389 sic
->bf52x
.iar5
= 0x44433333;
1390 sic
->bf52x
.iar6
= 0x00444664;
1391 sic
->bf52x
.iar7
= 0x00000000; /* XXX: Find and fix */
1394 set_hw_io_read_buffer (me
, bfin_sic_54x_io_read_buffer
);
1395 set_hw_io_write_buffer (me
, bfin_sic_54x_io_write_buffer
);
1396 set_hw_ports (me
, bfin_sic_54x_ports
);
1397 set_hw_port_event (me
, bfin_sic_54x_port_event
);
1398 mmr_names
= bf54x_mmr_names
;
1400 /* Initialize the SIC. */
1401 sic
->bf54x
.imask0
= sic
->bf54x
.imask1
= sic
->bf54x
.imask2
= 0;
1402 sic
->bf54x
.isr0
= sic
->bf54x
.isr1
= sic
->bf54x
.isr2
= 0;
1403 sic
->bf54x
.iwr0
= sic
->bf54x
.iwr1
= sic
->bf54x
.iwr1
= 0xFFFFFFFF;
1404 sic
->bf54x
.iar0
= 0x10000000;
1405 sic
->bf54x
.iar1
= 0x33322221;
1406 sic
->bf54x
.iar2
= 0x66655444;
1407 sic
->bf54x
.iar3
= 0x00000000;
1408 sic
->bf54x
.iar4
= 0x32222220;
1409 sic
->bf54x
.iar5
= 0x44433333;
1410 sic
->bf54x
.iar6
= 0x00444664;
1411 sic
->bf54x
.iar7
= 0x00000000;
1412 sic
->bf54x
.iar8
= 0x44111111;
1413 sic
->bf54x
.iar9
= 0x44444444;
1414 sic
->bf54x
.iar10
= 0x44444444;
1415 sic
->bf54x
.iar11
= 0x55444444;
1418 set_hw_io_read_buffer (me
, bfin_sic_561_io_read_buffer
);
1419 set_hw_io_write_buffer (me
, bfin_sic_561_io_write_buffer
);
1420 set_hw_ports (me
, bfin_sic_561_ports
);
1421 set_hw_port_event (me
, bfin_sic_561_port_event
);
1422 mmr_names
= bf561_mmr_names
;
1424 /* Initialize the SIC. */
1425 sic
->bf561
.imask0
= sic
->bf561
.imask1
= 0;
1426 sic
->bf561
.isr0
= sic
->bf561
.isr1
= 0;
1427 sic
->bf561
.iwr0
= sic
->bf561
.iwr1
= 0xFFFFFFFF;
1428 sic
->bf561
.iar0
= 0x00000000;
1429 sic
->bf561
.iar1
= 0x11111000;
1430 sic
->bf561
.iar2
= 0x21111111;
1431 sic
->bf561
.iar3
= 0x22222222;
1432 sic
->bf561
.iar4
= 0x33333222;
1433 sic
->bf561
.iar5
= 0x43333333;
1434 sic
->bf561
.iar6
= 0x21144444;
1435 sic
->bf561
.iar7
= 0x00006552;
1438 set_hw_io_read_buffer (me
, bfin_sic_537_io_read_buffer
);
1439 set_hw_io_write_buffer (me
, bfin_sic_537_io_write_buffer
);
1440 set_hw_ports (me
, bfin_sic_59x_ports
);
1441 set_hw_port_event (me
, bfin_sic_537_port_event
);
1442 mmr_names
= bf537_mmr_names
;
1444 /* Initialize the SIC. */
1445 sic
->bf537
.imask
= 0;
1447 sic
->bf537
.iwr
= 0xFFFFFFFF;
1448 sic
->bf537
.iar0
= 0x00000000;
1449 sic
->bf537
.iar1
= 0x33322221;
1450 sic
->bf537
.iar2
= 0x55444443;
1451 sic
->bf537
.iar3
= 0x66600005;
1454 hw_abort (me
, "no support for SIC on this Blackfin model yet");
1458 const struct hw_descriptor dv_bfin_sic_descriptor
[] =
1460 {"bfin_sic", bfin_sic_finish
,},