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sim: bfin: move option inits to respective modules
[binutils-gdb.git] / sim / bfin / machs.c
1 /* Simulator for Analog Devices Blackfin processors.
2
3 Copyright (C) 2005-2021 Free Software Foundation, Inc.
4 Contributed by Analog Devices, Inc. and Mike Frysinger.
5
6 This file is part of simulators.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21 #include "config.h"
22
23 #include <stdlib.h>
24
25 #include "sim-main.h"
26 #include "gdb/sim-bfin.h"
27 #include "bfd.h"
28
29 #include "sim-hw.h"
30 #include "devices.h"
31 #include "dv-bfin_cec.h"
32 #include "dv-bfin_dmac.h"
33
34 static const SIM_MACH bfin_mach;
35
36 struct bfin_memory_layout {
37 address_word addr, len;
38 unsigned mask; /* see mapmask in sim_core_attach() */
39 };
40 struct bfin_dev_layout {
41 address_word base, len;
42 unsigned int dmac;
43 const char *dev;
44 };
45 struct bfin_dmac_layout {
46 address_word base;
47 unsigned int dma_count;
48 };
49 struct bfin_port_layout {
50 /* Which device this routes to (name/port). */
51 const char *dst, *dst_port;
52 /* Which device this routes from (name/port). */
53 const char *src, *src_port;
54 };
55 struct bfin_model_data {
56 bu32 chipid;
57 int model_num;
58 const struct bfin_memory_layout *mem;
59 size_t mem_count;
60 const struct bfin_dev_layout *dev;
61 size_t dev_count;
62 const struct bfin_dmac_layout *dmac;
63 size_t dmac_count;
64 const struct bfin_port_layout *port;
65 size_t port_count;
66 };
67
68 #define LAYOUT(_addr, _len, _mask) { .addr = _addr, .len = _len, .mask = access_##_mask, }
69 #define _DEVICE(_base, _len, _dev, _dmac) { .base = _base, .len = _len, .dev = _dev, .dmac = _dmac, }
70 #define DEVICE(_base, _len, _dev) _DEVICE(_base, _len, _dev, 0)
71 #define PORT(_dst, _dst_port, _src, _src_port) \
72 { \
73 .dst = _dst, \
74 .dst_port = _dst_port, \
75 .src = _src, \
76 .src_port = _src_port, \
77 }
78 #define SIC(_s, _ip, _d, _op) PORT("bfin_sic", "int"#_ip"@"#_s, _d, _op)
79
80 /* [1] Common sim code can't model exec-only memory.
81 http://sourceware.org/ml/gdb/2010-02/msg00047.html */
82
83 #define bf000_chipid 0
84 static const struct bfin_memory_layout bf000_mem[] = {};
85 static const struct bfin_dev_layout bf000_dev[] = {};
86 static const struct bfin_dmac_layout bf000_dmac[] = {};
87 static const struct bfin_port_layout bf000_port[] = {};
88
89 #define bf50x_chipid 0x2800
90 #define bf504_chipid bf50x_chipid
91 #define bf506_chipid bf50x_chipid
92 static const struct bfin_memory_layout bf50x_mem[] =
93 {
94 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
95 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
96 LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
97 LAYOUT (0xFFC03800, 0x100, read_write), /* RSI stub */
98 LAYOUT (0xFFC0328C, 0xC, read_write), /* Flash stub */
99 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
100 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
101 LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */
102 LAYOUT (0xFFA04000, 0x4000, read_write_exec), /* Inst Cache [1] */
103 };
104 #define bf504_mem bf50x_mem
105 #define bf506_mem bf50x_mem
106 static const struct bfin_dev_layout bf50x_dev[] =
107 {
108 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
109 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
110 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
111 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
112 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
113 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
114 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
115 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
116 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
117 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
118 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
119 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
120 DEVICE (0xFFC00A00, BF50X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
121 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
122 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
123 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
124 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
125 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
126 DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
127 };
128 #define bf504_dev bf50x_dev
129 #define bf506_dev bf50x_dev
130 static const struct bfin_dmac_layout bf50x_dmac[] =
131 {
132 { BFIN_MMR_DMAC0_BASE, 12, },
133 };
134 #define bf504_dmac bf50x_dmac
135 #define bf506_dmac bf50x_dmac
136 static const struct bfin_port_layout bf50x_port[] =
137 {
138 SIC (0, 0, "bfin_pll", "pll"),
139 /*SIC (0, 1, "bfin_dmac@0", "stat"),*/
140 SIC (0, 2, "bfin_ppi@0", "stat"),
141 SIC (0, 3, "bfin_sport@0", "stat"),
142 SIC (0, 4, "bfin_sport@1", "stat"),
143 SIC (0, 5, "bfin_uart2@0", "stat"),
144 SIC (0, 6, "bfin_uart2@1", "stat"),
145 SIC (0, 7, "bfin_spi@0", "stat"),
146 SIC (0, 8, "bfin_spi@1", "stat"),
147 SIC (0, 9, "bfin_can@0", "stat"),
148 SIC (0, 10, "bfin_rsi@0", "int0"),
149 /*SIC (0, 11, reserved),*/
150 SIC (0, 12, "bfin_counter@0", "stat"),
151 SIC (0, 13, "bfin_counter@1", "stat"),
152 SIC (0, 14, "bfin_dma@0", "di"),
153 SIC (0, 15, "bfin_dma@1", "di"),
154 SIC (0, 16, "bfin_dma@2", "di"),
155 SIC (0, 17, "bfin_dma@3", "di"),
156 SIC (0, 18, "bfin_dma@4", "di"),
157 SIC (0, 19, "bfin_dma@5", "di"),
158 SIC (0, 20, "bfin_dma@6", "di"),
159 SIC (0, 21, "bfin_dma@7", "di"),
160 SIC (0, 22, "bfin_dma@8", "di"),
161 SIC (0, 23, "bfin_dma@9", "di"),
162 SIC (0, 24, "bfin_dma@10", "di"),
163 SIC (0, 25, "bfin_dma@11", "di"),
164 SIC (0, 26, "bfin_can@0", "rx"),
165 SIC (0, 27, "bfin_can@0", "tx"),
166 SIC (0, 28, "bfin_twi@0", "stat"),
167 SIC (0, 29, "bfin_gpio@5", "mask_a"),
168 SIC (0, 30, "bfin_gpio@5", "mask_b"),
169 /*SIC (0, 31, reserved),*/
170 SIC (1, 0, "bfin_gptimer@0", "stat"),
171 SIC (1, 1, "bfin_gptimer@1", "stat"),
172 SIC (1, 2, "bfin_gptimer@2", "stat"),
173 SIC (1, 3, "bfin_gptimer@3", "stat"),
174 SIC (1, 4, "bfin_gptimer@4", "stat"),
175 SIC (1, 5, "bfin_gptimer@5", "stat"),
176 SIC (1, 6, "bfin_gptimer@6", "stat"),
177 SIC (1, 7, "bfin_gptimer@7", "stat"),
178 SIC (1, 8, "bfin_gpio@6", "mask_a"),
179 SIC (1, 9, "bfin_gpio@6", "mask_b"),
180 SIC (1, 10, "bfin_dma@256", "di"), /* mdma0 */
181 SIC (1, 10, "bfin_dma@257", "di"), /* mdma0 */
182 SIC (1, 11, "bfin_dma@258", "di"), /* mdma1 */
183 SIC (1, 11, "bfin_dma@259", "di"), /* mdma1 */
184 SIC (1, 12, "bfin_wdog@0", "gpi"),
185 SIC (1, 13, "bfin_gpio@7", "mask_a"),
186 SIC (1, 14, "bfin_gpio@7", "mask_b"),
187 SIC (1, 15, "bfin_acm@0", "stat"),
188 SIC (1, 16, "bfin_acm@1", "int"),
189 /*SIC (1, 17, reserved),*/
190 /*SIC (1, 18, reserved),*/
191 SIC (1, 19, "bfin_pwm@0", "trip"),
192 SIC (1, 20, "bfin_pwm@0", "sync"),
193 SIC (1, 21, "bfin_pwm@1", "trip"),
194 SIC (1, 22, "bfin_pwm@1", "sync"),
195 SIC (1, 23, "bfin_rsi@0", "int1"),
196 };
197 #define bf504_port bf50x_port
198 #define bf506_port bf50x_port
199
200 #define bf51x_chipid 0x27e8
201 #define bf512_chipid bf51x_chipid
202 #define bf514_chipid bf51x_chipid
203 #define bf516_chipid bf51x_chipid
204 #define bf518_chipid bf51x_chipid
205 static const struct bfin_memory_layout bf51x_mem[] =
206 {
207 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
208 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
209 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
210 LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
211 LAYOUT (0xFFC03800, 0xD0, read_write), /* RSI stub */
212 LAYOUT (0xFFC03FE0, 0x20, read_write), /* RSI peripheral stub */
213 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
214 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
215 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
216 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
217 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
218 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
219 };
220 #define bf512_mem bf51x_mem
221 #define bf514_mem bf51x_mem
222 #define bf516_mem bf51x_mem
223 #define bf518_mem bf51x_mem
224 static const struct bfin_dev_layout bf512_dev[] =
225 {
226 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
227 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
228 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
229 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
230 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
231 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
232 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
233 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
234 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
235 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
236 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
237 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
238 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
239 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
240 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
241 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
242 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
243 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
244 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
245 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
246 DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
247 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
248 };
249 #define bf514_dev bf512_dev
250 static const struct bfin_dev_layout bf516_dev[] =
251 {
252 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
253 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
254 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
255 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
256 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
257 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
258 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
259 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
260 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
261 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
262 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
263 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
264 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
265 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
266 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
267 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
268 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
269 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
270 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
271 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
272 DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
273 DEVICE (0, 0x20, "bfin_emac/eth_phy"),
274 DEVICE (0xFFC03400, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
275 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
276 };
277 #define bf518_dev bf516_dev
278 #define bf512_dmac bf50x_dmac
279 #define bf514_dmac bf50x_dmac
280 #define bf516_dmac bf50x_dmac
281 #define bf518_dmac bf50x_dmac
282 static const struct bfin_port_layout bf51x_port[] =
283 {
284 SIC (0, 0, "bfin_pll", "pll"),
285 /*SIC (0, 1, "bfin_dmac@0", "stat"),*/
286 SIC (0, 2, "bfin_dmar@0", "block"),
287 SIC (0, 3, "bfin_dmar@1", "block"),
288 SIC (0, 4, "bfin_dmar@0", "overflow"),
289 SIC (0, 5, "bfin_dmar@1", "overflow"),
290 SIC (0, 6, "bfin_ppi@0", "stat"),
291 SIC (0, 7, "bfin_emac", "stat"),
292 SIC (0, 8, "bfin_sport@0", "stat"),
293 SIC (0, 9, "bfin_sport@1", "stat"),
294 SIC (0, 10, "bfin_ptp", "stat"),
295 /*SIC (0, 11, reserved),*/
296 SIC (0, 12, "bfin_uart@0", "stat"),
297 SIC (0, 13, "bfin_uart@1", "stat"),
298 SIC (0, 14, "bfin_rtc", "rtc"),
299 SIC (0, 15, "bfin_dma@0", "di"),
300 SIC (0, 16, "bfin_dma@3", "di"),
301 SIC (0, 17, "bfin_dma@4", "di"),
302 SIC (0, 18, "bfin_dma@5", "di"),
303 SIC (0, 19, "bfin_dma@6", "di"),
304 SIC (0, 20, "bfin_twi@0", "stat"),
305 SIC (0, 21, "bfin_dma@7", "di"),
306 SIC (0, 22, "bfin_dma@8", "di"),
307 SIC (0, 23, "bfin_dma@9", "di"),
308 SIC (0, 24, "bfin_dma@10", "di"),
309 SIC (0, 25, "bfin_dma@11", "di"),
310 SIC (0, 26, "bfin_otp", "stat"),
311 SIC (0, 27, "bfin_counter@0", "stat"),
312 SIC (0, 28, "bfin_dma@1", "di"),
313 SIC (0, 29, "bfin_gpio@7", "mask_a"),
314 SIC (0, 30, "bfin_dma@2", "di"),
315 SIC (0, 31, "bfin_gpio@7", "mask_b"),
316 SIC (1, 0, "bfin_gptimer@0", "stat"),
317 SIC (1, 1, "bfin_gptimer@1", "stat"),
318 SIC (1, 2, "bfin_gptimer@2", "stat"),
319 SIC (1, 3, "bfin_gptimer@3", "stat"),
320 SIC (1, 4, "bfin_gptimer@4", "stat"),
321 SIC (1, 5, "bfin_gptimer@5", "stat"),
322 SIC (1, 6, "bfin_gptimer@6", "stat"),
323 SIC (1, 7, "bfin_gptimer@7", "stat"),
324 SIC (1, 8, "bfin_gpio@6", "mask_a"),
325 SIC (1, 9, "bfin_gpio@6", "mask_b"),
326 SIC (1, 10, "bfin_dma@256", "di"), /* mdma0 */
327 SIC (1, 10, "bfin_dma@257", "di"), /* mdma0 */
328 SIC (1, 11, "bfin_dma@258", "di"), /* mdma1 */
329 SIC (1, 11, "bfin_dma@259", "di"), /* mdma1 */
330 SIC (1, 12, "bfin_wdog@0", "gpi"),
331 SIC (1, 13, "bfin_gpio@5", "mask_a"),
332 SIC (1, 14, "bfin_gpio@5", "mask_b"),
333 SIC (1, 15, "bfin_spi@0", "stat"),
334 SIC (1, 16, "bfin_spi@1", "stat"),
335 /*SIC (1, 17, reserved),*/
336 /*SIC (1, 18, reserved),*/
337 SIC (1, 19, "bfin_rsi@0", "int0"),
338 SIC (1, 20, "bfin_rsi@0", "int1"),
339 SIC (1, 21, "bfin_pwm@0", "trip"),
340 SIC (1, 22, "bfin_pwm@0", "sync"),
341 SIC (1, 23, "bfin_ptp", "stat"),
342 };
343 #define bf512_port bf51x_port
344 #define bf514_port bf51x_port
345 #define bf516_port bf51x_port
346 #define bf518_port bf51x_port
347
348 #define bf522_chipid 0x27e4
349 #define bf523_chipid 0x27e0
350 #define bf524_chipid bf522_chipid
351 #define bf525_chipid bf523_chipid
352 #define bf526_chipid bf522_chipid
353 #define bf527_chipid bf523_chipid
354 static const struct bfin_memory_layout bf52x_mem[] =
355 {
356 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
357 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
358 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
359 LAYOUT (0xFFC03200, 0x50, read_write), /* PORT_MUX stub */
360 LAYOUT (0xFFC03800, 0x500, read_write), /* MUSB stub */
361 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
362 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
363 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
364 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
365 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
366 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
367 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
368 };
369 #define bf522_mem bf52x_mem
370 #define bf523_mem bf52x_mem
371 #define bf524_mem bf52x_mem
372 #define bf525_mem bf52x_mem
373 #define bf526_mem bf52x_mem
374 #define bf527_mem bf52x_mem
375 static const struct bfin_dev_layout bf522_dev[] =
376 {
377 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
378 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
379 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
380 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
381 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
382 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
383 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
384 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
385 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
386 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
387 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
388 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
389 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
390 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
391 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
392 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
393 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
394 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
395 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
396 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
397 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
398 DEVICE (0xFFC03700, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
399 };
400 #define bf523_dev bf522_dev
401 #define bf524_dev bf522_dev
402 #define bf525_dev bf522_dev
403 static const struct bfin_dev_layout bf526_dev[] =
404 {
405 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
406 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
407 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
408 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
409 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
410 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
411 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
412 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
413 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
414 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
415 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
416 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
417 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
418 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
419 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
420 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
421 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
422 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
423 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
424 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
425 DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
426 DEVICE (0, 0x20, "bfin_emac/eth_phy"),
427 DEVICE (0xFFC03600, BFIN_MMR_OTP_SIZE, "bfin_otp"),
428 DEVICE (0xFFC03700, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
429 };
430 #define bf527_dev bf526_dev
431 #define bf522_dmac bf50x_dmac
432 #define bf523_dmac bf50x_dmac
433 #define bf524_dmac bf50x_dmac
434 #define bf525_dmac bf50x_dmac
435 #define bf526_dmac bf50x_dmac
436 #define bf527_dmac bf50x_dmac
437 static const struct bfin_port_layout bf52x_port[] =
438 {
439 SIC (0, 0, "bfin_pll", "pll"),
440 /*SIC (0, 1, "bfin_dmac@0", "stat"),*/
441 SIC (0, 2, "bfin_dmar@0", "block"),
442 SIC (0, 3, "bfin_dmar@1", "block"),
443 SIC (0, 4, "bfin_dmar@0", "overflow"),
444 SIC (0, 5, "bfin_dmar@1", "overflow"),
445 SIC (0, 6, "bfin_ppi@0", "stat"),
446 SIC (0, 7, "bfin_emac", "stat"),
447 SIC (0, 8, "bfin_sport@0", "stat"),
448 SIC (0, 9, "bfin_sport@1", "stat"),
449 /*SIC (0, 10, reserved),*/
450 /*SIC (0, 11, reserved),*/
451 SIC (0, 12, "bfin_uart@0", "stat"),
452 SIC (0, 13, "bfin_uart@1", "stat"),
453 SIC (0, 14, "bfin_rtc", "rtc"),
454 SIC (0, 15, "bfin_dma@0", "di"),
455 SIC (0, 16, "bfin_dma@3", "di"),
456 SIC (0, 17, "bfin_dma@4", "di"),
457 SIC (0, 18, "bfin_dma@5", "di"),
458 SIC (0, 19, "bfin_dma@6", "di"),
459 SIC (0, 20, "bfin_twi@0", "stat"),
460 SIC (0, 21, "bfin_dma@7", "di"),
461 SIC (0, 22, "bfin_dma@8", "di"),
462 SIC (0, 23, "bfin_dma@9", "di"),
463 SIC (0, 24, "bfin_dma@10", "di"),
464 SIC (0, 25, "bfin_dma@11", "di"),
465 SIC (0, 26, "bfin_otp", "stat"),
466 SIC (0, 27, "bfin_counter@0", "stat"),
467 SIC (0, 28, "bfin_dma@1", "di"),
468 SIC (0, 29, "bfin_gpio@7", "mask_a"),
469 SIC (0, 30, "bfin_dma@2", "di"),
470 SIC (0, 31, "bfin_gpio@7", "mask_b"),
471 SIC (1, 0, "bfin_gptimer@0", "stat"),
472 SIC (1, 1, "bfin_gptimer@1", "stat"),
473 SIC (1, 2, "bfin_gptimer@2", "stat"),
474 SIC (1, 3, "bfin_gptimer@3", "stat"),
475 SIC (1, 4, "bfin_gptimer@4", "stat"),
476 SIC (1, 5, "bfin_gptimer@5", "stat"),
477 SIC (1, 6, "bfin_gptimer@6", "stat"),
478 SIC (1, 7, "bfin_gptimer@7", "stat"),
479 SIC (1, 8, "bfin_gpio@6", "mask_a"),
480 SIC (1, 9, "bfin_gpio@6", "mask_b"),
481 SIC (1, 10, "bfin_dma@256", "di"), /* mdma0 */
482 SIC (1, 10, "bfin_dma@257", "di"), /* mdma0 */
483 SIC (1, 11, "bfin_dma@258", "di"), /* mdma1 */
484 SIC (1, 11, "bfin_dma@259", "di"), /* mdma1 */
485 SIC (1, 12, "bfin_wdog@0", "gpi"),
486 SIC (1, 13, "bfin_gpio@5", "mask_a"),
487 SIC (1, 14, "bfin_gpio@5", "mask_b"),
488 SIC (1, 15, "bfin_spi@0", "stat"),
489 SIC (1, 16, "bfin_nfc", "stat"),
490 SIC (1, 17, "bfin_hostdp", "stat"),
491 SIC (1, 18, "bfin_hostdp", "done"),
492 SIC (1, 20, "bfin_usb", "int0"),
493 SIC (1, 21, "bfin_usb", "int1"),
494 SIC (1, 22, "bfin_usb", "int2"),
495 };
496 #define bf522_port bf51x_port
497 #define bf523_port bf51x_port
498 #define bf524_port bf51x_port
499 #define bf525_port bf51x_port
500 #define bf526_port bf51x_port
501 #define bf527_port bf51x_port
502
503 #define bf531_chipid 0x27a5
504 #define bf532_chipid bf531_chipid
505 #define bf533_chipid bf531_chipid
506 static const struct bfin_memory_layout bf531_mem[] =
507 {
508 LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
509 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
510 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
511 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
512 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
513 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
514 };
515 static const struct bfin_memory_layout bf532_mem[] =
516 {
517 LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
518 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
519 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
520 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
521 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
522 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
523 LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */
524 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
525 };
526 static const struct bfin_memory_layout bf533_mem[] =
527 {
528 LAYOUT (0xFFC00640, 0xC, read_write), /* TIMER stub */
529 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
530 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
531 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
532 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
533 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
534 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
535 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
536 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
537 LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */
538 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
539 };
540 static const struct bfin_dev_layout bf533_dev[] =
541 {
542 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
543 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
544 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
545 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
546 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
547 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
548 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
549 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
550 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
551 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
552 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
553 };
554 #define bf531_dev bf533_dev
555 #define bf532_dev bf533_dev
556 static const struct bfin_dmac_layout bf533_dmac[] =
557 {
558 { BFIN_MMR_DMAC0_BASE, 8, },
559 };
560 #define bf531_dmac bf533_dmac
561 #define bf532_dmac bf533_dmac
562 static const struct bfin_port_layout bf533_port[] =
563 {
564 SIC (0, 0, "bfin_pll", "pll"),
565 /*SIC (0, 1, "bfin_dmac@0", "stat"),*/
566 SIC (0, 2, "bfin_ppi@0", "stat"),
567 SIC (0, 3, "bfin_sport@0", "stat"),
568 SIC (0, 4, "bfin_sport@1", "stat"),
569 SIC (0, 5, "bfin_spi@0", "stat"),
570 SIC (0, 6, "bfin_uart@0", "stat"),
571 SIC (0, 7, "bfin_rtc", "rtc"),
572 SIC (0, 8, "bfin_dma@0", "di"),
573 SIC (0, 9, "bfin_dma@1", "di"),
574 SIC (0, 10, "bfin_dma@2", "di"),
575 SIC (0, 11, "bfin_dma@3", "di"),
576 SIC (0, 12, "bfin_dma@4", "di"),
577 SIC (0, 13, "bfin_dma@5", "di"),
578 SIC (0, 14, "bfin_dma@6", "di"),
579 SIC (0, 15, "bfin_dma@7", "di"),
580 SIC (0, 16, "bfin_gptimer@0", "stat"),
581 SIC (0, 17, "bfin_gptimer@1", "stat"),
582 SIC (0, 18, "bfin_gptimer@2", "stat"),
583 SIC (0, 19, "bfin_gpio@5", "mask_a"),
584 SIC (0, 20, "bfin_gpio@5", "mask_b"),
585 SIC (0, 21, "bfin_dma@256", "di"), /* mdma0 */
586 SIC (0, 21, "bfin_dma@257", "di"), /* mdma0 */
587 SIC (0, 22, "bfin_dma@258", "di"), /* mdma */
588 SIC (0, 22, "bfin_dma@259", "di"), /* mdma1 */
589 SIC (0, 23, "bfin_wdog@0", "gpi"),
590 };
591 #define bf531_port bf533_port
592 #define bf532_port bf533_port
593
594 #define bf534_chipid 0x27c6
595 #define bf536_chipid 0x27c8
596 #define bf537_chipid bf536_chipid
597 static const struct bfin_memory_layout bf534_mem[] =
598 {
599 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
600 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
601 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
602 LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
603 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
604 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
605 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
606 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
607 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
608 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
609 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
610 };
611 static const struct bfin_memory_layout bf536_mem[] =
612 {
613 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
614 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
615 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
616 LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
617 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
618 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
619 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
620 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
621 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
622 };
623 static const struct bfin_memory_layout bf537_mem[] =
624 {
625 LAYOUT (0xFFC00680, 0xC, read_write), /* TIMER stub */
626 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
627 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
628 LAYOUT (0xFFC03200, 0x10, read_write), /* PORT_MUX stub */
629 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
630 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
631 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
632 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
633 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
634 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
635 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
636 };
637 static const struct bfin_dev_layout bf534_dev[] =
638 {
639 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
640 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
641 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
642 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
643 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
644 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
645 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
646 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
647 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
648 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
649 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
650 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
651 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
652 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
653 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
654 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
655 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
656 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
657 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
658 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
659 DEVICE (0, 0, "glue-or@1"),
660 DEVICE (0, 0, "glue-or@1/interrupt-ranges 0 5"),
661 DEVICE (0, 0, "glue-or@2"),
662 DEVICE (0, 0, "glue-or@2/interrupt-ranges 0 8"),
663 DEVICE (0, 0, "glue-or@17"),
664 DEVICE (0, 0, "glue-or@17/interrupt-ranges 0 2"),
665 DEVICE (0, 0, "glue-or@18"),
666 DEVICE (0, 0, "glue-or@18/interrupt-ranges 0 2"),
667 DEVICE (0, 0, "glue-or@27"),
668 DEVICE (0, 0, "glue-or@27/interrupt-ranges 0 2"),
669 DEVICE (0, 0, "glue-or@31"),
670 DEVICE (0, 0, "glue-or@31/interrupt-ranges 0 2"),
671 };
672 static const struct bfin_dev_layout bf537_dev[] =
673 {
674 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
675 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
676 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
677 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
678 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
679 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
680 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
681 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
682 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
683 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
684 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
685 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
686 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
687 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
688 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
689 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
690 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
691 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
692 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
693 DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1"),
694 DEVICE (0xFFC03000, BFIN_MMR_EMAC_SIZE, "bfin_emac"),
695 DEVICE (0, 0x20, "bfin_emac/eth_phy"),
696 DEVICE (0, 0, "glue-or@1"),
697 DEVICE (0, 0, "glue-or@1/interrupt-ranges 0 5"),
698 DEVICE (0, 0, "glue-or@2"),
699 DEVICE (0, 0, "glue-or@2/interrupt-ranges 0 8"),
700 DEVICE (0, 0, "glue-or@17"),
701 DEVICE (0, 0, "glue-or@17/interrupt-ranges 0 2"),
702 DEVICE (0, 0, "glue-or@18"),
703 DEVICE (0, 0, "glue-or@18/interrupt-ranges 0 2"),
704 DEVICE (0, 0, "glue-or@27"),
705 DEVICE (0, 0, "glue-or@27/interrupt-ranges 0 2"),
706 DEVICE (0, 0, "glue-or@31"),
707 DEVICE (0, 0, "glue-or@31/interrupt-ranges 0 2"),
708 };
709 #define bf536_dev bf537_dev
710 #define bf534_dmac bf50x_dmac
711 #define bf536_dmac bf50x_dmac
712 #define bf537_dmac bf50x_dmac
713 static const struct bfin_port_layout bf537_port[] =
714 {
715 SIC (0, 0, "bfin_pll", "pll"),
716 SIC (0, 1, "glue-or@1", "int"),
717 /*PORT ("glue-or@1", "int", "bfin_dmac@0", "stat"),*/
718 PORT ("glue-or@1", "int", "bfin_dmar@0", "block"),
719 PORT ("glue-or@1", "int", "bfin_dmar@1", "block"),
720 PORT ("glue-or@1", "int", "bfin_dmar@0", "overflow"),
721 PORT ("glue-or@1", "int", "bfin_dmar@1", "overflow"),
722 SIC (0, 2, "glue-or@2", "int"),
723 PORT ("glue-or@2", "int", "bfin_can@0", "stat"),
724 PORT ("glue-or@2", "int", "bfin_emac", "stat"),
725 PORT ("glue-or@2", "int", "bfin_sport@0", "stat"),
726 PORT ("glue-or@2", "int", "bfin_sport@1", "stat"),
727 PORT ("glue-or@2", "int", "bfin_ppi@0", "stat"),
728 PORT ("glue-or@2", "int", "bfin_spi@0", "stat"),
729 PORT ("glue-or@2", "int", "bfin_uart@0", "stat"),
730 PORT ("glue-or@2", "int", "bfin_uart@1", "stat"),
731 SIC (0, 3, "bfin_rtc", "rtc"),
732 SIC (0, 4, "bfin_dma@0", "di"),
733 SIC (0, 5, "bfin_dma@3", "di"),
734 SIC (0, 6, "bfin_dma@4", "di"),
735 SIC (0, 7, "bfin_dma@5", "di"),
736 SIC (0, 8, "bfin_dma@6", "di"),
737 SIC (0, 9, "bfin_twi@0", "stat"),
738 SIC (0, 10, "bfin_dma@7", "di"),
739 SIC (0, 11, "bfin_dma@8", "di"),
740 SIC (0, 12, "bfin_dma@9", "di"),
741 SIC (0, 13, "bfin_dma@10", "di"),
742 SIC (0, 14, "bfin_dma@11", "di"),
743 SIC (0, 15, "bfin_can@0", "rx"),
744 SIC (0, 16, "bfin_can@0", "tx"),
745 SIC (0, 17, "glue-or@17", "int"),
746 PORT ("glue-or@17", "int", "bfin_dma@1", "di"),
747 PORT ("glue-or@17", "int", "bfin_gpio@7", "mask_a"),
748 SIC (0, 18, "glue-or@18", "int"),
749 PORT ("glue-or@18", "int", "bfin_dma@2", "di"),
750 PORT ("glue-or@18", "int", "bfin_gpio@7", "mask_b"),
751 SIC (0, 19, "bfin_gptimer@0", "stat"),
752 SIC (0, 20, "bfin_gptimer@1", "stat"),
753 SIC (0, 21, "bfin_gptimer@2", "stat"),
754 SIC (0, 22, "bfin_gptimer@3", "stat"),
755 SIC (0, 23, "bfin_gptimer@4", "stat"),
756 SIC (0, 24, "bfin_gptimer@5", "stat"),
757 SIC (0, 25, "bfin_gptimer@6", "stat"),
758 SIC (0, 26, "bfin_gptimer@7", "stat"),
759 SIC (0, 27, "glue-or@27", "int"),
760 PORT ("glue-or@27", "int", "bfin_gpio@5", "mask_a"),
761 PORT ("glue-or@27", "int", "bfin_gpio@6", "mask_a"),
762 SIC (0, 28, "bfin_gpio@6", "mask_b"),
763 SIC (0, 29, "bfin_dma@256", "di"), /* mdma0 */
764 SIC (0, 29, "bfin_dma@257", "di"), /* mdma0 */
765 SIC (0, 30, "bfin_dma@258", "di"), /* mdma1 */
766 SIC (0, 30, "bfin_dma@259", "di"), /* mdma1 */
767 SIC (0, 31, "glue-or@31", "int"),
768 PORT ("glue-or@31", "int", "bfin_wdog@0", "gpi"),
769 PORT ("glue-or@31", "int", "bfin_gpio@5", "mask_b"),
770 };
771 #define bf534_port bf537_port
772 #define bf536_port bf537_port
773
774 #define bf538_chipid 0x27c4
775 #define bf539_chipid bf538_chipid
776 static const struct bfin_memory_layout bf538_mem[] =
777 {
778 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
779 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
780 LAYOUT (0xFFC01500, 0x70, read_write), /* PORTC/D/E stub */
781 LAYOUT (0xFFC02500, 0x60, read_write), /* SPORT2 stub */
782 LAYOUT (0xFFC02600, 0x60, read_write), /* SPORT3 stub */
783 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
784 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
785 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
786 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
787 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
788 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
789 LAYOUT (0xFFA0C000, 0x4000, read_write_exec), /* Inst C [1] */
790 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
791 };
792 #define bf539_mem bf538_mem
793 static const struct bfin_dev_layout bf538_dev[] =
794 {
795 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
796 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
797 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
798 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
799 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
800 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
801 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
802 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
803 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
804 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
805 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
806 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
807 _DEVICE (0xFFC02000, BFIN_MMR_UART_SIZE, "bfin_uart@1", 1),
808 _DEVICE (0xFFC02100, BFIN_MMR_UART_SIZE, "bfin_uart@2", 1),
809 DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"),
810 _DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1", 1),
811 _DEVICE (0xFFC02400, BFIN_MMR_SPI_SIZE, "bfin_spi@2", 1),
812 };
813 #define bf539_dev bf538_dev
814 static const struct bfin_dmac_layout bf538_dmac[] =
815 {
816 { BFIN_MMR_DMAC0_BASE, 8, },
817 { BFIN_MMR_DMAC1_BASE, 12, },
818 };
819 #define bf539_dmac bf538_dmac
820 static const struct bfin_port_layout bf538_port[] =
821 {
822 SIC (0, 0, "bfin_pll", "pll"),
823 SIC (0, 1, "bfin_dmac@0", "stat"),
824 SIC (0, 2, "bfin_ppi@0", "stat"),
825 SIC (0, 3, "bfin_sport@0", "stat"),
826 SIC (0, 4, "bfin_sport@1", "stat"),
827 SIC (0, 5, "bfin_spi@0", "stat"),
828 SIC (0, 6, "bfin_uart@0", "stat"),
829 SIC (0, 7, "bfin_rtc", "rtc"),
830 SIC (0, 8, "bfin_dma@0", "di"),
831 SIC (0, 9, "bfin_dma@1", "di"),
832 SIC (0, 10, "bfin_dma@2", "di"),
833 SIC (0, 11, "bfin_dma@3", "di"),
834 SIC (0, 12, "bfin_dma@4", "di"),
835 SIC (0, 13, "bfin_dma@5", "di"),
836 SIC (0, 14, "bfin_dma@6", "di"),
837 SIC (0, 15, "bfin_dma@7", "di"),
838 SIC (0, 16, "bfin_gptimer@0", "stat"),
839 SIC (0, 17, "bfin_gptimer@1", "stat"),
840 SIC (0, 18, "bfin_gptimer@2", "stat"),
841 SIC (0, 19, "bfin_gpio@5", "mask_a"),
842 SIC (0, 20, "bfin_gpio@5", "mask_b"),
843 SIC (0, 21, "bfin_dma@256", "di"), /* mdma0 */
844 SIC (0, 21, "bfin_dma@257", "di"), /* mdma0 */
845 SIC (0, 22, "bfin_dma@258", "di"), /* mdma1 */
846 SIC (0, 22, "bfin_dma@259", "di"), /* mdma1 */
847 SIC (0, 23, "bfin_wdog@0", "gpi"),
848 SIC (0, 24, "bfin_dmac@1", "stat"),
849 SIC (0, 25, "bfin_sport@2", "stat"),
850 SIC (0, 26, "bfin_sport@3", "stat"),
851 /*SIC (0, 27, reserved),*/
852 SIC (0, 28, "bfin_spi@1", "stat"),
853 SIC (0, 29, "bfin_spi@2", "stat"),
854 SIC (0, 30, "bfin_uart@1", "stat"),
855 SIC (0, 31, "bfin_uart@2", "stat"),
856 SIC (1, 0, "bfin_can@0", "stat"),
857 SIC (1, 1, "bfin_dma@8", "di"),
858 SIC (1, 2, "bfin_dma@9", "di"),
859 SIC (1, 3, "bfin_dma@10", "di"),
860 SIC (1, 4, "bfin_dma@11", "di"),
861 SIC (1, 5, "bfin_dma@12", "di"),
862 SIC (1, 6, "bfin_dma@13", "di"),
863 SIC (1, 7, "bfin_dma@14", "di"),
864 SIC (1, 8, "bfin_dma@15", "di"),
865 SIC (1, 9, "bfin_dma@16", "di"),
866 SIC (1, 10, "bfin_dma@17", "di"),
867 SIC (1, 11, "bfin_dma@18", "di"),
868 SIC (1, 12, "bfin_dma@19", "di"),
869 SIC (1, 13, "bfin_twi@0", "stat"),
870 SIC (1, 14, "bfin_twi@1", "stat"),
871 SIC (1, 15, "bfin_can@0", "rx"),
872 SIC (1, 16, "bfin_can@0", "tx"),
873 SIC (1, 17, "bfin_dma@260", "di"), /* mdma2 */
874 SIC (1, 17, "bfin_dma@261", "di"), /* mdma2 */
875 SIC (1, 18, "bfin_dma@262", "di"), /* mdma3 */
876 SIC (1, 18, "bfin_dma@263", "di"), /* mdma3 */
877 };
878 #define bf539_port bf538_port
879
880 #define bf54x_chipid 0x27de
881 #define bf542_chipid bf54x_chipid
882 #define bf544_chipid bf54x_chipid
883 #define bf547_chipid bf54x_chipid
884 #define bf548_chipid bf54x_chipid
885 #define bf549_chipid bf54x_chipid
886 static const struct bfin_memory_layout bf54x_mem[] =
887 {
888 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub XXX: not on BF542/4 */
889 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
890 LAYOUT (0xFFC02500, 0x60, read_write), /* SPORT2 stub */
891 LAYOUT (0xFFC02600, 0x60, read_write), /* SPORT3 stub */
892 LAYOUT (0xFFC03800, 0x70, read_write), /* ATAPI stub */
893 LAYOUT (0xFFC03900, 0x100, read_write), /* RSI stub */
894 LAYOUT (0xFFC03C00, 0x500, read_write), /* MUSB stub */
895 LAYOUT (0xFEB00000, 0x20000, read_write_exec), /* L2 */
896 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
897 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
898 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
899 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
900 LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
901 LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
902 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
903 };
904 #define bf542_mem bf54x_mem
905 #define bf544_mem bf54x_mem
906 #define bf547_mem bf54x_mem
907 #define bf548_mem bf54x_mem
908 #define bf549_mem bf54x_mem
909 static const struct bfin_dev_layout bf542_dev[] =
910 {
911 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
912 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
913 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
914 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
915 DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
916 DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
917 DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
918 _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1),
919 DEVICE (0xFFC01400, BFIN_MMR_PINT_SIZE, "bfin_pint@0"),
920 DEVICE (0xFFC01430, BFIN_MMR_PINT_SIZE, "bfin_pint@1"),
921 _DEVICE (0xFFC01460, BFIN_MMR_PINT_SIZE, "bfin_pint@2", 2),
922 _DEVICE (0xFFC01490, BFIN_MMR_PINT_SIZE, "bfin_pint@3", 2),
923 DEVICE (0xFFC014C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@0"),
924 DEVICE (0xFFC014E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@1"),
925 DEVICE (0xFFC01500, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@2"),
926 DEVICE (0xFFC01520, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@3"),
927 DEVICE (0xFFC01540, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@4"),
928 DEVICE (0xFFC01560, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@5"),
929 DEVICE (0xFFC01580, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@6"),
930 DEVICE (0xFFC015A0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@7"),
931 DEVICE (0xFFC015C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@8"),
932 DEVICE (0xFFC015E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@9"),
933 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
934 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
935 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
936 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
937 DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
938 DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
939 DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
940 DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
941 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
942 _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1),
943 DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
944 _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1),
945 _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1),
946 DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
947 DEVICE (0xFFC04300, BFIN_MMR_OTP_SIZE, "bfin_otp"),
948 };
949 static const struct bfin_dev_layout bf544_dev[] =
950 {
951 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
952 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
953 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
954 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
955 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"),
956 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"),
957 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"),
958 DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
959 DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
960 DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
961 _DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE, "bfin_eppi@0", 1),
962 _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1),
963 DEVICE (0xFFC01400, BFIN_MMR_PINT_SIZE, "bfin_pint@0"),
964 DEVICE (0xFFC01430, BFIN_MMR_PINT_SIZE, "bfin_pint@1"),
965 _DEVICE (0xFFC01460, BFIN_MMR_PINT_SIZE, "bfin_pint@2", 2),
966 _DEVICE (0xFFC01490, BFIN_MMR_PINT_SIZE, "bfin_pint@3", 2),
967 DEVICE (0xFFC014C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@0"),
968 DEVICE (0xFFC014E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@1"),
969 DEVICE (0xFFC01500, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@2"),
970 DEVICE (0xFFC01520, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@3"),
971 DEVICE (0xFFC01540, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@4"),
972 DEVICE (0xFFC01560, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@5"),
973 DEVICE (0xFFC01580, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@6"),
974 DEVICE (0xFFC015A0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@7"),
975 DEVICE (0xFFC015C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@8"),
976 DEVICE (0xFFC015E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@9"),
977 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
978 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
979 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
980 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
981 DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
982 DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
983 DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
984 DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
985 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
986 _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1),
987 DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"),
988 DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
989 _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1),
990 _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1),
991 DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
992 DEVICE (0xFFC04300, BFIN_MMR_OTP_SIZE, "bfin_otp"),
993 };
994 static const struct bfin_dev_layout bf547_dev[] =
995 {
996 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
997 DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE, "bfin_rtc"),
998 DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE, "bfin_uart2@0"),
999 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
1000 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"),
1001 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"),
1002 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"),
1003 DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
1004 DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
1005 DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
1006 _DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE, "bfin_eppi@0", 1),
1007 _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1),
1008 DEVICE (0xFFC01400, BFIN_MMR_PINT_SIZE, "bfin_pint@0"),
1009 DEVICE (0xFFC01430, BFIN_MMR_PINT_SIZE, "bfin_pint@1"),
1010 _DEVICE (0xFFC01460, BFIN_MMR_PINT_SIZE, "bfin_pint@2", 2),
1011 _DEVICE (0xFFC01490, BFIN_MMR_PINT_SIZE, "bfin_pint@3", 2),
1012 DEVICE (0xFFC014C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@0"),
1013 DEVICE (0xFFC014E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@1"),
1014 DEVICE (0xFFC01500, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@2"),
1015 DEVICE (0xFFC01520, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@3"),
1016 DEVICE (0xFFC01540, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@4"),
1017 DEVICE (0xFFC01560, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@5"),
1018 DEVICE (0xFFC01580, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@6"),
1019 DEVICE (0xFFC015A0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@7"),
1020 DEVICE (0xFFC015C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@8"),
1021 DEVICE (0xFFC015E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@9"),
1022 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
1023 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
1024 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
1025 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
1026 DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
1027 DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
1028 DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
1029 DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
1030 DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE, "bfin_uart2@1"),
1031 _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE, "bfin_uart2@2", 1),
1032 DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE, "bfin_twi@1"),
1033 DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
1034 _DEVICE (0xFFC02400, BFIN_MMR_SPI_SIZE, "bfin_spi@2", 1),
1035 _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE, "bfin_eppi@2", 1),
1036 _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE, "bfin_uart2@3", 1),
1037 DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE, "bfin_nfc"),
1038 };
1039 #define bf548_dev bf547_dev
1040 #define bf549_dev bf547_dev
1041 static const struct bfin_dmac_layout bf54x_dmac[] =
1042 {
1043 { BFIN_MMR_DMAC0_BASE, 12, },
1044 { BFIN_MMR_DMAC1_BASE, 12, },
1045 };
1046 #define bf542_dmac bf54x_dmac
1047 #define bf544_dmac bf54x_dmac
1048 #define bf547_dmac bf54x_dmac
1049 #define bf548_dmac bf54x_dmac
1050 #define bf549_dmac bf54x_dmac
1051 #define PINT_PIQS(p, b, g) \
1052 PORT (p, "piq0@"#b, g, "p0"), \
1053 PORT (p, "piq1@"#b, g, "p1"), \
1054 PORT (p, "piq2@"#b, g, "p2"), \
1055 PORT (p, "piq3@"#b, g, "p3"), \
1056 PORT (p, "piq4@"#b, g, "p4"), \
1057 PORT (p, "piq5@"#b, g, "p5"), \
1058 PORT (p, "piq6@"#b, g, "p6"), \
1059 PORT (p, "piq7@"#b, g, "p7"), \
1060 PORT (p, "piq8@"#b, g, "p8"), \
1061 PORT (p, "piq9@"#b, g, "p9"), \
1062 PORT (p, "piq10@"#b, g, "p10"), \
1063 PORT (p, "piq11@"#b, g, "p11"), \
1064 PORT (p, "piq12@"#b, g, "p12"), \
1065 PORT (p, "piq13@"#b, g, "p13"), \
1066 PORT (p, "piq14@"#b, g, "p14"), \
1067 PORT (p, "piq15@"#b, g, "p15")
1068 static const struct bfin_port_layout bf54x_port[] =
1069 {
1070 SIC (0, 0, "bfin_pll", "pll"),
1071 SIC (0, 1, "bfin_dmac@0", "stat"),
1072 SIC (0, 2, "bfin_eppi@0", "stat"),
1073 SIC (0, 3, "bfin_sport@0", "stat"),
1074 SIC (0, 4, "bfin_sport@1", "stat"),
1075 SIC (0, 5, "bfin_spi@0", "stat"),
1076 SIC (0, 6, "bfin_uart2@0", "stat"),
1077 SIC (0, 7, "bfin_rtc", "rtc"),
1078 SIC (0, 8, "bfin_dma@12", "di"),
1079 SIC (0, 9, "bfin_dma@0", "di"),
1080 SIC (0, 10, "bfin_dma@1", "di"),
1081 SIC (0, 11, "bfin_dma@2", "di"),
1082 SIC (0, 12, "bfin_dma@3", "di"),
1083 SIC (0, 13, "bfin_dma@4", "di"),
1084 SIC (0, 14, "bfin_dma@6", "di"),
1085 SIC (0, 15, "bfin_dma@7", "di"),
1086 SIC (0, 16, "bfin_gptimer@8", "stat"),
1087 SIC (0, 17, "bfin_gptimer@9", "stat"),
1088 SIC (0, 18, "bfin_gptimer@10", "stat"),
1089 SIC (0, 19, "bfin_pint@0", "stat"),
1090 PINT_PIQS ("bfin_pint@0", 0, "bfin_gpio2@0"),
1091 PINT_PIQS ("bfin_pint@0", 1, "bfin_gpio2@1"),
1092 SIC (0, 20, "bfin_pint@1", "stat"),
1093 PINT_PIQS ("bfin_pint@1", 0, "bfin_gpio2@0"),
1094 PINT_PIQS ("bfin_pint@1", 1, "bfin_gpio2@1"),
1095 SIC (0, 21, "bfin_dma@256", "di"), /* mdma0 */
1096 SIC (0, 21, "bfin_dma@257", "di"), /* mdma0 */
1097 SIC (0, 22, "bfin_dma@258", "di"), /* mdma1 */
1098 SIC (0, 22, "bfin_dma@259", "di"), /* mdma1 */
1099 SIC (0, 23, "bfin_wdog@0", "gpi"),
1100 SIC (0, 24, "bfin_dmac@1", "stat"),
1101 SIC (0, 25, "bfin_sport@2", "stat"),
1102 SIC (0, 26, "bfin_sport@3", "stat"),
1103 SIC (0, 27, "bfin_mxvr", "data"),
1104 SIC (0, 28, "bfin_spi@1", "stat"),
1105 SIC (0, 29, "bfin_spi@2", "stat"),
1106 SIC (0, 30, "bfin_uart2@1", "stat"),
1107 SIC (0, 31, "bfin_uart2@2", "stat"),
1108 SIC (1, 0, "bfin_can@0", "stat"),
1109 SIC (1, 1, "bfin_dma@18", "di"),
1110 SIC (1, 2, "bfin_dma@19", "di"),
1111 SIC (1, 3, "bfin_dma@20", "di"),
1112 SIC (1, 4, "bfin_dma@21", "di"),
1113 SIC (1, 5, "bfin_dma@13", "di"),
1114 SIC (1, 6, "bfin_dma@14", "di"),
1115 SIC (1, 7, "bfin_dma@5", "di"),
1116 SIC (1, 8, "bfin_dma@23", "di"),
1117 SIC (1, 9, "bfin_dma@8", "di"),
1118 SIC (1, 10, "bfin_dma@9", "di"),
1119 SIC (1, 11, "bfin_dma@10", "di"),
1120 SIC (1, 12, "bfin_dma@11", "di"),
1121 SIC (1, 13, "bfin_twi@0", "stat"),
1122 SIC (1, 14, "bfin_twi@1", "stat"),
1123 SIC (1, 15, "bfin_can@0", "rx"),
1124 SIC (1, 16, "bfin_can@0", "tx"),
1125 SIC (1, 17, "bfin_dma@260", "di"), /* mdma2 */
1126 SIC (1, 17, "bfin_dma@261", "di"), /* mdma2 */
1127 SIC (1, 18, "bfin_dma@262", "di"), /* mdma3 */
1128 SIC (1, 18, "bfin_dma@263", "di"), /* mdma3 */
1129 SIC (1, 19, "bfin_mxvr", "stat"),
1130 SIC (1, 20, "bfin_mxvr", "message"),
1131 SIC (1, 21, "bfin_mxvr", "packet"),
1132 SIC (1, 22, "bfin_eppi@1", "stat"),
1133 SIC (1, 23, "bfin_eppi@2", "stat"),
1134 SIC (1, 24, "bfin_uart2@3", "stat"),
1135 SIC (1, 25, "bfin_hostdp", "stat"),
1136 /*SIC (1, 26, reserved),*/
1137 SIC (1, 27, "bfin_pixc", "stat"),
1138 SIC (1, 28, "bfin_nfc", "stat"),
1139 SIC (1, 29, "bfin_atapi", "stat"),
1140 SIC (1, 30, "bfin_can@1", "stat"),
1141 SIC (1, 31, "bfin_dmar@0", "block"),
1142 SIC (1, 31, "bfin_dmar@1", "block"),
1143 SIC (1, 31, "bfin_dmar@0", "overflow"),
1144 SIC (1, 31, "bfin_dmar@1", "overflow"),
1145 SIC (2, 0, "bfin_dma@15", "di"),
1146 SIC (2, 1, "bfin_dma@16", "di"),
1147 SIC (2, 2, "bfin_dma@17", "di"),
1148 SIC (2, 3, "bfin_dma@22", "di"),
1149 SIC (2, 4, "bfin_counter@0", "stat"),
1150 SIC (2, 5, "bfin_kpad@0", "stat"),
1151 SIC (2, 6, "bfin_can@1", "rx"),
1152 SIC (2, 7, "bfin_can@1", "tx"),
1153 SIC (2, 8, "bfin_sdh", "mask0"),
1154 SIC (2, 9, "bfin_sdh", "mask1"),
1155 /*SIC (2, 10, reserved),*/
1156 SIC (2, 11, "bfin_usb", "int0"),
1157 SIC (2, 12, "bfin_usb", "int1"),
1158 SIC (2, 13, "bfin_usb", "int2"),
1159 SIC (2, 14, "bfin_usb", "dma"),
1160 SIC (2, 15, "bfin_otp", "stat"),
1161 /*SIC (2, 16, reserved),*/
1162 /*SIC (2, 17, reserved),*/
1163 /*SIC (2, 18, reserved),*/
1164 /*SIC (2, 19, reserved),*/
1165 /*SIC (2, 20, reserved),*/
1166 /*SIC (2, 21, reserved),*/
1167 SIC (2, 22, "bfin_gptimer@0", "stat"),
1168 SIC (2, 23, "bfin_gptimer@1", "stat"),
1169 SIC (2, 24, "bfin_gptimer@2", "stat"),
1170 SIC (2, 25, "bfin_gptimer@3", "stat"),
1171 SIC (2, 26, "bfin_gptimer@4", "stat"),
1172 SIC (2, 27, "bfin_gptimer@5", "stat"),
1173 SIC (2, 28, "bfin_gptimer@6", "stat"),
1174 SIC (2, 29, "bfin_gptimer@7", "stat"),
1175 SIC (2, 30, "bfin_pint@2", "stat"),
1176 PINT_PIQS ("bfin_pint@2", 0, "bfin_gpio2@2"),
1177 PINT_PIQS ("bfin_pint@2", 1, "bfin_gpio2@3"),
1178 PINT_PIQS ("bfin_pint@2", 2, "bfin_gpio2@4"),
1179 PINT_PIQS ("bfin_pint@2", 3, "bfin_gpio2@5"),
1180 PINT_PIQS ("bfin_pint@2", 4, "bfin_gpio2@6"),
1181 PINT_PIQS ("bfin_pint@2", 5, "bfin_gpio2@7"),
1182 PINT_PIQS ("bfin_pint@2", 6, "bfin_gpio2@8"),
1183 PINT_PIQS ("bfin_pint@2", 7, "bfin_gpio2@9"),
1184 SIC (2, 31, "bfin_pint@3", "stat"),
1185 PINT_PIQS ("bfin_pint@3", 0, "bfin_gpio2@2"),
1186 PINT_PIQS ("bfin_pint@3", 1, "bfin_gpio2@3"),
1187 PINT_PIQS ("bfin_pint@3", 2, "bfin_gpio2@4"),
1188 PINT_PIQS ("bfin_pint@3", 3, "bfin_gpio2@5"),
1189 PINT_PIQS ("bfin_pint@3", 4, "bfin_gpio2@6"),
1190 PINT_PIQS ("bfin_pint@3", 5, "bfin_gpio2@7"),
1191 PINT_PIQS ("bfin_pint@3", 6, "bfin_gpio2@8"),
1192 PINT_PIQS ("bfin_pint@3", 7, "bfin_gpio2@9"),
1193 };
1194 #define bf542_port bf54x_port
1195 #define bf544_port bf54x_port
1196 #define bf547_port bf54x_port
1197 #define bf548_port bf54x_port
1198 #define bf549_port bf54x_port
1199
1200 /* This is only Core A of course ... */
1201 #define bf561_chipid 0x27bb
1202 static const struct bfin_memory_layout bf561_mem[] =
1203 {
1204 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
1205 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
1206 LAYOUT (0xFEB00000, 0x20000, read_write_exec), /* L2 */
1207 LAYOUT (0xFF800000, 0x4000, read_write), /* Data A */
1208 LAYOUT (0xFF804000, 0x4000, read_write), /* Data A Cache */
1209 LAYOUT (0xFF900000, 0x4000, read_write), /* Data B */
1210 LAYOUT (0xFF904000, 0x4000, read_write), /* Data B Cache */
1211 LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */
1212 LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
1213 };
1214 static const struct bfin_dev_layout bf561_dev[] =
1215 {
1216 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
1217 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
1218 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
1219 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
1220 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
1221 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
1222 DEVICE (0xFFC00630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@3"),
1223 DEVICE (0xFFC00640, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@4"),
1224 DEVICE (0xFFC00650, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@5"),
1225 DEVICE (0xFFC00660, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@6"),
1226 DEVICE (0xFFC00670, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@7"),
1227 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
1228 DEVICE (0xFFC00A00, BFIN_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
1229 DEVICE (0xFFC00A10, BFIN_MMR_EBIU_SDC_SIZE, "bfin_ebiu_sdc"),
1230 _DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0", 1),
1231 DEVICE (0xFFC01200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@1"),
1232 _DEVICE (0xFFC01300, BFIN_MMR_PPI_SIZE, "bfin_ppi@1", 1),
1233 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
1234 DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@8"),
1235 DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@9"),
1236 DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@10"),
1237 DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@11"),
1238 DEVICE (0xFFC01700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@7"),
1239 };
1240 static const struct bfin_dmac_layout bf561_dmac[] =
1241 {
1242 { BFIN_MMR_DMAC0_BASE, 12, },
1243 { BFIN_MMR_DMAC1_BASE, 12, },
1244 /* XXX: IMDMA: { 0xFFC01800, 4, }, */
1245 };
1246 static const struct bfin_port_layout bf561_port[] =
1247 {
1248 /* SIC0 */
1249 SIC (0, 0, "bfin_pll", "pll"),
1250 /*SIC (0, 1, "bfin_dmac@0", "stat"),*/
1251 /*SIC (0, 2, "bfin_dmac@1", "stat"),*/
1252 /*SIC (0, 3, "bfin_imdmac", "stat"),*/
1253 SIC (0, 4, "bfin_ppi@0", "stat"),
1254 SIC (0, 5, "bfin_ppi@1", "stat"),
1255 SIC (0, 6, "bfin_sport@0", "stat"),
1256 SIC (0, 7, "bfin_sport@1", "stat"),
1257 SIC (0, 8, "bfin_spi@0", "stat"),
1258 SIC (0, 9, "bfin_uart@0", "stat"),
1259 /*SIC (0, 10, reserved),*/
1260 SIC (0, 11, "bfin_dma@12", "di"),
1261 SIC (0, 12, "bfin_dma@13", "di"),
1262 SIC (0, 13, "bfin_dma@14", "di"),
1263 SIC (0, 14, "bfin_dma@15", "di"),
1264 SIC (0, 15, "bfin_dma@16", "di"),
1265 SIC (0, 16, "bfin_dma@17", "di"),
1266 SIC (0, 17, "bfin_dma@18", "di"),
1267 SIC (0, 18, "bfin_dma@19", "di"),
1268 SIC (0, 19, "bfin_dma@20", "di"),
1269 SIC (0, 20, "bfin_dma@21", "di"),
1270 SIC (0, 21, "bfin_dma@22", "di"),
1271 SIC (0, 22, "bfin_dma@23", "di"),
1272 SIC (0, 23, "bfin_dma@0", "di"),
1273 SIC (0, 24, "bfin_dma@1", "di"),
1274 SIC (0, 25, "bfin_dma@2", "di"),
1275 SIC (0, 26, "bfin_dma@3", "di"),
1276 SIC (0, 27, "bfin_dma@4", "di"),
1277 SIC (0, 28, "bfin_dma@5", "di"),
1278 SIC (0, 29, "bfin_dma@6", "di"),
1279 SIC (0, 30, "bfin_dma@7", "di"),
1280 SIC (0, 31, "bfin_dma@8", "di"),
1281 SIC (1, 0, "bfin_dma@9", "di"),
1282 SIC (1, 1, "bfin_dma@10", "di"),
1283 SIC (1, 2, "bfin_dma@11", "di"),
1284 SIC (1, 3, "bfin_gptimer@0", "stat"),
1285 SIC (1, 4, "bfin_gptimer@1", "stat"),
1286 SIC (1, 5, "bfin_gptimer@2", "stat"),
1287 SIC (1, 6, "bfin_gptimer@3", "stat"),
1288 SIC (1, 7, "bfin_gptimer@4", "stat"),
1289 SIC (1, 8, "bfin_gptimer@5", "stat"),
1290 SIC (1, 9, "bfin_gptimer@6", "stat"),
1291 SIC (1, 10, "bfin_gptimer@7", "stat"),
1292 SIC (1, 11, "bfin_gptimer@8", "stat"),
1293 SIC (1, 12, "bfin_gptimer@9", "stat"),
1294 SIC (1, 13, "bfin_gptimer@10", "stat"),
1295 SIC (1, 14, "bfin_gptimer@11", "stat"),
1296 SIC (1, 15, "bfin_gpio@5", "mask_a"),
1297 SIC (1, 16, "bfin_gpio@5", "mask_b"),
1298 SIC (1, 17, "bfin_gpio@6", "mask_a"),
1299 SIC (1, 18, "bfin_gpio@6", "mask_b"),
1300 SIC (1, 19, "bfin_gpio@7", "mask_a"),
1301 SIC (1, 20, "bfin_gpio@7", "mask_b"),
1302 SIC (1, 21, "bfin_dma@256", "di"), /* mdma0 */
1303 SIC (1, 21, "bfin_dma@257", "di"), /* mdma0 */
1304 SIC (1, 22, "bfin_dma@258", "di"), /* mdma1 */
1305 SIC (1, 22, "bfin_dma@259", "di"), /* mdma1 */
1306 SIC (1, 23, "bfin_dma@260", "di"), /* mdma2 */
1307 SIC (1, 23, "bfin_dma@261", "di"), /* mdma2 */
1308 SIC (1, 24, "bfin_dma@262", "di"), /* mdma3 */
1309 SIC (1, 24, "bfin_dma@263", "di"), /* mdma3 */
1310 SIC (1, 25, "bfin_imdma@0", "di"),
1311 SIC (1, 26, "bfin_imdma@1", "di"),
1312 SIC (1, 27, "bfin_wdog@0", "gpi"),
1313 SIC (1, 27, "bfin_wdog@1", "gpi"),
1314 /*SIC (1, 28, reserved),*/
1315 /*SIC (1, 29, reserved),*/
1316 SIC (1, 30, "bfin_sic", "sup_irq@0"),
1317 SIC (1, 31, "bfin_sic", "sup_irq@1"),
1318 };
1319
1320 #define bf592_chipid 0x20cb
1321 static const struct bfin_memory_layout bf592_mem[] =
1322 {
1323 LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub */
1324 LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */
1325 LAYOUT (0xFF800000, 0x8000, read_write), /* Data A */
1326 LAYOUT (0xFFA00000, 0x4000, read_write_exec), /* Inst A [1] */
1327 LAYOUT (0xFFA04000, 0x4000, read_write_exec), /* Inst B [1] */
1328 };
1329 static const struct bfin_dev_layout bf592_dev[] =
1330 {
1331 DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE, "bfin_wdog@0"),
1332 DEVICE (0xFFC00400, BFIN_MMR_UART_SIZE, "bfin_uart@0"),
1333 DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE, "bfin_spi@0"),
1334 DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"),
1335 DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"),
1336 DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"),
1337 DEVICE (0xFFC00700, BFIN_MMR_GPIO_SIZE, "bfin_gpio@5"),
1338 DEVICE (0xFFC01000, BFIN_MMR_PPI_SIZE, "bfin_ppi@0"),
1339 DEVICE (0xFFC01300, BFIN_MMR_SPI_SIZE, "bfin_spi@1"),
1340 DEVICE (0xFFC01400, BFIN_MMR_TWI_SIZE, "bfin_twi@0"),
1341 DEVICE (0xFFC01500, BFIN_MMR_GPIO_SIZE, "bfin_gpio@6"),
1342 };
1343 static const struct bfin_dmac_layout bf592_dmac[] =
1344 {
1345 /* XXX: there are only 9 channels, but mdma code below assumes that they
1346 start right after the dma channels ... */
1347 { BFIN_MMR_DMAC0_BASE, 12, },
1348 };
1349 static const struct bfin_port_layout bf592_port[] =
1350 {
1351 SIC (0, 0, "bfin_pll", "pll"),
1352 /*SIC (0, 1, "bfin_dmac@0", "stat"),*/
1353 SIC (0, 2, "bfin_ppi@0", "stat"),
1354 SIC (0, 3, "bfin_sport@0", "stat"),
1355 SIC (0, 4, "bfin_sport@1", "stat"),
1356 SIC (0, 5, "bfin_spi@0", "stat"),
1357 SIC (0, 6, "bfin_spi@1", "stat"),
1358 SIC (0, 7, "bfin_uart@0", "stat"),
1359 SIC (0, 8, "bfin_dma@0", "di"),
1360 SIC (0, 9, "bfin_dma@1", "di"),
1361 SIC (0, 10, "bfin_dma@2", "di"),
1362 SIC (0, 11, "bfin_dma@3", "di"),
1363 SIC (0, 12, "bfin_dma@4", "di"),
1364 SIC (0, 13, "bfin_dma@5", "di"),
1365 SIC (0, 14, "bfin_dma@6", "di"),
1366 SIC (0, 15, "bfin_dma@7", "di"),
1367 SIC (0, 16, "bfin_dma@8", "di"),
1368 SIC (0, 17, "bfin_gpio@5", "mask_a"),
1369 SIC (0, 18, "bfin_gpio@5", "mask_b"),
1370 SIC (0, 19, "bfin_gptimer@0", "stat"),
1371 SIC (0, 20, "bfin_gptimer@1", "stat"),
1372 SIC (0, 21, "bfin_gptimer@2", "stat"),
1373 SIC (0, 22, "bfin_gpio@6", "mask_a"),
1374 SIC (0, 23, "bfin_gpio@6", "mask_b"),
1375 SIC (0, 24, "bfin_twi@0", "stat"),
1376 /* XXX: 25 - 28 are supposed to be reserved; see comment in machs.c:bf592_dmac[] */
1377 SIC (0, 25, "bfin_dma@9", "di"),
1378 SIC (0, 26, "bfin_dma@10", "di"),
1379 SIC (0, 27, "bfin_dma@11", "di"),
1380 SIC (0, 28, "bfin_dma@12", "di"),
1381 /*SIC (0, 25, reserved),*/
1382 /*SIC (0, 26, reserved),*/
1383 /*SIC (0, 27, reserved),*/
1384 /*SIC (0, 28, reserved),*/
1385 SIC (0, 29, "bfin_dma@256", "di"), /* mdma0 */
1386 SIC (0, 29, "bfin_dma@257", "di"), /* mdma0 */
1387 SIC (0, 30, "bfin_dma@258", "di"), /* mdma1 */
1388 SIC (0, 30, "bfin_dma@259", "di"), /* mdma1 */
1389 SIC (0, 31, "bfin_wdog", "gpi"),
1390 };
1391
1392 static const struct bfin_model_data bfin_model_data[] =
1393 {
1394 #define P(n) \
1395 [MODEL_BF##n] = { \
1396 bf##n##_chipid, n, \
1397 bf##n##_mem , ARRAY_SIZE (bf##n##_mem ), \
1398 bf##n##_dev , ARRAY_SIZE (bf##n##_dev ), \
1399 bf##n##_dmac, ARRAY_SIZE (bf##n##_dmac), \
1400 bf##n##_port, ARRAY_SIZE (bf##n##_port), \
1401 },
1402 #include "proc_list.def"
1403 #undef P
1404 };
1405
1406 #define CORE_DEVICE(dev, DEV) \
1407 DEVICE (BFIN_COREMMR_##DEV##_BASE, BFIN_COREMMR_##DEV##_SIZE, "bfin_"#dev)
1408 static const struct bfin_dev_layout bfin_core_dev[] =
1409 {
1410 CORE_DEVICE (cec, CEC),
1411 CORE_DEVICE (ctimer, CTIMER),
1412 CORE_DEVICE (evt, EVT),
1413 CORE_DEVICE (jtag, JTAG),
1414 CORE_DEVICE (mmu, MMU),
1415 CORE_DEVICE (pfmon, PFMON),
1416 CORE_DEVICE (trace, TRACE),
1417 CORE_DEVICE (wp, WP),
1418 };
1419
1420 static void
1421 dv_bfin_hw_port_parse (SIM_DESC sd, const struct bfin_model_data *mdata,
1422 const char *dev)
1423 {
1424 size_t i;
1425 const char *sdev;
1426
1427 sdev = strchr (dev, '/');
1428 if (sdev)
1429 ++sdev;
1430 else
1431 sdev = dev;
1432
1433 for (i = 0; i < mdata->port_count; ++i)
1434 {
1435 const struct bfin_port_layout *port = &mdata->port[i];
1436
1437 /* There might be more than one mapping. */
1438 if (!strcmp (sdev, port->src))
1439 sim_hw_parse (sd, "/core/%s > %s %s /core/%s", dev,
1440 port->src_port, port->dst_port, port->dst);
1441 }
1442 }
1443
1444 #define dv_bfin_hw_parse(sd, dv, DV) \
1445 do { \
1446 bu32 base = BFIN_MMR_##DV##_BASE; \
1447 bu32 size = BFIN_MMR_##DV##_SIZE; \
1448 sim_hw_parse (sd, "/core/bfin_"#dv"/reg %#x %i", base, size); \
1449 sim_hw_parse (sd, "/core/bfin_"#dv"/type %i", mdata->model_num); \
1450 dv_bfin_hw_port_parse (sd, mdata, "bfin_"#dv); \
1451 } while (0)
1452
1453 static void
1454 bfin_model_hw_tree_init (SIM_DESC sd, SIM_CPU *cpu)
1455 {
1456 const SIM_MODEL *model = CPU_MODEL (cpu);
1457 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
1458 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1459 int mnum = MODEL_NUM (model);
1460 unsigned i, j, dma_chan;
1461
1462 /* Map the core devices. */
1463 for (i = 0; i < ARRAY_SIZE (bfin_core_dev); ++i)
1464 {
1465 const struct bfin_dev_layout *dev = &bfin_core_dev[i];
1466 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev->dev, dev->base, dev->len);
1467 }
1468 sim_hw_parse (sd, "/core/bfin_ctimer > ivtmr ivtmr /core/bfin_cec");
1469
1470 if (mnum == MODEL_BF000)
1471 goto done;
1472
1473 /* Map the system devices. */
1474 dv_bfin_hw_parse (sd, sic, SIC);
1475 for (i = 7; i < 16; ++i)
1476 sim_hw_parse (sd, "/core/bfin_sic > ivg%i ivg%i /core/bfin_cec", i, i);
1477
1478 dv_bfin_hw_parse (sd, pll, PLL);
1479
1480 dma_chan = 0;
1481 for (i = 0; i < mdata->dmac_count; ++i)
1482 {
1483 const struct bfin_dmac_layout *dmac = &mdata->dmac[i];
1484
1485 sim_hw_parse (sd, "/core/bfin_dmac@%u/type %i", i, mdata->model_num);
1486
1487 /* Hook up the non-mdma channels. */
1488 for (j = 0; j < dmac->dma_count; ++j)
1489 {
1490 char dev[64];
1491
1492 sprintf (dev, "bfin_dmac@%u/bfin_dma@%u", i, dma_chan);
1493 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev,
1494 dmac->base + j * BFIN_MMR_DMA_SIZE, BFIN_MMR_DMA_SIZE);
1495 dv_bfin_hw_port_parse (sd, mdata, dev);
1496
1497 ++dma_chan;
1498 }
1499
1500 /* Hook up the mdma channels -- assume every DMAC has 4. */
1501 for (j = 0; j < 4; ++j)
1502 {
1503 char dev[64];
1504
1505 sprintf (dev, "bfin_dmac@%u/bfin_dma@%u", i, j + BFIN_DMAC_MDMA_BASE);
1506 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev,
1507 dmac->base + (j + dmac->dma_count) * BFIN_MMR_DMA_SIZE,
1508 BFIN_MMR_DMA_SIZE);
1509 dv_bfin_hw_port_parse (sd, mdata, dev);
1510 }
1511 }
1512
1513 for (i = 0; i < mdata->dev_count; ++i)
1514 {
1515 const struct bfin_dev_layout *dev = &mdata->dev[i];
1516
1517 if (dev->len)
1518 {
1519 sim_hw_parse (sd, "/core/%s/reg %#x %i", dev->dev, dev->base, dev->len);
1520 sim_hw_parse (sd, "/core/%s/type %i", dev->dev, mdata->model_num);
1521 }
1522 else
1523 {
1524 sim_hw_parse (sd, "/core/%s", dev->dev);
1525 }
1526
1527 dv_bfin_hw_port_parse (sd, mdata, dev->dev);
1528 if (strchr (dev->dev, '/'))
1529 continue;
1530
1531 if (!strncmp (dev->dev, "bfin_uart", 9)
1532 || !strncmp (dev->dev, "bfin_emac", 9)
1533 || !strncmp (dev->dev, "bfin_sport", 10))
1534 {
1535 const char *sint = dev->dev + 5;
1536 sim_hw_parse (sd, "/core/%s > tx %s_tx /core/bfin_dmac@%u", dev->dev, sint, dev->dmac);
1537 sim_hw_parse (sd, "/core/%s > rx %s_rx /core/bfin_dmac@%u", dev->dev, sint, dev->dmac);
1538 }
1539 else if (!strncmp (dev->dev, "bfin_wdog", 9))
1540 {
1541 sim_hw_parse (sd, "/core/%s > reset rst /core/bfin_cec", dev->dev);
1542 sim_hw_parse (sd, "/core/%s > nmi nmi /core/bfin_cec", dev->dev);
1543 }
1544 }
1545
1546 done:
1547 /* Add any additional user board content. */
1548 if (board->hw_file)
1549 sim_do_commandf (sd, "hw-file %s", board->hw_file);
1550
1551 /* Trigger all the new devices' finish func. */
1552 hw_tree_finish (dv_get_device (cpu, "/"));
1553 }
1554
1555 #include "bfroms/all.h"
1556
1557 struct bfrom {
1558 bu32 addr, len, alias_len;
1559 int sirev;
1560 const char *buf;
1561 };
1562
1563 #define BFROMA(addr, rom, sirev, alias_len) \
1564 { addr, sizeof (bfrom_bf##rom##_0_##sirev), alias_len, \
1565 sirev, bfrom_bf##rom##_0_##sirev, }
1566 #define BFROM(rom, sirev, alias_len) BFROMA (0xef000000, rom, sirev, alias_len)
1567 #define BFROM_STUB { 0, 0, 0, 0, NULL, }
1568 static const struct bfrom bf50x_roms[] =
1569 {
1570 BFROM (50x, 0, 0x1000000),
1571 BFROM_STUB,
1572 };
1573 static const struct bfrom bf51x_roms[] =
1574 {
1575 BFROM (51x, 2, 0x1000000),
1576 BFROM (51x, 1, 0x1000000),
1577 BFROM (51x, 0, 0x1000000),
1578 BFROM_STUB,
1579 };
1580 static const struct bfrom bf526_roms[] =
1581 {
1582 BFROM (526, 2, 0x1000000),
1583 BFROM (526, 1, 0x1000000),
1584 BFROM (526, 0, 0x1000000),
1585 BFROM_STUB,
1586 };
1587 static const struct bfrom bf527_roms[] =
1588 {
1589 BFROM (527, 2, 0x1000000),
1590 BFROM (527, 1, 0x1000000),
1591 BFROM (527, 0, 0x1000000),
1592 BFROM_STUB,
1593 };
1594 static const struct bfrom bf533_roms[] =
1595 {
1596 BFROM (533, 6, 0x1000000),
1597 BFROM (533, 5, 0x1000000),
1598 BFROM (533, 4, 0x1000000),
1599 BFROM (533, 3, 0x1000000),
1600 BFROM (533, 2, 0x1000000),
1601 BFROM (533, 1, 0x1000000),
1602 BFROM_STUB,
1603 };
1604 static const struct bfrom bf537_roms[] =
1605 {
1606 BFROM (537, 3, 0x100000),
1607 BFROM (537, 2, 0x100000),
1608 BFROM (537, 1, 0x100000),
1609 BFROM (537, 0, 0x100000),
1610 BFROM_STUB,
1611 };
1612 static const struct bfrom bf538_roms[] =
1613 {
1614 BFROM (538, 5, 0x1000000),
1615 BFROM (538, 4, 0x1000000),
1616 BFROM (538, 3, 0x1000000),
1617 BFROM (538, 2, 0x1000000),
1618 BFROM (538, 1, 0x1000000),
1619 BFROM (538, 0, 0x1000000),
1620 BFROM_STUB,
1621 };
1622 static const struct bfrom bf54x_roms[] =
1623 {
1624 BFROM (54x, 4, 0x1000),
1625 BFROM (54x, 2, 0x1000),
1626 BFROM (54x, 1, 0x1000),
1627 BFROM (54x, 0, 0x1000),
1628 BFROMA (0xffa14000, 54x_l1, 4, 0x10000),
1629 BFROMA (0xffa14000, 54x_l1, 2, 0x10000),
1630 BFROMA (0xffa14000, 54x_l1, 1, 0x10000),
1631 BFROMA (0xffa14000, 54x_l1, 0, 0x10000),
1632 BFROM_STUB,
1633 };
1634 static const struct bfrom bf561_roms[] =
1635 {
1636 /* XXX: No idea what the actual wrap limit is here. */
1637 BFROM (561, 5, 0x1000),
1638 BFROM_STUB,
1639 };
1640 static const struct bfrom bf59x_roms[] =
1641 {
1642 BFROM (59x, 1, 0x1000000),
1643 BFROM (59x, 0, 0x1000000),
1644 BFROMA (0xffa10000, 59x_l1, 1, 0x10000),
1645 BFROM_STUB,
1646 };
1647
1648 static void
1649 bfin_model_map_bfrom (SIM_DESC sd, SIM_CPU *cpu)
1650 {
1651 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
1652 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1653 int mnum = mdata->model_num;
1654 const struct bfrom *bfrom;
1655 unsigned int sirev;
1656
1657 if (mnum >= 500 && mnum <= 509)
1658 bfrom = bf50x_roms;
1659 else if (mnum >= 510 && mnum <= 519)
1660 bfrom = bf51x_roms;
1661 else if (mnum >= 520 && mnum <= 529)
1662 bfrom = (mnum & 1) ? bf527_roms : bf526_roms;
1663 else if (mnum >= 531 && mnum <= 533)
1664 bfrom = bf533_roms;
1665 else if (mnum == 535)
1666 return; /* Stub. */
1667 else if (mnum >= 534 && mnum <= 537)
1668 bfrom = bf537_roms;
1669 else if (mnum >= 538 && mnum <= 539)
1670 bfrom = bf538_roms;
1671 else if (mnum >= 540 && mnum <= 549)
1672 bfrom = bf54x_roms;
1673 else if (mnum == 561)
1674 bfrom = bf561_roms;
1675 else if (mnum >= 590 && mnum <= 599)
1676 bfrom = bf59x_roms;
1677 else
1678 return;
1679
1680 if (board->sirev_valid)
1681 sirev = board->sirev;
1682 else
1683 sirev = bfrom->sirev;
1684 while (bfrom->buf)
1685 {
1686 /* Map all the ranges for this model/sirev. */
1687 if (bfrom->sirev == sirev)
1688 sim_core_attach (sd, NULL, 0, access_read_exec, 0, bfrom->addr,
1689 bfrom->alias_len ? : bfrom->len, bfrom->len, NULL,
1690 (char *)bfrom->buf);
1691 ++bfrom;
1692 }
1693 }
1694
1695 void
1696 bfin_model_cpu_init (SIM_DESC sd, SIM_CPU *cpu)
1697 {
1698 const SIM_MODEL *model = CPU_MODEL (cpu);
1699 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
1700 int mnum = MODEL_NUM (model);
1701 size_t idx;
1702
1703 /* These memory maps are supposed to be cpu-specific, but the common sim
1704 code does not yet allow that (2nd arg is "cpu" rather than "NULL". */
1705 sim_core_attach (sd, NULL, 0, access_read_write, 0, BFIN_L1_SRAM_SCRATCH,
1706 BFIN_L1_SRAM_SCRATCH_SIZE, 0, NULL, NULL);
1707
1708 if (STATE_ENVIRONMENT (CPU_STATE (cpu)) != OPERATING_ENVIRONMENT)
1709 return;
1710
1711 if (mnum == MODEL_BF000)
1712 goto core_only;
1713
1714 /* Map in the on-chip memories (SRAMs). */
1715 mdata = &bfin_model_data[MODEL_NUM (model)];
1716 for (idx = 0; idx < mdata->mem_count; ++idx)
1717 {
1718 const struct bfin_memory_layout *mem = &mdata->mem[idx];
1719 sim_core_attach (sd, NULL, 0, mem->mask, 0, mem->addr,
1720 mem->len, 0, NULL, NULL);
1721 }
1722
1723 /* Map the on-chip ROMs. */
1724 bfin_model_map_bfrom (sd, cpu);
1725
1726 core_only:
1727 /* Finally, build up the tree for this cpu model. */
1728 bfin_model_hw_tree_init (sd, cpu);
1729 }
1730
1731 bu32
1732 bfin_model_get_chipid (SIM_DESC sd)
1733 {
1734 SIM_CPU *cpu = STATE_CPU (sd, 0);
1735 const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
1736 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1737 return
1738 (board->sirev << 28) |
1739 (mdata->chipid << 12) |
1740 (((0xE5 << 1) | 1) & 0xFF);
1741 }
1742
1743 bu32
1744 bfin_model_get_dspid (SIM_DESC sd)
1745 {
1746 const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1747 return
1748 (0xE5 << 24) |
1749 (0x04 << 16) |
1750 (board->sirev);
1751 }
1752
1753 static void
1754 bfin_model_init (SIM_CPU *cpu)
1755 {
1756 CPU_MODEL_DATA (cpu) = (void *) &bfin_model_data[MODEL_NUM (CPU_MODEL (cpu))];
1757 }
1758
1759 static bu32
1760 bfin_extract_unsigned_integer (unsigned char *addr, int len)
1761 {
1762 bu32 retval;
1763 unsigned char * p;
1764 unsigned char * startaddr = (unsigned char *)addr;
1765 unsigned char * endaddr = startaddr + len;
1766
1767 retval = 0;
1768
1769 for (p = endaddr; p > startaddr;)
1770 retval = (retval << 8) | *--p;
1771
1772 return retval;
1773 }
1774
1775 static void
1776 bfin_store_unsigned_integer (unsigned char *addr, int len, bu32 val)
1777 {
1778 unsigned char *p;
1779 unsigned char *startaddr = addr;
1780 unsigned char *endaddr = startaddr + len;
1781
1782 for (p = startaddr; p < endaddr;)
1783 {
1784 *p++ = val & 0xff;
1785 val >>= 8;
1786 }
1787 }
1788
1789 static bu32 *
1790 bfin_get_reg (SIM_CPU *cpu, int rn)
1791 {
1792 switch (rn)
1793 {
1794 case SIM_BFIN_R0_REGNUM: return &DREG (0);
1795 case SIM_BFIN_R1_REGNUM: return &DREG (1);
1796 case SIM_BFIN_R2_REGNUM: return &DREG (2);
1797 case SIM_BFIN_R3_REGNUM: return &DREG (3);
1798 case SIM_BFIN_R4_REGNUM: return &DREG (4);
1799 case SIM_BFIN_R5_REGNUM: return &DREG (5);
1800 case SIM_BFIN_R6_REGNUM: return &DREG (6);
1801 case SIM_BFIN_R7_REGNUM: return &DREG (7);
1802 case SIM_BFIN_P0_REGNUM: return &PREG (0);
1803 case SIM_BFIN_P1_REGNUM: return &PREG (1);
1804 case SIM_BFIN_P2_REGNUM: return &PREG (2);
1805 case SIM_BFIN_P3_REGNUM: return &PREG (3);
1806 case SIM_BFIN_P4_REGNUM: return &PREG (4);
1807 case SIM_BFIN_P5_REGNUM: return &PREG (5);
1808 case SIM_BFIN_SP_REGNUM: return &SPREG;
1809 case SIM_BFIN_FP_REGNUM: return &FPREG;
1810 case SIM_BFIN_I0_REGNUM: return &IREG (0);
1811 case SIM_BFIN_I1_REGNUM: return &IREG (1);
1812 case SIM_BFIN_I2_REGNUM: return &IREG (2);
1813 case SIM_BFIN_I3_REGNUM: return &IREG (3);
1814 case SIM_BFIN_M0_REGNUM: return &MREG (0);
1815 case SIM_BFIN_M1_REGNUM: return &MREG (1);
1816 case SIM_BFIN_M2_REGNUM: return &MREG (2);
1817 case SIM_BFIN_M3_REGNUM: return &MREG (3);
1818 case SIM_BFIN_B0_REGNUM: return &BREG (0);
1819 case SIM_BFIN_B1_REGNUM: return &BREG (1);
1820 case SIM_BFIN_B2_REGNUM: return &BREG (2);
1821 case SIM_BFIN_B3_REGNUM: return &BREG (3);
1822 case SIM_BFIN_L0_REGNUM: return &LREG (0);
1823 case SIM_BFIN_L1_REGNUM: return &LREG (1);
1824 case SIM_BFIN_L2_REGNUM: return &LREG (2);
1825 case SIM_BFIN_L3_REGNUM: return &LREG (3);
1826 case SIM_BFIN_RETS_REGNUM: return &RETSREG;
1827 case SIM_BFIN_A0_DOT_X_REGNUM: return &AXREG (0);
1828 case SIM_BFIN_A0_DOT_W_REGNUM: return &AWREG (0);
1829 case SIM_BFIN_A1_DOT_X_REGNUM: return &AXREG (1);
1830 case SIM_BFIN_A1_DOT_W_REGNUM: return &AWREG (1);
1831 case SIM_BFIN_LC0_REGNUM: return &LCREG (0);
1832 case SIM_BFIN_LT0_REGNUM: return &LTREG (0);
1833 case SIM_BFIN_LB0_REGNUM: return &LBREG (0);
1834 case SIM_BFIN_LC1_REGNUM: return &LCREG (1);
1835 case SIM_BFIN_LT1_REGNUM: return &LTREG (1);
1836 case SIM_BFIN_LB1_REGNUM: return &LBREG (1);
1837 case SIM_BFIN_CYCLES_REGNUM: return &CYCLESREG;
1838 case SIM_BFIN_CYCLES2_REGNUM: return &CYCLES2REG;
1839 case SIM_BFIN_USP_REGNUM: return &USPREG;
1840 case SIM_BFIN_SEQSTAT_REGNUM: return &SEQSTATREG;
1841 case SIM_BFIN_SYSCFG_REGNUM: return &SYSCFGREG;
1842 case SIM_BFIN_RETI_REGNUM: return &RETIREG;
1843 case SIM_BFIN_RETX_REGNUM: return &RETXREG;
1844 case SIM_BFIN_RETN_REGNUM: return &RETNREG;
1845 case SIM_BFIN_RETE_REGNUM: return &RETEREG;
1846 case SIM_BFIN_PC_REGNUM: return &PCREG;
1847 default: return NULL;
1848 }
1849 }
1850
1851 static int
1852 bfin_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *buf, int len)
1853 {
1854 bu32 value, *reg;
1855
1856 reg = bfin_get_reg (cpu, rn);
1857 if (reg)
1858 value = *reg;
1859 else if (rn == SIM_BFIN_ASTAT_REGNUM)
1860 value = ASTAT;
1861 else if (rn == SIM_BFIN_CC_REGNUM)
1862 value = CCREG;
1863 else
1864 return -1;
1865
1866 /* Handle our KSP/USP shadowing in SP. While in supervisor mode, we
1867 have the normal SP/USP behavior. User mode is tricky though. */
1868 if (STATE_ENVIRONMENT (CPU_STATE (cpu)) == OPERATING_ENVIRONMENT
1869 && cec_is_user_mode (cpu))
1870 {
1871 if (rn == SIM_BFIN_SP_REGNUM)
1872 value = KSPREG;
1873 else if (rn == SIM_BFIN_USP_REGNUM)
1874 value = SPREG;
1875 }
1876
1877 bfin_store_unsigned_integer (buf, 4, value);
1878
1879 return 4;
1880 }
1881
1882 static int
1883 bfin_reg_store (SIM_CPU *cpu, int rn, unsigned char *buf, int len)
1884 {
1885 bu32 value, *reg;
1886
1887 value = bfin_extract_unsigned_integer (buf, 4);
1888 reg = bfin_get_reg (cpu, rn);
1889
1890 if (reg)
1891 /* XXX: Need register trace ? */
1892 *reg = value;
1893 else if (rn == SIM_BFIN_ASTAT_REGNUM)
1894 SET_ASTAT (value);
1895 else if (rn == SIM_BFIN_CC_REGNUM)
1896 SET_CCREG (value);
1897 else
1898 return -1;
1899
1900 return 4;
1901 }
1902
1903 static sim_cia
1904 bfin_pc_get (SIM_CPU *cpu)
1905 {
1906 return PCREG;
1907 }
1908
1909 static void
1910 bfin_pc_set (SIM_CPU *cpu, sim_cia newpc)
1911 {
1912 SET_PCREG (newpc);
1913 }
1914
1915 static const char *
1916 bfin_insn_name (SIM_CPU *cpu, int i)
1917 {
1918 static const char * const insn_name[] = {
1919 #define I(insn) #insn,
1920 #include "insn_list.def"
1921 #undef I
1922 };
1923 return insn_name[i];
1924 }
1925
1926 static void
1927 bfin_init_cpu (SIM_CPU *cpu)
1928 {
1929 CPU_REG_FETCH (cpu) = bfin_reg_fetch;
1930 CPU_REG_STORE (cpu) = bfin_reg_store;
1931 CPU_PC_FETCH (cpu) = bfin_pc_get;
1932 CPU_PC_STORE (cpu) = bfin_pc_set;
1933 CPU_MAX_INSNS (cpu) = BFIN_INSN_MAX;
1934 CPU_INSN_NAME (cpu) = bfin_insn_name;
1935 }
1936
1937 static void
1938 bfin_prepare_run (SIM_CPU *cpu)
1939 {
1940 }
1941
1942 static const SIM_MODEL bfin_models[] =
1943 {
1944 #define P(n) { "bf"#n, & bfin_mach, MODEL_BF##n, NULL, bfin_model_init },
1945 #include "proc_list.def"
1946 #undef P
1947 { 0, NULL, 0, NULL, NULL, }
1948 };
1949
1950 static const SIM_MACH_IMP_PROPERTIES bfin_imp_properties =
1951 {
1952 sizeof (SIM_CPU),
1953 0,
1954 };
1955
1956 static const SIM_MACH bfin_mach =
1957 {
1958 "bfin", "bfin", MACH_BFIN,
1959 32, 32, & bfin_models[0], & bfin_imp_properties,
1960 bfin_init_cpu,
1961 bfin_prepare_run
1962 };
1963
1964 const SIM_MACH *sim_machs[] =
1965 {
1966 & bfin_mach,
1967 NULL
1968 };
1969 \f
1970 /* Device option parsing. */
1971
1972 static DECLARE_OPTION_HANDLER (bfin_mach_option_handler);
1973
1974 enum {
1975 OPTION_MACH_SIREV = OPTION_START,
1976 OPTION_MACH_HW_BOARD_FILE,
1977 };
1978
1979 static const OPTION bfin_mach_options[] =
1980 {
1981 { {"sirev", required_argument, NULL, OPTION_MACH_SIREV },
1982 '\0', "NUMBER", "Set CPU silicon revision",
1983 bfin_mach_option_handler, NULL },
1984
1985 { {"hw-board-file", required_argument, NULL, OPTION_MACH_HW_BOARD_FILE },
1986 '\0', "FILE", "Add the supplemental devices listed in the file",
1987 bfin_mach_option_handler, NULL },
1988
1989 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL, NULL }
1990 };
1991
1992 static SIM_RC
1993 bfin_mach_option_handler (SIM_DESC sd, sim_cpu *current_cpu, int opt,
1994 char *arg, int is_command)
1995 {
1996 struct bfin_board_data *board = STATE_BOARD_DATA (sd);
1997
1998 switch (opt)
1999 {
2000 case OPTION_MACH_SIREV:
2001 board->sirev_valid = 1;
2002 /* Accept (and throw away) a leading "0." in the version. */
2003 if (!strncmp (arg, "0.", 2))
2004 arg += 2;
2005 board->sirev = atoi (arg);
2006 if (board->sirev > 0xf)
2007 {
2008 sim_io_eprintf (sd, "sirev '%s' needs to fit into 4 bits\n", arg);
2009 return SIM_RC_FAIL;
2010 }
2011 return SIM_RC_OK;
2012
2013 case OPTION_MACH_HW_BOARD_FILE:
2014 board->hw_file = xstrdup (arg);
2015 return SIM_RC_OK;
2016
2017 default:
2018 sim_io_eprintf (sd, "Unknown Blackfin option %d\n", opt);
2019 return SIM_RC_FAIL;
2020 }
2021 }
2022
2023 /* Provide a prototype to silence -Wmissing-prototypes. */
2024 extern MODULE_INIT_FN sim_install_bfin_mach;
2025
2026 SIM_RC
2027 sim_install_bfin_mach (SIM_DESC sd)
2028 {
2029 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
2030 return sim_add_option_table (sd, NULL, bfin_mach_options);
2031 }