sim/common/cgen-par.h

   1 /* Simulator header for cgen parallel support.
   2    Copyright (C) 1999 Free Software Foundation, Inc.
   3    Contributed by Cygnus Solutions.
   4
   5 This file is part of the GNU instruction set simulator.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef CGEN_PAR_H
  22 #define CGEN_PAR_H
  23
  24 /* Kinds of writes stored on the write queue.  */
  25 enum cgen_write_queue_kind {
  26   CGEN_BI_WRITE, CGEN_QI_WRITE, CGEN_SI_WRITE, CGEN_SF_WRITE,
  27   CGEN_PC_WRITE,
  28   CGEN_FN_HI_WRITE, CGEN_FN_SI_WRITE, CGEN_FN_DI_WRITE, CGEN_FN_DF_WRITE,
  29   CGEN_FN_PC_WRITE,
  30   CGEN_MEM_QI_WRITE, CGEN_MEM_HI_WRITE, CGEN_MEM_SI_WRITE, CGEN_MEM_DI_WRITE,
  31   CGEN_MEM_DF_WRITE,
  32   CGEN_NUM_WRITE_KINDS
  33 };
  34
  35 /* Element of the write queue.  */
  36 typedef struct {
  37   enum cgen_write_queue_kind kind; /* Used to select union member below.  */
  38   IADDR insn_address;       /* Address of the insn performing the write.  */
  39   union {
  40     struct {
  41       BI  *target;
  42       BI   value;
  43     } bi_write;
  44     struct {
  45       UQI *target;
  46       QI   value;
  47     } qi_write;
  48     struct {
  49       SI *target;
  50       SI  value;
  51     } si_write;
  52     struct {
  53       SI *target;
  54       SF  value;
  55     } sf_write;
  56     struct {
  57       USI value;
  58     } pc_write;
  59     struct {
  60       UINT regno;
  61       UHI   value;
  62       void (*function)(SIM_CPU *, UINT, UHI);
  63     } fn_hi_write;
  64     struct {
  65       UINT regno;
  66       SI   value;
  67       void (*function)(SIM_CPU *, UINT, USI);
  68     } fn_si_write;
  69     struct {
  70       UINT regno;
  71       DI   value;
  72       void (*function)(SIM_CPU *, UINT, DI);
  73     } fn_di_write;
  74     struct {
  75       UINT regno;
  76       DI   value;
  77       void (*function)(SIM_CPU *, UINT, DI);
  78     } fn_df_write;
  79     struct {
  80       USI  value;
  81       void (*function)(SIM_CPU *, USI);
  82     } fn_pc_write;
  83     struct {
  84       SI   address;
  85       QI   value;
  86     } mem_qi_write;
  87     struct {
  88       SI   address;
  89       HI   value;
  90     } mem_hi_write;
  91     struct {
  92       SI   address;
  93       SI   value;
  94     } mem_si_write;
  95     struct {
  96       SI   address;
  97       DI   value;
  98     } mem_di_write;
  99     struct {
 100       SI   address;
 101       DI   value;
 102     } mem_df_write;
 103   } kinds;
 104 } CGEN_WRITE_QUEUE_ELEMENT;
 105
 106 #define CGEN_WRITE_QUEUE_ELEMENT_KIND(element) ((element)->kind)
 107 #define CGEN_WRITE_QUEUE_ELEMENT_IADDR(element) ((element)->insn_address)
 108
 109 extern void cgen_write_queue_element_execute (
 110   SIM_CPU *, CGEN_WRITE_QUEUE_ELEMENT *
 111 );
 112
 113 /* Instance of the queue for parallel write-after support.  */
 114 /* FIXME: Should be dynamic?  */
 115 #define CGEN_WRITE_QUEUE_SIZE (4 * 4) /* 4 writes x 4 insns -- for now.  */
 116
 117 typedef struct {
 118   int index;
 119   CGEN_WRITE_QUEUE_ELEMENT q[CGEN_WRITE_QUEUE_SIZE];
 120 } CGEN_WRITE_QUEUE;
 121
 122 #define CGEN_WRITE_QUEUE_CLEAR(queue)       ((queue)->index = 0)
 123 #define CGEN_WRITE_QUEUE_INDEX(queue)       ((queue)->index)
 124 #define CGEN_WRITE_QUEUE_ELEMENT(queue, ix) (&(queue)->q[(ix)])
 125
 126 #define CGEN_WRITE_QUEUE_NEXT(queue) (   \
 127   (queue)->index < CGEN_WRITE_QUEUE_SIZE \
 128     ? &(queue)->q[(queue)->index++]      \
 129     : cgen_write_queue_overflow (queue)  \
 130 )
 131
 132 extern CGEN_WRITE_QUEUE_ELEMENT *cgen_write_queue_overflow (CGEN_WRITE_QUEUE *);
 133
 134 /* Functions for queuing writes.  Used by semantic code.  */
 135 extern void sim_queue_bi_write (SIM_CPU *, BI *, BI);
 136 extern void sim_queue_qi_write (SIM_CPU *, UQI *, UQI);
 137 extern void sim_queue_si_write (SIM_CPU *, SI *, SI);
 138 extern void sim_queue_sf_write (SIM_CPU *, SI *, SF);
 139
 140 extern void sim_queue_pc_write (SIM_CPU *, USI);
 141
 142 extern void sim_queue_fn_hi_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, UHI), UINT, UHI);
 143 extern void sim_queue_fn_si_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, USI), UINT, SI);
 144 extern void sim_queue_fn_di_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DI), UINT, DI);
 145 extern void sim_queue_fn_df_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DI), UINT, DF);
 146 extern void sim_queue_fn_pc_write (SIM_CPU *, void (*)(SIM_CPU *, USI), USI);
 147
 148 extern void sim_queue_mem_qi_write (SIM_CPU *, SI, QI);
 149 extern void sim_queue_mem_hi_write (SIM_CPU *, SI, HI);
 150 extern void sim_queue_mem_si_write (SIM_CPU *, SI, SI);
 151 extern void sim_queue_mem_di_write (SIM_CPU *, SI, DI);
 152 extern void sim_queue_mem_df_write (SIM_CPU *, SI, DF);
 153
 154 #endif /* CGEN_PAR_H */