1 /* Simulator cache routines for CGEN simulators (and maybe others).
2 Copyright (C) 1996-2021 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* This must come before any other includes. */
23 #define SCACHE_DEFINE_INLINE
27 #include "libiberty.h"
28 #include "sim-options.h"
32 #define UNUSED_ADDR 0xffffffff
34 /* Scache configuration parameters.
35 ??? Experiments to determine reasonable values is wip.
36 These are just guesses. */
38 /* Default number of scache elements.
39 The size of an element is typically 32-64 bytes, so the size of the
40 default scache will be between 512K and 1M bytes. */
41 #ifdef CONFIG_SIM_CACHE_SIZE
42 #define SCACHE_DEFAULT_CACHE_SIZE CONFIG_SIM_CACHE_SIZE
44 #define SCACHE_DEFAULT_CACHE_SIZE 16384
47 /* Minimum cache size.
48 The m32r port assumes a cache size of at least 2 so it can decode both 16
49 bit insns. When compiling we need an extra for the chain entry. And this
50 must be a multiple of 2. Hence 4 is the minimum (though, for those with
51 featuritis or itchy pedantic bits, we could make this conditional on
53 #define MIN_SCACHE_SIZE 4
55 /* Ratio of size of text section to size of scache.
56 When compiling, we don't want to flush the scache more than we have to
57 but we also don't want it to be exorbitantly(sp?) large. So we pick a high
58 default value, then reduce it by the size of the program being simulated,
59 but we don't override any value specified on the command line.
60 If not specified on the command line, the size to use is computed as
62 min (DEFAULT_SCACHE_SIZE,
63 text_size / (base_insn_size * INSN_SCACHE_RATIO))). */
64 /* ??? Interesting idea but not currently used. */
65 #define INSN_SCACHE_RATIO 4
67 /* Default maximum insn chain length.
68 The only reason for a maximum is so we can place a maximum size on the
69 profiling table. Chain lengths are determined by cti's.
70 32 is a more reasonable number, but when profiling, the before/after
71 handlers take up that much more space. The scache is filled from front to
72 back so all this determines is when the scache needs to be flushed. */
73 #define MAX_CHAIN_LENGTH 64
75 /* Default maximum hash list length. */
76 #define MAX_HASH_CHAIN_LENGTH 4
78 /* Minimum hash table size. */
79 #define MIN_HASH_CHAINS 32
81 /* Ratio of number of scache elements to number of hash lists.
82 Since the user can only specify the size of the scache, we compute the
83 size of the hash table as
84 max (MIN_HASH_CHAINS, scache_size / SCACHE_HASH_RATIO). */
85 #define SCACHE_HASH_RATIO 8
88 FIXME: May wish to make the hashing architecture specific.
90 #define HASH_PC(pc) (((pc) >> 2) + ((pc) >> 5))
92 static MODULE_INIT_FN scache_init
;
93 static MODULE_UNINSTALL_FN scache_uninstall
;
95 static DECLARE_OPTION_HANDLER (scache_option_handler
);
97 #define OPTION_PROFILE_SCACHE (OPTION_START + 0)
99 static const OPTION scache_options
[] = {
100 { {"scache-size", optional_argument
, NULL
, 'c'},
101 'c', "[SIZE]", "Specify size of simulator execution cache",
102 scache_option_handler
},
104 /* ??? It might be nice to allow the user to specify the size of the hash
105 table, the maximum hash list length, and the maximum chain length, but
106 for now that might be more akin to featuritis. */
108 { {"profile-scache", optional_argument
, NULL
, OPTION_PROFILE_SCACHE
},
109 '\0', "on|off", "Perform simulator execution cache profiling",
110 scache_option_handler
},
111 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
}
115 scache_option_handler (SIM_DESC sd
, sim_cpu
*cpu
, int opt
,
116 char *arg
, int is_command
)
125 unsigned int n
= (unsigned int) strtoul (arg
, NULL
, 0);
126 if (n
< MIN_SCACHE_SIZE
)
128 sim_io_eprintf (sd
, "invalid scache size `%u', must be at least %u",
132 /* Ensure it's a multiple of 2. */
133 if ((n
& (n
- 1)) != 0)
136 sim_io_eprintf (sd
, "scache size `%u' not a multiple of 2\n", n
);
137 /* Round up to nearest multiple of 2. */
138 for (i
= 1; i
&& i
< n
; i
<<= 1)
143 sim_io_eprintf (sd
, "rounding scache size up to %u\n", n
);
147 STATE_SCACHE_SIZE (sd
) = n
;
149 CPU_SCACHE_SIZE (cpu
) = n
;
154 STATE_SCACHE_SIZE (sd
) = SCACHE_DEFAULT_CACHE_SIZE
;
156 CPU_SCACHE_SIZE (cpu
) = SCACHE_DEFAULT_CACHE_SIZE
;
160 sim_io_eprintf (sd
, "Simulator execution cache not enabled, `--scache-size' ignored\n");
163 case OPTION_PROFILE_SCACHE
:
164 if (WITH_SCACHE
&& WITH_PROFILE_SCACHE_P
)
166 /* FIXME: handle cpu != NULL. */
167 return sim_profile_set_option (sd
, "-scache", PROFILE_SCACHE_IDX
,
171 sim_io_eprintf (sd
, "Simulator cache profiling not compiled in, `--profile-scache' ignored\n");
178 /* Provide a prototype to silence -Wmissing-prototypes. */
179 SIM_RC
sim_install_scache (SIM_DESC sd
);
181 /* Install the simulator cache into the simulator. */
183 sim_install_scache (SIM_DESC sd
)
185 sim_add_option_table (sd
, NULL
, scache_options
);
186 sim_module_add_init_fn (sd
, scache_init
);
187 sim_module_add_uninstall_fn (sd
, scache_uninstall
);
189 /* This is the default, it may be overridden on the command line. */
190 STATE_SCACHE_SIZE (sd
) = WITH_SCACHE
;
196 scache_init (SIM_DESC sd
)
200 for (c
= 0; c
< MAX_NR_PROCESSORS
; ++c
)
202 SIM_CPU
*cpu
= STATE_CPU (sd
, c
);
203 int elm_size
= IMP_PROPS_SCACHE_ELM_SIZE (MACH_IMP_PROPS (CPU_MACH (cpu
)));
205 /* elm_size is 0 if the cpu doesn't not have scache support */
208 CPU_SCACHE_SIZE (cpu
) = 0;
209 CPU_SCACHE_CACHE (cpu
) = NULL
;
213 if (CPU_SCACHE_SIZE (cpu
) == 0)
214 CPU_SCACHE_SIZE (cpu
) = STATE_SCACHE_SIZE (sd
);
215 CPU_SCACHE_CACHE (cpu
) =
216 (SCACHE
*) xmalloc (CPU_SCACHE_SIZE (cpu
) * elm_size
);
218 CPU_SCACHE_MAX_CHAIN_LENGTH (cpu
) = MAX_CHAIN_LENGTH
;
219 CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu
) = MAX_HASH_CHAIN_LENGTH
;
220 CPU_SCACHE_NUM_HASH_CHAINS (cpu
) = max (MIN_HASH_CHAINS
,
221 CPU_SCACHE_SIZE (cpu
)
222 / SCACHE_HASH_RATIO
);
223 CPU_SCACHE_HASH_TABLE (cpu
) =
224 (SCACHE_MAP
*) xmalloc (CPU_SCACHE_NUM_HASH_CHAINS (cpu
)
225 * CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu
)
226 * sizeof (SCACHE_MAP
));
227 CPU_SCACHE_PBB_BEGIN (cpu
) = (SCACHE
*) zalloc (elm_size
);
228 CPU_SCACHE_CHAIN_LENGTHS (cpu
) =
229 (unsigned long *) zalloc ((CPU_SCACHE_MAX_CHAIN_LENGTH (cpu
) + 1)
241 scache_uninstall (SIM_DESC sd
)
245 for (c
= 0; c
< MAX_NR_PROCESSORS
; ++c
)
247 SIM_CPU
*cpu
= STATE_CPU (sd
, c
);
249 if (CPU_SCACHE_CACHE (cpu
) != NULL
)
250 free (CPU_SCACHE_CACHE (cpu
));
252 if (CPU_SCACHE_HASH_TABLE (cpu
) != NULL
)
253 free (CPU_SCACHE_HASH_TABLE (cpu
));
254 if (CPU_SCACHE_PBB_BEGIN (cpu
) != NULL
)
255 free (CPU_SCACHE_PBB_BEGIN (cpu
));
256 if (CPU_SCACHE_CHAIN_LENGTHS (cpu
) != NULL
)
257 free (CPU_SCACHE_CHAIN_LENGTHS (cpu
));
263 scache_flush (SIM_DESC sd
)
267 for (c
= 0; c
< MAX_NR_PROCESSORS
; ++c
)
269 SIM_CPU
*cpu
= STATE_CPU (sd
, c
);
270 scache_flush_cpu (cpu
);
275 scache_flush_cpu (SIM_CPU
*cpu
)
279 /* Don't bother if cache not in use. */
280 if (CPU_SCACHE_SIZE (cpu
) == 0)
284 /* It's important that this be reasonably fast as this can be done when
285 the simulation is running. */
286 CPU_SCACHE_NEXT_FREE (cpu
) = CPU_SCACHE_CACHE (cpu
);
287 n
= CPU_SCACHE_NUM_HASH_CHAINS (cpu
) * CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu
);
288 /* ??? Might be faster to just set the first entry, then update the
289 "last entry" marker during allocation. */
290 for (i
= 0; i
< n
; ++i
)
291 CPU_SCACHE_HASH_TABLE (cpu
) [i
] . pc
= UNUSED_ADDR
;
294 int elm_size
= IMP_PROPS_SCACHE_ELM_SIZE (MACH_IMP_PROPS (CPU_MACH (cpu
)));
297 /* Technically, this may not be necessary, but it helps debugging. */
298 memset (CPU_SCACHE_CACHE (cpu
), 0,
299 CPU_SCACHE_SIZE (cpu
) * elm_size
);
301 for (i
= 0, sc
= CPU_SCACHE_CACHE (cpu
); i
< CPU_SCACHE_SIZE (cpu
);
302 ++i
, sc
= (SCACHE
*) ((char *) sc
+ elm_size
))
304 sc
->argbuf
.addr
= UNUSED_ADDR
;
312 /* Look up PC in the hash table of scache entry points.
313 Returns the entry or NULL if not found. */
316 scache_lookup (SIM_CPU
*cpu
, IADDR pc
)
318 /* FIXME: hash computation is wrong, doesn't take into account
319 NUM_HASH_CHAIN_ENTRIES. A lot of the hash table will be unused! */
320 unsigned int slot
= HASH_PC (pc
) & (CPU_SCACHE_NUM_HASH_CHAINS (cpu
) - 1);
321 int i
, max_i
= CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu
);
324 /* We don't update hit/miss statistics as this is only used when recording
325 branch target addresses. */
327 scm
= & CPU_SCACHE_HASH_TABLE (cpu
) [slot
];
328 for (i
= 0; i
< max_i
&& scm
->pc
!= UNUSED_ADDR
; ++i
, ++scm
)
336 /* Look up PC and if not found create an entry for it.
337 If found the result is a pointer to the SCACHE entry.
338 If not found the result is NULL, and the address of a buffer of at least
339 N entries is stored in BUFP.
340 It's done this way so the caller can still distinguish found/not-found.
341 If the table is full, it is emptied to make room.
342 If the maximum length of a hash list is reached a random entry is thrown out
344 ??? One might want to try to make this smarter, but let's see some
345 measurable benefit first. */
348 scache_lookup_or_alloc (SIM_CPU
*cpu
, IADDR pc
, int n
, SCACHE
**bufp
)
350 /* FIXME: hash computation is wrong, doesn't take into account
351 NUM_HASH_CHAIN_ENTRIES. A lot of the hash table will be unused! */
352 unsigned int slot
= HASH_PC (pc
) & (CPU_SCACHE_NUM_HASH_CHAINS (cpu
) - 1);
353 int i
, max_i
= CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu
);
357 scm
= & CPU_SCACHE_HASH_TABLE (cpu
) [slot
];
358 for (i
= 0; i
< max_i
&& scm
->pc
!= UNUSED_ADDR
; ++i
, ++scm
)
362 PROFILE_COUNT_SCACHE_HIT (cpu
);
366 PROFILE_COUNT_SCACHE_MISS (cpu
);
368 /* The address we want isn't cached. Bummer.
369 If the hash chain we have for this address is full, throw out an entry
374 /* Rather than do something sophisticated like LRU, we just throw out
375 a semi-random entry. Let someone else have the joy of saying how
376 wrong this is. NEXT_FREE is the entry to throw out and cycles
377 through all possibilities. */
378 static int next_free
= 0;
380 scm
= & CPU_SCACHE_HASH_TABLE (cpu
) [slot
];
381 /* FIXME: This seems rather clumsy. */
382 for (i
= 0; i
< next_free
; ++i
, ++scm
)
385 if (next_free
== CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu
))
389 /* At this point SCM points to the hash table entry to use.
390 Now make sure there's room in the cache. */
391 /* FIXME: Kinda weird to use a next_free adjusted scm when cache is
395 int elm_size
= IMP_PROPS_SCACHE_ELM_SIZE (MACH_IMP_PROPS (CPU_MACH (cpu
)));
396 int elms_used
= (((char *) CPU_SCACHE_NEXT_FREE (cpu
)
397 - (char *) CPU_SCACHE_CACHE (cpu
))
399 int elms_left
= CPU_SCACHE_SIZE (cpu
) - elms_used
;
403 PROFILE_COUNT_SCACHE_FULL_FLUSH (cpu
);
404 scache_flush_cpu (cpu
);
408 sc
= CPU_SCACHE_NEXT_FREE (cpu
);
416 #endif /* WITH_SCACHE_PBB */
418 /* Print cache access statics for CPU. */
421 scache_print_profile (SIM_CPU
*cpu
, int verbose
)
423 SIM_DESC sd
= CPU_STATE (cpu
);
424 unsigned long hits
= CPU_SCACHE_HITS (cpu
);
425 unsigned long misses
= CPU_SCACHE_MISSES (cpu
);
427 unsigned long max_val
;
428 unsigned long *lengths
;
431 if (CPU_SCACHE_SIZE (cpu
) == 0)
434 sim_io_printf (sd
, "Simulator Cache Statistics\n\n");
436 /* One could use PROFILE_LABEL_WIDTH here. I chose not to. */
437 sim_io_printf (sd
, " Cache size: %s\n",
438 sim_add_commas (buf
, sizeof (buf
), CPU_SCACHE_SIZE (cpu
)));
439 sim_io_printf (sd
, " Hits: %s\n",
440 sim_add_commas (buf
, sizeof (buf
), hits
));
441 sim_io_printf (sd
, " Misses: %s\n",
442 sim_add_commas (buf
, sizeof (buf
), misses
));
443 if (hits
+ misses
!= 0)
444 sim_io_printf (sd
, " Hit rate: %.2f%%\n",
445 ((double) hits
/ ((double) hits
+ (double) misses
)) * 100);
448 sim_io_printf (sd
, "\n");
449 sim_io_printf (sd
, " Hash table size: %s\n",
450 sim_add_commas (buf
, sizeof (buf
), CPU_SCACHE_NUM_HASH_CHAINS (cpu
)));
451 sim_io_printf (sd
, " Max hash list length: %s\n",
452 sim_add_commas (buf
, sizeof (buf
), CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu
)));
453 sim_io_printf (sd
, " Max insn chain length: %s\n",
454 sim_add_commas (buf
, sizeof (buf
), CPU_SCACHE_MAX_CHAIN_LENGTH (cpu
)));
455 sim_io_printf (sd
, " Cache full flushes: %s\n",
456 sim_add_commas (buf
, sizeof (buf
), CPU_SCACHE_FULL_FLUSHES (cpu
)));
457 sim_io_printf (sd
, "\n");
461 sim_io_printf (sd
, " Insn chain lengths:\n\n");
463 lengths
= CPU_SCACHE_CHAIN_LENGTHS (cpu
);
464 for (i
= 1; i
< CPU_SCACHE_MAX_CHAIN_LENGTH (cpu
); ++i
)
465 if (lengths
[i
] > max_val
)
466 max_val
= lengths
[i
];
467 for (i
= 1; i
< CPU_SCACHE_MAX_CHAIN_LENGTH (cpu
); ++i
)
469 sim_io_printf (sd
, " %2d: %*s: ",
471 max_val
< 10000 ? 5 : 10,
472 sim_add_commas (buf
, sizeof (buf
), lengths
[i
]));
473 sim_profile_print_bar (sd
, cpu
, PROFILE_HISTOGRAM_WIDTH
,
474 lengths
[i
], max_val
);
475 sim_io_printf (sd
, "\n");
477 sim_io_printf (sd
, "\n");
479 #endif /* WITH_SCACHE_PBB */