1 # Generate the main loop of the simulator.
2 # Copyright (C) 1996-2021 Free Software Foundation, Inc.
3 # Contributed by Cygnus Support.
5 # This file is part of the GNU simulators.
7 # This program is free software; you can redistribute it and/or modify
8 # it under the terms of the GNU General Public License as published by
9 # the Free Software Foundation; either version 3 of the License, or
10 # (at your option) any later version.
12 # This program is distributed in the hope that it will be useful,
13 # but WITHOUT ANY WARRANTY; without even the implied warranty of
14 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 # GNU General Public License for more details.
17 # You should have received a copy of the GNU General Public License
18 # along with this program. If not, see <http://www.gnu.org/licenses/>.
20 # This file creates two files: eng.hin and mloop.cin.
21 # eng.hin defines a few macros that specify what kind of engine was selected
22 # based on the arguments to this script.
23 # mloop.cin contains the engine.
25 # ??? Rename mloop.c to eng.c?
26 # ??? Rename mainloop.in to engine.in?
27 # ??? Add options to specify output file names?
28 # ??? Rename this file to genengine.sh?
30 # Syntax: genmloop.sh [options]
35 # - specify single cpu or multiple cpus (number specifyable at runtime),
36 # maximum number is a configuration parameter
39 # -fast: include support for fast execution in addition to full featured mode
41 # Full featured mode is for tracing, profiling, etc. and is always
42 # provided. Fast mode contains no frills, except speed.
43 # A target need only provide a "full" version of one of
44 # simple,scache,pbb. If the target wants it can also provide a fast
45 # version of same. It can't provide more than this.
46 # ??? Later add ability to have another set of full/fast semantics
47 # for use in with-devices/with-smp situations (pbb can be inappropriate
50 # -full-switch: same as -fast but for full featured version of -switch
51 # Only needed if -fast present.
53 # -simple: simple execution engine (the default)
55 # This engine fetches and executes one instruction at a time.
56 # Field extraction is done in the semantic routines.
58 # ??? There are two possible flavours of -simple. One that extracts
59 # fields in the semantic routine (which is what is implemented here),
60 # and one that stores the extracted fields in ARGBUF before calling the
61 # semantic routine. The latter is essentially the -scache case with a
62 # cache size of one (and the scache lookup code removed). There are no
63 # current uses of this and it's not clear when doing this would be a win.
64 # More complicated ISA's that want to use -simple may find this a win.
65 # Should this ever be desirable, implement a new engine style here and
66 # call it -extract (or some such). It's believed that the CGEN-generated
67 # code for the -scache case would be usable here, so no new code
68 # generation option would be needed for CGEN.
70 # -scache: use the scache to speed things up (not always a win)
72 # This engine caches the extracted instruction before executing it.
73 # When executing instructions they are first looked up in the scache.
75 # -pbb: same as -scache but extract a (pseudo-) basic block at a time
77 # This engine is basically identical to the scache version except that
78 # extraction is done a pseudo-basic-block at a time and the address of
79 # the scache entry of a branch target is recorded as well.
80 # Additional speedups are then possible by defering Ctrl-C checking
81 # to the end of basic blocks and by threading the insns together.
82 # We call them pseudo-basic-block's instead of just basic-blocks because
83 # they're not necessarily basic-blocks, though normally are.
85 # -parallel-read: support parallel execution with read-before-exec support.
86 # -parallel-write: support parallel execution with write-after-exec support.
87 # -parallel-generic-write: support parallel execution with generic queued
90 # One of these options is specified in addition to -simple, -scache,
91 # -pbb. Note that while the code can determine if the cpu supports
92 # parallel execution with HAVE_PARALLEL_INSNS [and thus this option is
93 # technically unnecessary], having this option cuts down on the clutter
96 # -parallel-only: semantic code only supports parallel version of insn
98 # Semantic code only supports parallel versions of each insn.
99 # Things can be sped up by generating both serial and parallel versions
100 # and is better suited to mixed parallel architectures like the m32r.
102 # -prefix: string to prepend to function names in mloop.c/eng.h.
104 # If no prefix is specified, the cpu type is used.
106 # -switch file: specify file containing semantics implemented as a switch()
110 # Specify the cpu family name.
112 # -infile <input-file>
114 # Specify the mainloop.in input file.
116 # -outfile-suffix <output-file-suffix>
118 # Specify the suffix to append to output files.
122 # Specify the shell to use to execute <input-file>
124 # Only one of -scache/-pbb may be selected.
125 # -simple is the default.
130 # - build mainloop.in from .cpu file
150 -multi) type=multi
;;
153 -full-switch) full_switch
=yes ;;
155 -scache) scache
=yes ;;
158 -outfile-prefix) shift ; outprefix
=$1 ;;
159 -outfile-suffix) shift ; outsuffix
=$1 ;;
160 -parallel-read) parallel
=read ;;
161 -parallel-write) parallel
=write ;;
162 -parallel-generic-write) parallel
=genwrite
;;
163 -parallel-only) parallel_only
=yes ;;
164 -prefix) shift ; prefix
=$1 ;;
165 -switch) shift ; switch
=$1 ;;
166 -cpu) shift ; cpu
=$1 ;;
167 -infile) shift ; infile
=$1 ;;
168 -shell) shift ; SHELL
=$1 ;;
169 *) echo "unknown option: $1" >&2 ; exit 1 ;;
174 # Argument validation.
176 if [ x
$scache = xyes
-a x
$pbb = xyes
] ; then
177 echo "only one of -scache and -pbb may be selected" >&2
181 if [ "x$cpu" = xunknown
] ; then
182 echo "cpu family not specified" >&2
186 if [ "x$infile" = x
] ; then
187 echo "mainloop.in not specified" >&2
191 if [ "x$prefix" = xunknown
] ; then
195 lowercase
='abcdefghijklmnopqrstuvwxyz'
196 uppercase
='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
197 CPU
=`echo ${cpu} | tr "${lowercase}" "${uppercase}"`
198 PREFIX
=`echo ${prefix} | tr "${lowercase}" "${uppercase}"`
200 ##########################################################################
202 rm -f ${outprefix}eng
${outsuffix}.hin
203 exec 1>${outprefix}eng
${outsuffix}.hin
205 echo "/* engine configuration for ${cpu} */"
208 echo "/* WITH_FAST: non-zero if a fast version of the engine is available"
209 echo " in addition to the full-featured version. */"
210 if [ x
$fast = xyes
] ; then
211 echo "#define WITH_FAST 1"
213 echo "#define WITH_FAST 0"
217 echo "/* WITH_SCACHE_PBB_${PREFIX}: non-zero if the pbb engine was selected. */"
218 if [ x
$pbb = xyes
] ; then
219 echo "#define WITH_SCACHE_PBB_${PREFIX} 1"
221 echo "#define WITH_SCACHE_PBB_${PREFIX} 0"
225 echo "/* HAVE_PARALLEL_INSNS: non-zero if cpu can parallelly execute > 1 insn. */"
226 # blah blah blah, other ways to do this, blah blah blah
229 echo "#define HAVE_PARALLEL_INSNS 0"
230 echo "#define WITH_PARALLEL_READ 0"
231 echo "#define WITH_PARALLEL_WRITE 0"
232 echo "#define WITH_PARALLEL_GENWRITE 0"
235 echo "#define HAVE_PARALLEL_INSNS 1"
236 echo "/* Parallel execution is supported by read-before-exec. */"
237 echo "#define WITH_PARALLEL_READ 1"
238 echo "#define WITH_PARALLEL_WRITE 0"
239 echo "#define WITH_PARALLEL_GENWRITE 0"
242 echo "#define HAVE_PARALLEL_INSNS 1"
243 echo "/* Parallel execution is supported by write-after-exec. */"
244 echo "#define WITH_PARALLEL_READ 0"
245 echo "#define WITH_PARALLEL_WRITE 1"
246 echo "#define WITH_PARALLEL_GENWRITE 0"
249 echo "#define HAVE_PARALLEL_INSNS 1"
250 echo "/* Parallel execution is supported by generic write-after-exec. */"
251 echo "#define WITH_PARALLEL_READ 0"
252 echo "#define WITH_PARALLEL_WRITE 0"
253 echo "#define WITH_PARALLEL_GENWRITE 1"
257 if [ "x$switch" != x
] ; then
259 echo "/* WITH_SEM_SWITCH_FULL: non-zero if full-featured engine is"
260 echo " implemented as a switch(). */"
261 if [ x
$fast != xyes
-o x
$full_switch = xyes
] ; then
262 echo "#define WITH_SEM_SWITCH_FULL 1"
264 echo "#define WITH_SEM_SWITCH_FULL 0"
267 echo "/* WITH_SEM_SWITCH_FAST: non-zero if fast engine is"
268 echo " implemented as a switch(). */"
269 if [ x
$fast = xyes
] ; then
270 echo "#define WITH_SEM_SWITCH_FAST 1"
272 echo "#define WITH_SEM_SWITCH_FAST 0"
276 # Decls of functions we define.
279 echo "/* Functions defined in the generated mainloop.c file"
280 echo " (which doesn't necessarily have that file name). */"
282 echo "extern ENGINE_FN ${prefix}_engine_run_full;"
283 echo "extern ENGINE_FN ${prefix}_engine_run_fast;"
285 if [ x
$pbb = xyes
] ; then
287 echo "extern SEM_PC ${prefix}_pbb_begin (SIM_CPU *, int);"
288 echo "extern SEM_PC ${prefix}_pbb_chain (SIM_CPU *, SEM_ARG);"
289 echo "extern SEM_PC ${prefix}_pbb_cti_chain (SIM_CPU *, SEM_ARG, SEM_BRANCH_TYPE, PCADDR);"
290 echo "extern void ${prefix}_pbb_before (SIM_CPU *, SCACHE *);"
291 echo "extern void ${prefix}_pbb_after (SIM_CPU *, SCACHE *);"
294 ##########################################################################
296 rm -f ${outprefix}tmp-mloop-$$.cin ${outprefix}mloop${outsuffix}.cin
297 exec 1>${outprefix}tmp-mloop-$$.cin
299 # We use @cpu@ instead of ${cpu} because we still need to run sed to handle
300 # transformation of @cpu@ for mainloop.in, so there's no need to use ${cpu}
304 /* This file is generated by the genmloop script. DO NOT EDIT! */
306 /* This must come before any other includes. */
309 /* Enable switch() support in cgen headers. */
310 #define SEM_IN_SWITCH
312 #define WANT_CPU @cpu@
313 #define WANT_CPU_@CPU@
315 #include "sim-main.h"
317 #include "cgen-mem.h"
318 #include "cgen-ops.h"
319 #include "sim-assert.h"
321 /* Fill in the administrative ARGBUF fields required by all insns,
325 @prefix@_fill_argbuf (const SIM_CPU *cpu, ARGBUF *abuf, const IDESC *idesc,
326 PCADDR pc, int fast_p)
329 SEM_SET_CODE (abuf, idesc, fast_p);
330 ARGBUF_ADDR (abuf) = pc;
332 ARGBUF_IDESC (abuf) = idesc;
335 /* Fill in tracing/profiling fields of an ARGBUF. */
338 @prefix@_fill_argbuf_tp (const SIM_CPU *cpu, ARGBUF *abuf,
339 int trace_p, int profile_p)
341 ARGBUF_TRACE_P (abuf) = trace_p;
342 ARGBUF_PROFILE_P (abuf) = profile_p;
347 /* Emit the "x-before" handler.
348 x-before is emitted before each insn (serial or parallel).
349 This is as opposed to x-after which is only emitted at the end of a group
350 of parallel insns. */
352 ATTRIBUTE_UNUSED static INLINE void
353 @prefix@_emit_before (SIM_CPU *current_cpu, SCACHE *sc, PCADDR pc, int first_p)
355 ARGBUF *abuf = &sc[0].argbuf;
356 const IDESC *id = & CPU_IDESC (current_cpu) [@PREFIX@_INSN_X_BEFORE];
358 abuf->fields.before.first_p = first_p;
359 @prefix@_fill_argbuf (current_cpu, abuf, id, pc, 0);
360 /* no need to set trace_p,profile_p */
363 /* Emit the "x-after" handler.
364 x-after is emitted after a serial insn or at the end of a group of
367 ATTRIBUTE_UNUSED static INLINE void
368 @prefix@_emit_after (SIM_CPU *current_cpu, SCACHE *sc, PCADDR pc)
370 ARGBUF *abuf = &sc[0].argbuf;
371 const IDESC *id = & CPU_IDESC (current_cpu) [@PREFIX@_INSN_X_AFTER];
373 @prefix@_fill_argbuf (current_cpu, abuf, id, pc, 0);
374 /* no need to set trace_p,profile_p */
377 #endif /* WITH_SCACHE_PBB */
381 ${SHELL} $infile support
383 ##########################################################################
385 # Simple engine: fetch an instruction, execute the instruction.
387 # Instruction fields are not extracted into ARGBUF, they are extracted in
388 # the semantic routines themselves. However, there is still a need to pass
389 # and return misc. information to the semantic routines so we still use ARGBUF.
390 # [One could certainly implement things differently and remove ARGBUF.
391 # It's not clear this is necessarily always a win.]
392 # ??? The use of the SCACHE struct is for consistency with the with-scache
393 # case though it might be a source of confusion.
395 if [ x
$scache != xyes
-a x
$pbb != xyes
] ; then
402 @prefix@_engine_run_full (SIM_CPU *current_cpu)
405 SIM_DESC current_state = CPU_STATE (current_cpu);
406 /* ??? Use of SCACHE is a bit of a hack as we don't actually use the scache.
407 We do however use ARGBUF so for consistency with the other engine flavours
408 the SCACHE type is used. */
409 SCACHE cache[MAX_LIW_INSNS];
410 SCACHE *sc = &cache[0];
417 PAREXEC pbufs[MAX_PARALLEL_INSNS];
424 # Any initialization code before looping starts.
425 # Note that this code may declare some locals.
426 ${SHELL} $infile init
428 if [ x
$parallel = xread
] ; then
431 #if defined (__GNUC__)
433 if (! CPU_IDESC_READ_INIT_P (current_cpu))
435 /* ??? Later maybe paste read.c in when building mainloop.c. */
436 #define DEFINE_LABELS
438 CPU_IDESC_READ_INIT_P (current_cpu) = 1;
448 if (! CPU_IDESC_SEM_INIT_P (current_cpu))
450 #if WITH_SEM_SWITCH_FULL
451 #if defined (__GNUC__)
452 /* ??? Later maybe paste sem-switch.c in when building mainloop.c. */
453 #define DEFINE_LABELS
457 @prefix@_sem_init_idesc_table (current_cpu);
459 CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
464 /* begin full-exec-simple */
467 ${SHELL} $infile full-exec-simple
470 /* end full-exec-simple */
472 ++ CPU_INSN_COUNT (current_cpu);
474 while (0 /*CPU_RUNNING_P (current_cpu)*/);
481 ####################################
483 # Simple engine: fast version.
484 # ??? A somewhat dubious effort, but for completeness' sake.
486 if [ x
$fast = xyes
] ; then
492 FIXME: "fast simple version unimplemented, delete -fast arg to genmloop.sh."
502 ##########################################################################
504 # Non-parallel scache engine: lookup insn in scache, fetch if missing,
507 if [ x
$scache = xyes
-a x
$parallel = xno
] ; then
511 static INLINE SCACHE *
512 @prefix@_scache_lookup (SIM_CPU *current_cpu, PCADDR vpc, SCACHE *scache,
513 unsigned int hash_mask, int FAST_P)
515 /* First step: look up current insn in hash table. */
516 SCACHE *sc = scache + SCACHE_HASH_PC (vpc, hash_mask);
518 /* If the entry isn't the one we want (cache miss),
519 fetch and decode the instruction. */
520 if (sc->argbuf.addr != vpc)
523 PROFILE_COUNT_SCACHE_MISS (current_cpu);
525 /* begin extract-scache */
528 ${SHELL} $infile extract-scache
531 /* end extract-scache */
535 PROFILE_COUNT_SCACHE_HIT (current_cpu);
536 /* Make core access statistics come out right.
537 The size is a guess, but it's currently not used either. */
538 PROFILE_COUNT_CORE (current_cpu, vpc, 2, exec_map);
547 @prefix@_engine_run_full (SIM_CPU *current_cpu)
549 SIM_DESC current_state = CPU_STATE (current_cpu);
550 SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
551 unsigned int hash_mask = CPU_SCACHE_HASH_MASK (current_cpu);
556 # Any initialization code before looping starts.
557 # Note that this code may declare some locals.
558 ${SHELL} $infile init
562 if (! CPU_IDESC_SEM_INIT_P (current_cpu))
564 #if ! WITH_SEM_SWITCH_FULL
565 @prefix@_sem_init_idesc_table (current_cpu);
567 CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
576 sc = @prefix@_scache_lookup (current_cpu, vpc, scache, hash_mask, FAST_P);
578 /* begin full-exec-scache */
581 ${SHELL} $infile full-exec-scache
584 /* end full-exec-scache */
588 ++ CPU_INSN_COUNT (current_cpu);
590 while (0 /*CPU_RUNNING_P (current_cpu)*/);
597 ####################################
599 # Non-parallel scache engine: fast version.
601 if [ x
$fast = xyes
] ; then
608 @prefix@_engine_run_fast (SIM_CPU *current_cpu)
610 SIM_DESC current_state = CPU_STATE (current_cpu);
611 SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
612 unsigned int hash_mask = CPU_SCACHE_HASH_MASK (current_cpu);
617 # Any initialization code before looping starts.
618 # Note that this code may declare some locals.
619 ${SHELL} $infile init
623 if (! CPU_IDESC_SEM_INIT_P (current_cpu))
625 #if WITH_SEM_SWITCH_FAST
626 #if defined (__GNUC__)
627 /* ??? Later maybe paste sem-switch.c in when building mainloop.c. */
628 #define DEFINE_LABELS
632 @prefix@_semf_init_idesc_table (current_cpu);
634 CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
643 sc = @prefix@_scache_lookup (current_cpu, vpc, scache, hash_mask, FAST_P);
645 /* begin fast-exec-scache */
648 ${SHELL} $infile fast-exec-scache
651 /* end fast-exec-scache */
655 ++ CPU_INSN_COUNT (current_cpu);
657 while (0 /*CPU_RUNNING_P (current_cpu)*/);
666 fi # -scache && ! parallel
668 ##########################################################################
670 # Parallel scache engine: lookup insn in scache, fetch if missing,
672 # For the parallel case we give the target more flexibility.
674 if [ x
$scache = xyes
-a x
$parallel != xno
] ; then
678 static INLINE SCACHE *
679 @prefix@_scache_lookup (SIM_CPU *current_cpu, PCADDR vpc, SCACHE *scache,
680 unsigned int hash_mask, int FAST_P)
682 /* First step: look up current insn in hash table. */
683 SCACHE *sc = scache + SCACHE_HASH_PC (vpc, hash_mask);
685 /* If the entry isn't the one we want (cache miss),
686 fetch and decode the instruction. */
687 if (sc->argbuf.addr != vpc)
690 PROFILE_COUNT_SCACHE_MISS (current_cpu);
692 #define SET_LAST_INSN_P(last_p) do { sc->last_insn_p = (last_p); } while (0)
693 /* begin extract-scache */
696 ${SHELL} $infile extract-scache
699 /* end extract-scache */
700 #undef SET_LAST_INSN_P
704 PROFILE_COUNT_SCACHE_HIT (current_cpu);
705 /* Make core access statistics come out right.
706 The size is a guess, but it's currently not used either. */
707 PROFILE_COUNT_CORE (current_cpu, vpc, 2, exec_map);
716 @prefix@_engine_run_full (SIM_CPU *current_cpu)
718 SIM_DESC current_state = CPU_STATE (current_cpu);
719 SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
720 unsigned int hash_mask = CPU_SCACHE_HASH_MASK (current_cpu);
725 # Any initialization code before looping starts.
726 # Note that this code may declare some locals.
727 ${SHELL} $infile init
729 if [ x
$parallel = xread
] ; then
731 #if defined (__GNUC__)
733 if (! CPU_IDESC_READ_INIT_P (current_cpu))
735 /* ??? Later maybe paste read.c in when building mainloop.c. */
736 #define DEFINE_LABELS
738 CPU_IDESC_READ_INIT_P (current_cpu) = 1;
748 if (! CPU_IDESC_SEM_INIT_P (current_cpu))
750 #if ! WITH_SEM_SWITCH_FULL
751 @prefix@_sem_init_idesc_table (current_cpu);
753 CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
760 /* begin full-exec-scache */
763 ${SHELL} $infile full-exec-scache
766 /* end full-exec-scache */
768 while (0 /*CPU_RUNNING_P (current_cpu)*/);
775 ####################################
777 # Parallel scache engine: fast version.
779 if [ x
$fast = xyes
] ; then
786 @prefix@_engine_run_fast (SIM_CPU *current_cpu)
788 SIM_DESC current_state = CPU_STATE (current_cpu);
789 SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
790 unsigned int hash_mask = CPU_SCACHE_HASH_MASK (current_cpu);
792 PAREXEC pbufs[MAX_PARALLEL_INSNS];
797 # Any initialization code before looping starts.
798 # Note that this code may declare some locals.
799 ${SHELL} $infile init
801 if [ x
$parallel = xread
] ; then
804 #if defined (__GNUC__)
806 if (! CPU_IDESC_READ_INIT_P (current_cpu))
808 /* ??? Later maybe paste read.c in when building mainloop.c. */
809 #define DEFINE_LABELS
811 CPU_IDESC_READ_INIT_P (current_cpu) = 1;
821 if (! CPU_IDESC_SEM_INIT_P (current_cpu))
823 #if WITH_SEM_SWITCH_FAST
824 #if defined (__GNUC__)
825 /* ??? Later maybe paste sem-switch.c in when building mainloop.c. */
826 #define DEFINE_LABELS
830 @prefix@_semf_init_idesc_table (current_cpu);
832 CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
839 /* begin fast-exec-scache */
842 ${SHELL} $infile fast-exec-scache
845 /* end fast-exec-scache */
847 while (0 /*CPU_RUNNING_P (current_cpu)*/);
856 fi # -scache && parallel
858 ##########################################################################
860 # Compilation engine: lookup insn in scache, extract a pbb
861 # (pseudo-basic-block) if missing, then execute the pbb.
862 # A "pbb" is a sequence of insns up to the next cti insn or until
863 # some prespecified maximum.
864 # CTI: control transfer instruction.
866 if [ x
$pbb = xyes
] ; then
870 /* Record address of cti terminating a pbb. */
871 #define SET_CTI_VPC(sc) do { _cti_sc = (sc); } while (0)
872 /* Record number of [real] insns in pbb. */
873 #define SET_INSN_COUNT(n) do { _insn_count = (n); } while (0)
875 /* Fetch and extract a pseudo-basic-block.
876 FAST_P is non-zero if no tracing/profiling/etc. is wanted. */
879 @prefix@_pbb_begin (SIM_CPU *current_cpu, int FAST_P)
884 int max_insns = CPU_SCACHE_MAX_CHAIN_LENGTH (current_cpu);
888 new_vpc = scache_lookup_or_alloc (current_cpu, pc, max_insns, &sc);
891 /* Leading '_' to avoid collision with mainloop.in. */
893 SCACHE *orig_sc = sc;
894 SCACHE *_cti_sc = NULL;
895 int slice_insns = CPU_MAX_SLICE_INSNS (current_cpu);
897 /* First figure out how many instructions to compile.
898 MAX_INSNS is the size of the allocated buffer, which includes space
899 for before/after handlers if they're being used.
900 SLICE_INSNS is the maxinum number of real insns that can be
901 executed. Zero means "as many as we want". */
902 /* ??? max_insns is serving two incompatible roles.
903 1) Number of slots available in scache buffer.
904 2) Number of real insns to execute.
905 They're incompatible because there are virtual insns emitted too
906 (chain,cti-chain,before,after handlers). */
908 if (slice_insns == 1)
910 /* No need to worry about extra slots required for virtual insns
911 and parallel exec support because MAX_CHAIN_LENGTH is
912 guaranteed to be big enough to execute at least 1 insn! */
917 /* Allow enough slop so that while compiling insns, if max_insns > 0
918 then there's guaranteed to be enough space to emit one real insn.
919 MAX_CHAIN_LENGTH is typically much longer than
920 the normal number of insns between cti's anyway. */
921 max_insns -= (1 /* one for the trailing chain insn */
924 : (1 + MAX_PARALLEL_INSNS) /* before+after */)
925 + (MAX_PARALLEL_INSNS > 1
926 ? (MAX_PARALLEL_INSNS * 2)
929 /* Account for before/after handlers. */
934 && slice_insns < max_insns)
935 max_insns = slice_insns;
940 /* SC,PC must be updated to point passed the last entry used.
941 SET_CTI_VPC must be called if pbb is terminated by a cti.
942 SET_INSN_COUNT must be called to record number of real insns in
943 pbb [could be computed by us of course, extra cpu but perhaps
944 negligible enough]. */
946 /* begin extract-pbb */
949 ${SHELL} $infile extract-pbb
952 /* end extract-pbb */
954 /* The last one is a pseudo-insn to link to the next chain.
955 It is also used to record the insn count for this chain. */
959 /* Was pbb terminated by a cti? */
962 id = & CPU_IDESC (current_cpu) [@PREFIX@_INSN_X_CTI_CHAIN];
966 id = & CPU_IDESC (current_cpu) [@PREFIX@_INSN_X_CHAIN];
968 SEM_SET_CODE (&sc->argbuf, id, FAST_P);
969 sc->argbuf.idesc = id;
970 sc->argbuf.addr = pc;
971 sc->argbuf.fields.chain.insn_count = _insn_count;
972 sc->argbuf.fields.chain.next = 0;
973 sc->argbuf.fields.chain.branch_target = 0;
977 /* Update the pointer to the next free entry, may not have used as
978 many entries as was asked for. */
979 CPU_SCACHE_NEXT_FREE (current_cpu) = sc;
980 /* Record length of chain if profiling.
981 This includes virtual insns since they count against
984 PROFILE_COUNT_SCACHE_CHAIN_LENGTH (current_cpu, sc - orig_sc);
990 /* Chain to the next block from a non-cti terminated previous block. */
993 @prefix@_pbb_chain (SIM_CPU *current_cpu, SEM_ARG sem_arg)
995 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
997 PBB_UPDATE_INSN_COUNT (current_cpu, sem_arg);
999 SET_H_PC (abuf->addr);
1001 /* If not running forever, exit back to main loop. */
1002 if (CPU_MAX_SLICE_INSNS (current_cpu) != 0
1003 /* Also exit back to main loop if there's an event.
1004 Note that if CPU_MAX_SLICE_INSNS != 1, events won't get processed
1005 at the "right" time, but then that was what was asked for.
1006 There is no silver bullet for simulator engines.
1007 ??? Clearly this needs a cleaner interface.
1008 At present it's just so Ctrl-C works. */
1009 || STATE_EVENTS (CPU_STATE (current_cpu))->work_pending)
1010 CPU_RUNNING_P (current_cpu) = 0;
1012 /* If chained to next block, go straight to it. */
1013 if (abuf->fields.chain.next)
1014 return abuf->fields.chain.next;
1015 /* See if next block has already been compiled. */
1016 abuf->fields.chain.next = scache_lookup (current_cpu, abuf->addr);
1017 if (abuf->fields.chain.next)
1018 return abuf->fields.chain.next;
1019 /* Nope, so next insn is a virtual insn to invoke the compiler
1021 return CPU_SCACHE_PBB_BEGIN (current_cpu);
1024 /* Chain to the next block from a cti terminated previous block.
1025 BR_TYPE indicates whether the branch was taken and whether we can cache
1026 the vpc of the branch target.
1027 NEW_PC is the target's branch address, and is only valid if
1028 BR_TYPE != SEM_BRANCH_UNTAKEN. */
1031 @prefix@_pbb_cti_chain (SIM_CPU *current_cpu, SEM_ARG sem_arg,
1032 SEM_BRANCH_TYPE br_type, PCADDR new_pc)
1034 SEM_PC *new_vpc_ptr;
1036 PBB_UPDATE_INSN_COUNT (current_cpu, sem_arg);
1038 /* If not running forever, exit back to main loop. */
1039 if (CPU_MAX_SLICE_INSNS (current_cpu) != 0
1040 /* Also exit back to main loop if there's an event.
1041 Note that if CPU_MAX_SLICE_INSNS != 1, events won't get processed
1042 at the "right" time, but then that was what was asked for.
1043 There is no silver bullet for simulator engines.
1044 ??? Clearly this needs a cleaner interface.
1045 At present it's just so Ctrl-C works. */
1046 || STATE_EVENTS (CPU_STATE (current_cpu))->work_pending)
1047 CPU_RUNNING_P (current_cpu) = 0;
1049 /* Restart compiler if we branched to an uncacheable address
1051 if (br_type == SEM_BRANCH_UNCACHEABLE)
1054 return CPU_SCACHE_PBB_BEGIN (current_cpu);
1057 /* If branch wasn't taken, update the pc and set BR_ADDR_PTR to our
1059 if (br_type == SEM_BRANCH_UNTAKEN)
1061 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1062 new_pc = abuf->addr;
1064 new_vpc_ptr = &abuf->fields.chain.next;
1068 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1070 new_vpc_ptr = &abuf->fields.chain.branch_target;
1073 /* If chained to next block, go straight to it. */
1075 return *new_vpc_ptr;
1076 /* See if next block has already been compiled. */
1077 *new_vpc_ptr = scache_lookup (current_cpu, new_pc);
1079 return *new_vpc_ptr;
1080 /* Nope, so next insn is a virtual insn to invoke the compiler
1082 return CPU_SCACHE_PBB_BEGIN (current_cpu);
1085 /* x-before handler.
1086 This is called before each insn. */
1089 @prefix@_pbb_before (SIM_CPU *current_cpu, SCACHE *sc)
1091 SEM_ARG sem_arg = sc;
1092 const ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1093 int first_p = abuf->fields.before.first_p;
1094 const ARGBUF *cur_abuf = SEM_ARGBUF (sc + 1);
1095 const IDESC *cur_idesc = cur_abuf->idesc;
1096 PCADDR pc = cur_abuf->addr;
1098 if (ARGBUF_PROFILE_P (cur_abuf))
1099 PROFILE_COUNT_INSN (current_cpu, pc, cur_idesc->num);
1101 /* If this isn't the first insn, finish up the previous one. */
1105 if (PROFILE_MODEL_P (current_cpu))
1107 const SEM_ARG prev_sem_arg = sc - 1;
1108 const ARGBUF *prev_abuf = SEM_ARGBUF (prev_sem_arg);
1109 const IDESC *prev_idesc = prev_abuf->idesc;
1112 /* ??? May want to measure all insns if doing insn tracing. */
1113 if (ARGBUF_PROFILE_P (prev_abuf))
1115 cycles = (*prev_idesc->timing->model_fn) (current_cpu, prev_sem_arg);
1116 @prefix@_model_insn_after (current_cpu, 0 /*last_p*/, cycles);
1120 CGEN_TRACE_INSN_FINI (current_cpu, cur_abuf, 0 /*last_p*/);
1123 /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */
1124 if (PROFILE_MODEL_P (current_cpu)
1125 && ARGBUF_PROFILE_P (cur_abuf))
1126 @prefix@_model_insn_before (current_cpu, first_p);
1128 CGEN_TRACE_INSN_INIT (current_cpu, cur_abuf, first_p);
1129 CGEN_TRACE_INSN (current_cpu, cur_idesc->idata, cur_abuf, pc);
1133 This is called after a serial insn or at the end of a group of parallel
1137 @prefix@_pbb_after (SIM_CPU *current_cpu, SCACHE *sc)
1139 SEM_ARG sem_arg = sc;
1140 const ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1141 const SEM_ARG prev_sem_arg = sc - 1;
1142 const ARGBUF *prev_abuf = SEM_ARGBUF (prev_sem_arg);
1144 /* ??? May want to measure all insns if doing insn tracing. */
1145 if (PROFILE_MODEL_P (current_cpu)
1146 && ARGBUF_PROFILE_P (prev_abuf))
1148 const IDESC *prev_idesc = prev_abuf->idesc;
1151 cycles = (*prev_idesc->timing->model_fn) (current_cpu, prev_sem_arg);
1152 @prefix@_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
1154 CGEN_TRACE_INSN_FINI (current_cpu, prev_abuf, 1 /*last_p*/);
1160 @prefix@_engine_run_full (SIM_CPU *current_cpu)
1162 SIM_DESC current_state = CPU_STATE (current_cpu);
1163 SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
1164 /* virtual program counter */
1166 #if WITH_SEM_SWITCH_FULL
1167 /* For communication between cti's and cti-chain. */
1168 SEM_BRANCH_TYPE pbb_br_type;
1177 PAREXEC pbufs[MAX_PARALLEL_INSNS];
1178 PAREXEC *par_exec = &pbufs[0];
1184 # Any initialization code before looping starts.
1185 # Note that this code may declare some locals.
1186 ${SHELL} $infile init
1190 if (! CPU_IDESC_SEM_INIT_P (current_cpu))
1192 /* ??? 'twould be nice to move this up a level and only call it once.
1193 On the other hand, in the "let's go fast" case the test is only done
1194 once per pbb (since we only return to the main loop at the end of
1195 a pbb). And in the "let's run until we're done" case we don't return
1196 until the program exits. */
1198 #if WITH_SEM_SWITCH_FULL
1199 #if defined (__GNUC__)
1200 /* ??? Later maybe paste sem-switch.c in when building mainloop.c. */
1201 #define DEFINE_LABELS
1205 @prefix@_sem_init_idesc_table (current_cpu);
1208 /* Initialize the "begin (compile) a pbb" virtual insn. */
1209 vpc = CPU_SCACHE_PBB_BEGIN (current_cpu);
1210 SEM_SET_FULL_CODE (SEM_ARGBUF (vpc),
1211 & CPU_IDESC (current_cpu) [@PREFIX@_INSN_X_BEGIN]);
1212 vpc->argbuf.idesc = & CPU_IDESC (current_cpu) [@PREFIX@_INSN_X_BEGIN];
1214 CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
1217 CPU_RUNNING_P (current_cpu) = 1;
1218 /* ??? In the case where we're returning to the main loop after every
1219 pbb we don't want to call pbb_begin each time (which hashes on the pc
1220 and does a table lookup). A way to speed this up is to save vpc
1222 vpc = @prefix@_pbb_begin (current_cpu, FAST_P);
1226 /* begin full-exec-pbb */
1229 ${SHELL} $infile full-exec-pbb
1232 /* end full-exec-pbb */
1234 while (CPU_RUNNING_P (current_cpu));
1241 ####################################
1243 # Compile engine: fast version.
1245 if [ x
$fast = xyes
] ; then
1252 @prefix@_engine_run_fast (SIM_CPU *current_cpu)
1254 SIM_DESC current_state = CPU_STATE (current_cpu);
1255 SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
1256 /* virtual program counter */
1258 #if WITH_SEM_SWITCH_FAST
1259 /* For communication between cti's and cti-chain. */
1260 SEM_BRANCH_TYPE pbb_br_type;
1269 PAREXEC pbufs[MAX_PARALLEL_INSNS];
1270 PAREXEC *par_exec = &pbufs[0];
1276 # Any initialization code before looping starts.
1277 # Note that this code may declare some locals.
1278 ${SHELL} $infile init
1282 if (! CPU_IDESC_SEM_INIT_P (current_cpu))
1284 /* ??? 'twould be nice to move this up a level and only call it once.
1285 On the other hand, in the "let's go fast" case the test is only done
1286 once per pbb (since we only return to the main loop at the end of
1287 a pbb). And in the "let's run until we're done" case we don't return
1288 until the program exits. */
1290 #if WITH_SEM_SWITCH_FAST
1291 #if defined (__GNUC__)
1292 /* ??? Later maybe paste sem-switch.c in when building mainloop.c. */
1293 #define DEFINE_LABELS
1297 @prefix@_semf_init_idesc_table (current_cpu);
1300 /* Initialize the "begin (compile) a pbb" virtual insn. */
1301 vpc = CPU_SCACHE_PBB_BEGIN (current_cpu);
1302 SEM_SET_FAST_CODE (SEM_ARGBUF (vpc),
1303 & CPU_IDESC (current_cpu) [@PREFIX@_INSN_X_BEGIN]);
1304 vpc->argbuf.idesc = & CPU_IDESC (current_cpu) [@PREFIX@_INSN_X_BEGIN];
1306 CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
1309 CPU_RUNNING_P (current_cpu) = 1;
1310 /* ??? In the case where we're returning to the main loop after every
1311 pbb we don't want to call pbb_begin each time (which hashes on the pc
1312 and does a table lookup). A way to speed this up is to save vpc
1314 vpc = @prefix@_pbb_begin (current_cpu, FAST_P);
1318 /* begin fast-exec-pbb */
1321 ${SHELL} $infile fast-exec-pbb
1324 /* end fast-exec-pbb */
1326 while (CPU_RUNNING_P (current_cpu));
1336 # Expand @..@ macros appearing in tmp-mloop-{pid}.cin.
1338 -e "s/@cpu@/$cpu/g" -e "s/@CPU@/$CPU/g" \
1339 -e "s/@prefix@/$prefix/g" -e "s/@PREFIX@/$PREFIX/g" \
1340 < ${outprefix}tmp-mloop-$$.cin > ${outprefix}mloop${outsuffix}.cin
1342 rm -f ${outprefix}tmp-mloop-$$.cin