1 /* Simulator pseudo baseclass.
2 Copyright (C) 1997 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
22 /* Simulator state pseudo baseclass.
24 Each simulator is required to have the file ``sim-main.h''. That
25 file includes ``sim-basics.h'', defines the base type ``sim_cia''
26 (the data type that contains complete current instruction address
27 information), include ``sim-base.h'':
29 #include "sim-basics.h"
30 typedef address_word sim_cia;
33 finally, two data types ``struct _sim_cpu' and ``struct sim_state'
37 ... simulator specific members ...
42 sim_cpu cpu[MAX_NR_PROCESSORS];
44 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
46 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
48 ... simulator specific members ...
52 Note that `base' appears last. This makes `base.magic' appear last
53 in the entire struct and helps catch miscompilation errors. */
59 /* Pre-declare certain types. */
61 /* typedef <target-dependant> sim_cia; */
63 #define NULL_CIA ((sim_cia) 0)
65 #ifndef INVALID_INSTRUCTION_ADDRESS
66 #define INVALID_INSTRUCTION_ADDRESS ((address_word)0 - 1)
68 typedef struct _sim_cpu sim_cpu
;
70 #include "sim-module.h"
72 #include "sim-trace.h"
73 #include "sim-profile.h"
74 #include "sim-model.h"
76 #include "sim-events.h"
78 #include "sim-engine.h"
79 #include "sim-watch.h"
82 /* Global pointer to current state while sim_resume is running.
83 On a machine with lots of registers, it might be possible to reserve
84 one of them for current_state. However on a machine with few registers
85 current_state can't permanently live in one and indirecting through it
86 will be slower [in which case one can have sim_resume set globals from
87 current_state for faster access].
88 If CURRENT_STATE_REG is defined, it means current_state is living in
92 #ifdef CURRENT_STATE_REG
95 extern struct sim_state
*current_state
;
99 /* The simulator may provide different (and faster) definition. */
100 #ifndef CURRENT_STATE
101 #define CURRENT_STATE current_state
107 /* Simulator's argv[0]. */
109 #define STATE_MY_NAME(sd) ((sd)->base.my_name)
111 /* Who opened the simulator. */
112 SIM_OPEN_KIND open_kind
;
113 #define STATE_OPEN_KIND(sd) ((sd)->base.open_kind)
115 /* The host callbacks. */
116 struct host_callback_struct
*callback
;
117 #define STATE_CALLBACK(sd) ((sd)->base.callback)
119 #if 0 /* FIXME: Not ready yet. */
120 /* Stuff defined in sim-config.h. */
121 struct sim_config config
;
122 #define STATE_CONFIG(sd) ((sd)->base.config)
125 /* List of installed module `init' handlers. */
126 MODULE_INIT_LIST
*init_list
;
127 #define STATE_INIT_LIST(sd) ((sd)->base.init_list)
128 /* List of installed module `uninstall' handlers. */
129 MODULE_UNINSTALL_LIST
*uninstall_list
;
130 #define STATE_UNINSTALL_LIST(sd) ((sd)->base.uninstall_list)
132 /* ??? This might be more appropriate in sim_cpu. */
133 /* Machine tables for this cpu. See sim-model.h. */
135 #define STATE_MODEL(sd) ((sd)->base.model)
137 /* Supported options. */
138 struct option_list
*options
;
139 #define STATE_OPTIONS(sd) ((sd)->base.options)
141 /* Non-zero if -v specified. */
143 #define STATE_VERBOSE_P(sd) ((sd)->base.verbose_p)
145 /* If non NULL, the BFD architecture specified on the command line */
146 const struct bfd_arch_info
*architecture
;
147 #define STATE_ARCHITECTURE(sd) ((sd)->base.architecture)
149 /* If non NULL, the bfd target specified on the command line */
151 #define STATE_TARGET(sd) ((sd)->base.target)
153 /* In standalone simulator, this is the program's arguments passed
154 on the command line. */
156 #define STATE_PROG_ARGV(sd) ((sd)->base.prog_argv)
158 /* The program's bfd. */
159 struct _bfd
*prog_bfd
;
160 #define STATE_PROG_BFD(sd) ((sd)->base.prog_bfd)
162 /* The program's text section. */
163 struct sec
*text_section
;
164 /* Starting and ending text section addresses from the bfd. */
165 SIM_ADDR text_start
, text_end
;
166 #define STATE_TEXT_SECTION(sd) ((sd)->base.text_section)
167 #define STATE_TEXT_START(sd) ((sd)->base.text_start)
168 #define STATE_TEXT_END(sd) ((sd)->base.text_end)
170 /* Start address, set when the program is loaded from the bfd. */
172 #define STATE_START_ADDR(sd) ((sd)->base.start_addr)
175 /* Size of the simulator's cache, if any.
176 This is not the target's cache. It is the cache the simulator uses
177 to process instructions. */
178 unsigned int scache_size
;
179 #define STATE_SCACHE_SIZE(sd) ((sd)->base.scache_size)
182 /* FIXME: Move to top level sim_state struct (as some struct)? */
183 #ifdef SIM_HAVE_FLATMEM
184 unsigned int mem_size
;
185 #define STATE_MEM_SIZE(sd) ((sd)->base.mem_size)
186 unsigned int mem_base
;
187 #define STATE_MEM_BASE(sd) ((sd)->base.mem_base)
188 unsigned char *memory
;
189 #define STATE_MEMORY(sd) ((sd)->base.memory)
192 /* core memory bus */
193 #define STATE_CORE(sd) (&(sd)->base.core)
197 #define STATE_EVENTS(sd) (&(sd)->base.events)
200 /* generic halt/resume engine */
202 #define STATE_ENGINE(sd) (&(sd)->base.engine)
204 /* generic watchpoint support */
205 sim_watchpoints watchpoints
;
206 #define STATE_WATCHPOINTS(sd) (&(sd)->base.watchpoints)
208 /* Marker for those wanting to do sanity checks.
209 This should remain the last member of this struct to help catch
210 miscompilation errors. */
212 #define SIM_MAGIC_NUMBER 0x4242
213 #define STATE_MAGIC(sd) ((sd)->base.magic)
218 /* Pseudo baseclass for each cpu. */
222 /* Backlink to main state struct. */
224 #define CPU_STATE(cpu) ((cpu)->base.state)
226 /* Processor specific core data */
228 #define CPU_CORE(cpu) (& (cpu)->base.core)
230 /* Trace data. See sim-trace.h. */
231 TRACE_DATA trace_data
;
232 #define CPU_TRACE_DATA(cpu) (& (cpu)->base.trace_data)
234 /* Maximum number of debuggable entities.
235 This debugging is not intended for normal use.
236 It is only enabled when the simulator is configured with --with-debug
237 which shouldn't normally be specified. */
238 #ifndef MAX_DEBUG_VALUES
239 #define MAX_DEBUG_VALUES 4
242 /* Boolean array of specified debugging flags. */
243 char debug_flags
[MAX_DEBUG_VALUES
];
244 #define CPU_DEBUG_FLAGS(cpu) ((cpu)->base.debug_flags)
245 /* Standard values. */
246 #define DEBUG_INSN_IDX 0
247 #define DEBUG_NEXT_IDX 2 /* simulator specific debug bits begin here */
249 /* Debugging output goes to this or stderr if NULL.
250 We can't store `stderr' here as stderr goes through a callback. */
252 #define CPU_DEBUG_FILE(cpu) ((cpu)->base.debug_file)
254 /* Profile data. See sim-profile.h. */
255 PROFILE_DATA profile_data
;
256 #define CPU_PROFILE_DATA(cpu) (& (cpu)->base.profile_data)
261 /* Functions for allocating/freeing a sim_state. */
262 SIM_DESC sim_state_alloc
PARAMS ((SIM_OPEN_KIND kind
, host_callback
*callback
));
263 void sim_state_free
PARAMS ((SIM_DESC
));
266 #endif /* SIM_BASE_H */