sim/common/sim-core.h

   1 /*  This file is part of the program psim.
   2
   3     Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
   4
   5     This program is free software; you can redistribute it and/or modify
   6     it under the terms of the GNU General Public License as published by
   7     the Free Software Foundation; either version 2 of the License, or
   8     (at your option) any later version.
   9
  10     This program is distributed in the hope that it will be useful,
  11     but WITHOUT ANY WARRANTY; without even the implied warranty of
  12     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13     GNU General Public License for more details.
  14
  15     You should have received a copy of the GNU General Public License
  16     along with this program; if not, write to the Free Software
  17     Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18
  19     */
  20
  21
  22 #ifndef _SIM_CORE_H_
  23 #define _SIM_CORE_H_
  24
  25
  26 /* core signals (error conditions) */
  27
  28 typedef enum {
  29   sim_core_unmapped_signal,
  30   sim_core_unaligned_signal,
  31   nr_sim_core_signals,
  32 } sim_core_signals;
  33
  34 /* define SIM_CORE_SIGNAL to catch these signals - see sim-core.c for
  35    details */
  36
  37
  38
  39 /* basic types */
  40
  41 typedef struct _sim_core_mapping sim_core_mapping;
  42 struct _sim_core_mapping {
  43   /* common */
  44   int level;
  45   int space;
  46   unsigned_word base;
  47   unsigned_word bound;
  48   unsigned_word nr_bytes;
  49   unsigned mask;
  50   /* memory map */
  51   void *free_buffer;
  52   void *buffer;
  53   /* callback map */
  54   device *device;
  55   /* tracing */
  56   int trace;
  57   /* growth */
  58   sim_core_mapping *next;
  59 };
  60
  61 typedef struct _sim_core_map sim_core_map;
  62 struct _sim_core_map {
  63   sim_core_mapping *first;
  64 };
  65
  66 typedef enum {
  67   sim_core_read_map,
  68   sim_core_write_map,
  69   sim_core_execute_map,
  70   nr_sim_core_maps,
  71 } sim_core_maps;
  72
  73
  74 typedef struct _sim_core_common {
  75   sim_core_map map[nr_sim_core_maps];
  76 } sim_core_common;
  77
  78
  79 /* Main core structure */
  80
  81 typedef struct _sim_core sim_core;
  82 struct _sim_core {
  83   sim_core_common common;
  84   address_word byte_xor; /* apply xor universally */
  85 };
  86
  87
  88 /* Per CPU distributed component of the core.  At present this is
  89    mostly a clone of the global core data structure. */
  90
  91 typedef struct _sim_cpu_core {
  92   sim_core_common common;
  93   address_word xor[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero-sized array */
  94 } sim_cpu_core;
  95
  96
  97 /* Install the "core" module.  */
  98
  99 EXTERN_SIM_CORE\
 100 (SIM_RC) sim_core_install (SIM_DESC sd);
 101
 102
 103
 104 /* Create a memory space within the core.
 105
 106    CPU, when non NULL, specifes the single processor that the memory
 107    space is to be attached to. (UNIMPLEMENTED).
 108
 109    LEVEL specifies the ordering of the memory region.  Lower regions
 110    are searched first.  Within a level, memory regions can not
 111    overlap.
 112
 113    DEVICE, when non NULL, specifies a callback memory space.
 114    (UNIMPLEMENTED, see the ppc simulator for an example).
 115
 116    MODULO, when the simulator has been configured WITH_MODULO support
 117    and is greater than zero, specifies that accesses to the region
 118    [ADDR .. ADDR+NR_BYTES) should be mapped onto the sub region [ADDR
 119    .. ADDR+MODULO).  The modulo value must be a power of two.
 120
 121    OPTIONAL_BUFFER, when non NULL, specifies the buffer to use for
 122    data read & written to the region.  Normally a more efficient
 123    internal structure is used.  It is assumed that buffer is allocated
 124    such that the byte alignmed of OPTIONAL_BUFFER matches ADDR vis
 125    (OPTIONAL_BUFFER % 8) == (ADDR % 8)) */
 126
 127 EXTERN_SIM_CORE\
 128 (void) sim_core_attach
 129 (SIM_DESC sd,
 130  sim_cpu *cpu,
 131  int level,
 132  access_type access,
 133  int address_space,
 134  address_word addr,
 135  address_word nr_bytes,
 136  unsigned modulo,
 137  device *client,
 138  void *optional_buffer);
 139
 140
 141 /* Delete a memory space within the core.
 142
 143  */
 144
 145 EXTERN_SIM_CORE\
 146 (void) sim_core_detach
 147 (SIM_DESC sd,
 148  sim_cpu *cpu,
 149  int level,
 150  int address_space,
 151  address_word addr);
 152
 153
 154 /* Variable sized read/write
 155
 156    Transfer a variable sized block of raw data between the host and
 157    target.  Should any problems occure, the number of bytes
 158    successfully transfered is returned.
 159
 160    No host/target byte endian conversion is performed.  No xor-endian
 161    conversion is performed.
 162
 163    If CPU argument, when non NULL, specifies the processor specific
 164    address map that is to be used in the transfer. */
 165
 166
 167 EXTERN_SIM_CORE\
 168 (unsigned) sim_core_read_buffer
 169 (SIM_DESC sd,
 170  sim_cpu *cpu,
 171  sim_core_maps map,
 172  void *buffer,
 173  address_word addr,
 174  unsigned nr_bytes);
 175
 176 EXTERN_SIM_CORE\
 177 (unsigned) sim_core_write_buffer
 178 (SIM_DESC sd,
 179  sim_cpu *cpu,
 180  sim_core_maps map,
 181  const void *buffer,
 182  address_word addr,
 183  unsigned nr_bytes);
 184
 185
 186
 187 /* Configure the core's XOR endian transfer mode.  Only applicable
 188    when WITH_XOR_ENDIAN is enabled.
 189
 190    Targets suporting XOR endian, shall notify the core of any changes
 191    in state via this call.
 192
 193    The CPU argument, when non NULL, specifes the single processor that
 194    the xor-endian configuration is to be applied to. */
 195
 196 EXTERN_SIM_CORE\
 197 (void) sim_core_set_xor\
 198 (SIM_DESC sd,
 199  sim_cpu *cpu,
 200  int is_xor);
 201
 202
 203 /* XOR version of variable sized read/write.
 204
 205    Transfer a variable sized block of raw data between the host and
 206    target.  Should any problems occure, the number of bytes
 207    successfully transfered is returned.
 208
 209    No host/target byte endian conversion is performed.  If applicable
 210    (WITH_XOR_ENDIAN and xor-endian set), xor-endian conversion *is*
 211    performed.
 212
 213    If CPU argument, when non NULL, specifies the processor specific
 214    address map that is to be used in the transfer. */
 215
 216 EXTERN_SIM_CORE\
 217 (unsigned) sim_core_xor_read_buffer
 218 (SIM_DESC sd,
 219  sim_cpu *cpu,
 220  sim_core_maps map,
 221  void *buffer,
 222  address_word addr,
 223  unsigned nr_bytes);
 224
 225 EXTERN_SIM_CORE\
 226 (unsigned) sim_core_xor_write_buffer
 227 (SIM_DESC sd,
 228  sim_cpu *cpu,
 229  sim_core_maps map,
 230  const void *buffer,
 231  address_word addr,
 232  unsigned nr_bytes);
 233
 234
 235
 236 /* Fixed sized, processor oriented, read/write.
 237
 238    Transfer a fixed amout of memory between the host and target.  The
 239    data transfered is translated from/to host to/from target byte
 240    order (including xor endian).  Should the transfer fail, the
 241    operation shall abort (no return).
 242
 243    The aligned alternative makes the assumption that that the address
 244    is N byte aligned (no alignment checks are made).
 245
 246    The unaligned alternative checks the address for correct byte
 247    alignment.  Action, as defined by WITH_ALIGNMENT, being taken
 248    should the check fail.
 249
 250    Misaligned xor-endian accesses are broken into a sequence of
 251    transfers each <= WITH_XOR_ENDIAN bytes */
 252
 253
 254 #define DECLARE_SIM_CORE_WRITE_N(ALIGNMENT,N) \
 255 INLINE_SIM_CORE\
 256 (void) sim_core_write_##ALIGNMENT##_##N \
 257 (sim_cpu *cpu, \
 258  sim_cia cia, \
 259  sim_core_maps map, \
 260  address_word addr, \
 261  unsigned_##N val);
 262
 263 DECLARE_SIM_CORE_WRITE_N(aligned,1)
 264 DECLARE_SIM_CORE_WRITE_N(aligned,2)
 265 DECLARE_SIM_CORE_WRITE_N(aligned,4)
 266 DECLARE_SIM_CORE_WRITE_N(aligned,8)
 267 DECLARE_SIM_CORE_WRITE_N(aligned,16)
 268
 269 DECLARE_SIM_CORE_WRITE_N(unaligned,1)
 270 DECLARE_SIM_CORE_WRITE_N(unaligned,2)
 271 DECLARE_SIM_CORE_WRITE_N(unaligned,4)
 272 DECLARE_SIM_CORE_WRITE_N(unaligned,8)
 273 DECLARE_SIM_CORE_WRITE_N(unaligned,16)
 274
 275
 276 #define sim_core_write_1 sim_core_write_aligned_1
 277 #define sim_core_write_2 sim_core_write_aligned_2
 278 #define sim_core_write_4 sim_core_write_aligned_4
 279 #define sim_core_write_8 sim_core_write_aligned_8
 280 #define sim_core_write_16 sim_core_write_aligned_16
 281
 282 #define sim_core_write_unaligned_word XCONCAT2(sim_core_write_unaligned_,WITH_TARGET_WORD_BITSIZE)
 283 #define sim_core_write_aligned_word XCONCAT2(sim_core_write_aligned_,WITH_TARGET_WORD_BITSIZE)
 284 #define sim_core_write_word XCONCAT2(sim_core_write_,WITH_TARGET_WORD_BITSIZE)
 285
 286 #undef DECLARE_SIM_CORE_WRITE_N
 287
 288
 289 #define DECLARE_SIM_CORE_READ_N(ALIGNMENT,N) \
 290 INLINE_SIM_CORE\
 291 (unsigned_##N) sim_core_read_##ALIGNMENT##_##N \
 292 (sim_cpu *cpu, \
 293  sim_cia cia, \
 294  sim_core_maps map, \
 295  address_word addr);
 296
 297 DECLARE_SIM_CORE_READ_N(aligned,1)
 298 DECLARE_SIM_CORE_READ_N(aligned,2)
 299 DECLARE_SIM_CORE_READ_N(aligned,4)
 300 DECLARE_SIM_CORE_READ_N(aligned,8)
 301 DECLARE_SIM_CORE_READ_N(aligned,16)
 302
 303 DECLARE_SIM_CORE_READ_N(unaligned,1)
 304 DECLARE_SIM_CORE_READ_N(unaligned,2)
 305 DECLARE_SIM_CORE_READ_N(unaligned,4)
 306 DECLARE_SIM_CORE_READ_N(unaligned,8)
 307 DECLARE_SIM_CORE_READ_N(unaligned,16)
 308
 309 #define sim_core_read_1 sim_core_read_aligned_1
 310 #define sim_core_read_2 sim_core_read_aligned_2
 311 #define sim_core_read_4 sim_core_read_aligned_4
 312 #define sim_core_read_8 sim_core_read_aligned_8
 313 #define sim_core_read_16 sim_core_read_aligned_16
 314
 315 #define sim_core_read_unaligned_word XCONCAT2(sim_core_read_unaligned_,WITH_TARGET_WORD_BITSIZE)
 316 #define sim_core_read_aligned_word XCONCAT2(sim_core_read_aligned_,WITH_TARGET_WORD_BITSIZE)
 317 #define sim_core_read_word XCONCAT2(sim_core_read_,WITH_TARGET_WORD_BITSIZE)
 318
 319 #undef DECLARE_SIM_CORE_READ_N
 320
 321 #endif