sim/common/sim-core.h

   1 /*  This file is part of the program psim.
   2
   3     Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
   4
   5     This program is free software; you can redistribute it and/or modify
   6     it under the terms of the GNU General Public License as published by
   7     the Free Software Foundation; either version 2 of the License, or
   8     (at your option) any later version.
   9
  10     This program is distributed in the hope that it will be useful,
  11     but WITHOUT ANY WARRANTY; without even the implied warranty of
  12     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13     GNU General Public License for more details.
  14
  15     You should have received a copy of the GNU General Public License
  16     along with this program; if not, write to the Free Software
  17     Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18
  19     */
  20
  21
  22 #ifndef _SIM_CORE_H_
  23 #define _SIM_CORE_H_
  24
  25
  26 /* core signals (error conditions) */
  27
  28 typedef enum {
  29   sim_core_unmapped_signal,
  30   sim_core_unaligned_signal,
  31   nr_sim_core_signals,
  32 } sim_core_signals;
  33
  34 /* define SIM_CORE_SIGNAL to catch these signals - see sim-core.c for
  35    details */
  36
  37
  38
  39 /* basic types */
  40
  41 typedef struct _sim_core_mapping sim_core_mapping;
  42 struct _sim_core_mapping {
  43   /* common */
  44   int level;
  45   int space;
  46   unsigned_word base;
  47   unsigned_word bound;
  48   unsigned_word nr_bytes;
  49   unsigned mask;
  50   /* memory map */
  51   void *free_buffer;
  52   void *buffer;
  53   /* callback map */
  54   device *device;
  55   /* tracing */
  56   int trace;
  57   /* growth */
  58   sim_core_mapping *next;
  59 };
  60
  61 typedef struct _sim_core_map sim_core_map;
  62 struct _sim_core_map {
  63   sim_core_mapping *first;
  64 };
  65
  66 typedef enum {
  67   sim_core_read_map,
  68   sim_core_write_map,
  69   sim_core_execute_map,
  70   nr_sim_core_maps,
  71 } sim_core_maps;
  72
  73
  74 typedef struct _sim_core_common {
  75   sim_core_map map[nr_sim_core_maps];
  76 } sim_core_common;
  77
  78
  79 /* Main core structure */
  80
  81 typedef struct _sim_core sim_core;
  82 struct _sim_core {
  83   sim_core_common common;
  84   address_word byte_xor; /* apply xor universally */
  85 };
  86
  87
  88 /* Per CPU distributed component of the core.  At present this is
  89    mostly a clone of the global core data structure. */
  90
  91 typedef struct _sim_cpu_core {
  92   sim_core_common common;
  93   address_word xor[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero-sized array */
  94 } sim_cpu_core;
  95
  96
  97 /* Install the "core" module.  */
  98
  99 EXTERN_SIM_CORE\
 100 (SIM_RC) sim_core_install (SIM_DESC sd);
 101
 102
 103
 104 /* Create a memory space within the core.
 105
 106    The CPU option (when non NULL) specifes the single processor that
 107    the memory space is to be attached to. (UNIMPLEMENTED).
 108
 109    */
 110
 111 EXTERN_SIM_CORE\
 112 (void) sim_core_attach
 113 (SIM_DESC sd,
 114  sim_cpu *cpu,
 115  attach_type attach,
 116  access_type access,
 117  int address_space,
 118  address_word addr,
 119  address_word nr_bytes,
 120  unsigned modulo, /* Power of two, zero for none. */
 121  device *client,
 122  void *optional_buffer);
 123
 124 /* Delete a memory space within the core.
 125
 126  */
 127
 128 EXTERN_SIM_CORE\
 129 (void) sim_core_detach
 130 (SIM_DESC sd,
 131  sim_cpu *cpu,
 132  attach_type attach,
 133  int address_space,
 134  address_word addr);
 135
 136
 137 /* Variable sized read/write
 138
 139    Transfer a variable sized block of raw data between the host and
 140    target.  Should any problems occure, the number of bytes
 141    successfully transfered is returned.
 142
 143    No host/target byte endian conversion is performed.  No xor-endian
 144    conversion is performed.
 145
 146    If CPU argument, when non NULL, specifies the processor specific
 147    address map that is to be used in the transfer. */
 148
 149
 150 EXTERN_SIM_CORE\
 151 (unsigned) sim_core_read_buffer
 152 (SIM_DESC sd,
 153  sim_cpu *cpu,
 154  sim_core_maps map,
 155  void *buffer,
 156  address_word addr,
 157  unsigned nr_bytes);
 158
 159 EXTERN_SIM_CORE\
 160 (unsigned) sim_core_write_buffer
 161 (SIM_DESC sd,
 162  sim_cpu *cpu,
 163  sim_core_maps map,
 164  const void *buffer,
 165  address_word addr,
 166  unsigned nr_bytes);
 167
 168
 169
 170 /* Configure the core's XOR endian transfer mode.  Only applicable
 171    when WITH_XOR_ENDIAN is enabled.
 172
 173    Targets suporting XOR endian, shall notify the core of any changes
 174    in state via this call.
 175
 176    The CPU argument, when non NULL, specifes the single processor that
 177    the xor-endian configuration is to be applied to. */
 178
 179 EXTERN_SIM_CORE\
 180 (void) sim_core_set_xor\
 181 (SIM_DESC sd,
 182  sim_cpu *cpu,
 183  int is_xor);
 184
 185
 186 /* XOR version of variable sized read/write.
 187
 188    Transfer a variable sized block of raw data between the host and
 189    target.  Should any problems occure, the number of bytes
 190    successfully transfered is returned.
 191
 192    No host/target byte endian conversion is performed.  If applicable
 193    (WITH_XOR_ENDIAN and xor-endian set), xor-endian conversion *is*
 194    performed.
 195
 196    If CPU argument, when non NULL, specifies the processor specific
 197    address map that is to be used in the transfer. */
 198
 199 EXTERN_SIM_CORE\
 200 (unsigned) sim_core_xor_read_buffer
 201 (SIM_DESC sd,
 202  sim_cpu *cpu,
 203  sim_core_maps map,
 204  void *buffer,
 205  address_word addr,
 206  unsigned nr_bytes);
 207
 208 EXTERN_SIM_CORE\
 209 (unsigned) sim_core_xor_write_buffer
 210 (SIM_DESC sd,
 211  sim_cpu *cpu,
 212  sim_core_maps map,
 213  const void *buffer,
 214  address_word addr,
 215  unsigned nr_bytes);
 216
 217
 218
 219 /* Fixed sized, processor oriented, read/write.
 220
 221    Transfer a fixed amout of memory between the host and target.  The
 222    data transfered is translated from/to host to/from target byte
 223    order (including xor endian).  Should the transfer fail, the
 224    operation shall abort (no return).
 225
 226    The aligned alternative makes the assumption that that the address
 227    is N byte aligned (no alignment checks are made).
 228
 229    The unaligned alternative checks the address for correct byte
 230    alignment.  Action, as defined by WITH_ALIGNMENT, being taken
 231    should the check fail.
 232
 233    Misaligned xor-endian accesses are broken into a sequence of
 234    transfers each <= WITH_XOR_ENDIAN bytes */
 235
 236
 237 #define DECLARE_SIM_CORE_WRITE_N(ALIGNMENT,N) \
 238 INLINE_SIM_CORE\
 239 (void) sim_core_write_##ALIGNMENT##_##N \
 240 (sim_cpu *cpu, \
 241  sim_cia cia, \
 242  sim_core_maps map, \
 243  address_word addr, \
 244  unsigned_##N val);
 245
 246 DECLARE_SIM_CORE_WRITE_N(aligned,1)
 247 DECLARE_SIM_CORE_WRITE_N(aligned,2)
 248 DECLARE_SIM_CORE_WRITE_N(aligned,4)
 249 DECLARE_SIM_CORE_WRITE_N(aligned,8)
 250 DECLARE_SIM_CORE_WRITE_N(aligned,word)
 251
 252 DECLARE_SIM_CORE_WRITE_N(unaligned,1)
 253 DECLARE_SIM_CORE_WRITE_N(unaligned,2)
 254 DECLARE_SIM_CORE_WRITE_N(unaligned,4)
 255 DECLARE_SIM_CORE_WRITE_N(unaligned,8)
 256 DECLARE_SIM_CORE_WRITE_N(unaligned,word)
 257
 258 #define sim_core_write_1 sim_core_write_aligned_1
 259 #define sim_core_write_2 sim_core_write_aligned_2
 260 #define sim_core_write_4 sim_core_write_aligned_4
 261 #define sim_core_write_8 sim_core_write_aligned_8
 262
 263 #undef DECLARE_SIM_CORE_WRITE_N
 264
 265
 266 #define DECLARE_SIM_CORE_READ_N(ALIGNMENT,N) \
 267 INLINE_SIM_CORE\
 268 (unsigned_##N) sim_core_read_##ALIGNMENT##_##N \
 269 (sim_cpu *cpu, \
 270  sim_cia cia, \
 271  sim_core_maps map, \
 272  address_word addr);
 273
 274 DECLARE_SIM_CORE_READ_N(aligned,1)
 275 DECLARE_SIM_CORE_READ_N(aligned,2)
 276 DECLARE_SIM_CORE_READ_N(aligned,4)
 277 DECLARE_SIM_CORE_READ_N(aligned,8)
 278 DECLARE_SIM_CORE_READ_N(aligned,word)
 279
 280 DECLARE_SIM_CORE_READ_N(unaligned,1)
 281 DECLARE_SIM_CORE_READ_N(unaligned,2)
 282 DECLARE_SIM_CORE_READ_N(unaligned,4)
 283 DECLARE_SIM_CORE_READ_N(unaligned,8)
 284 DECLARE_SIM_CORE_READ_N(unaligned,word)
 285
 286 #define sim_core_read_1 sim_core_read_aligned_1
 287 #define sim_core_read_2 sim_core_read_aligned_2
 288 #define sim_core_read_4 sim_core_read_aligned_4
 289 #define sim_core_read_8 sim_core_read_aligned_8
 290
 291 #undef DECLARE_SIM_CORE_READ_N
 292
 293 #endif