1 /* Simulation code for the CR16 processor.
2 Copyright (C) 2008-2022 Free Software Foundation, Inc.
3 Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com>
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
25 #include "sim/callback.h"
26 #include "opcode/cr16.h"
29 #define DEBUG_TRACE 0x00000001
30 #define DEBUG_VALUES 0x00000002
31 #define DEBUG_LINE_NUMBER 0x00000004
32 #define DEBUG_MEMSIZE 0x00000008
33 #define DEBUG_INSTRUCTION 0x00000010
34 #define DEBUG_TRAP 0x00000020
35 #define DEBUG_MEMORY 0x00000040
38 #define DEBUG (DEBUG_TRACE | DEBUG_VALUES | DEBUG_LINE_NUMBER)
41 extern int cr16_debug
;
44 #include "sim-config.h"
45 #include "sim-types.h"
47 /* FIXME: CR16 defines */
48 typedef uint16_t reg_t
;
49 typedef uint32_t creg_t
;
59 void (*func
)(SIM_DESC
, SIM_CPU
*);
61 operand_desc operands
[4];
66 INS_UNKNOWN
, /* unknown instruction */
79 extern unsigned long ins_type_counters
[ (int)INS_MAX
];
85 /* Write-back slots */
100 #define SLOT (State.slot)
101 #define SLOT_NR (State.slot_nr)
102 #define SLOT_PEND_MASK(DEST, MSK, VAL) \
105 SLOT[SLOT_NR].dest = &(DEST); \
106 SLOT[SLOT_NR].size = sizeof (DEST); \
107 switch (sizeof (DEST)) \
110 SLOT[SLOT_NR].data._1 = (unsigned_1) (VAL); \
111 SLOT[SLOT_NR].mask._1 = (unsigned_1) (MSK); \
114 SLOT[SLOT_NR].data._2 = (unsigned_2) (VAL); \
115 SLOT[SLOT_NR].mask._2 = (unsigned_2) (MSK); \
118 SLOT[SLOT_NR].data._4 = (unsigned_4) (VAL); \
119 SLOT[SLOT_NR].mask._4 = (unsigned_4) (MSK); \
122 SLOT_NR = (SLOT_NR + 1); \
125 #define SLOT_PEND(DEST, VAL) SLOT_PEND_MASK(DEST, 0, VAL)
126 #define SLOT_DISCARD() (SLOT_NR = 0)
127 #define SLOT_FLUSH() \
131 for (i = 0; i < SLOT_NR; i++) \
133 switch (SLOT[i].size) \
136 *(unsigned_1*) SLOT[i].dest &= SLOT[i].mask._1; \
137 *(unsigned_1*) SLOT[i].dest |= SLOT[i].data._1; \
140 *(unsigned_2*) SLOT[i].dest &= SLOT[i].mask._2; \
141 *(unsigned_2*) SLOT[i].dest |= SLOT[i].data._2; \
144 *(unsigned_4*) SLOT[i].dest &= SLOT[i].mask._4; \
145 *(unsigned_4*) SLOT[i].dest |= SLOT[i].data._4; \
152 #define SLOT_DUMP() \
156 for (i = 0; i < SLOT_NR; i++) \
158 switch (SLOT[i].size) \
161 printf ("SLOT %d *0x%08lx & 0x%02x | 0x%02x\n", i, \
162 (long) SLOT[i].dest, \
163 (unsigned) SLOT[i].mask._1, \
164 (unsigned) SLOT[i].data._1); \
167 printf ("SLOT %d *0x%08lx & 0x%04x | 0x%04x\n", i, \
168 (long) SLOT[i].dest, \
169 (unsigned) SLOT[i].mask._2, \
170 (unsigned) SLOT[i].data._2); \
173 printf ("SLOT %d *0x%08lx & 0x%08x | 0x%08x\n", i, \
174 (long) SLOT[i].dest, \
175 (unsigned) SLOT[i].mask._4, \
176 (unsigned) SLOT[i].data._4); \
179 printf ("SLOT %d *0x%08lx & 0x%08x%08x | 0x%08x%08x\n", i, \
180 (long) SLOT[i].dest, \
181 (unsigned) (SLOT[i].mask._8 >> 32), \
182 (unsigned) SLOT[i].mask._8, \
183 (unsigned) (SLOT[i].data._8 >> 32), \
184 (unsigned) SLOT[i].data._8); \
193 creg_t regs
[16]; /* general-purpose registers */
194 #define GPR(N) (State.regs[(N)] + 0)
195 #define SET_GPR(N,VAL) (State.regs[(N)] = (VAL))
199 ((((uint16_t) State.regs[(N) + 1]) << 16) | (uint16_t) State.regs[(N)]) \
202 #define SET_GPR32(N,VAL) do { \
204 { SET_GPR (N + 1, (VAL) >> 16); SET_GPR (N, ((VAL) & 0xffff));} \
205 else { if ( N == 11) \
206 { SET_GPR (N + 1, ((GPR32 (12)) & 0xffff0000)|((VAL) >> 16)); \
207 SET_GPR (N, ((VAL) & 0xffff));} \
208 else SET_GPR (N, (VAL));} \
211 creg_t cregs
[16]; /* control registers */
212 #define CREG(N) (State.cregs[(N)] + 0)
213 #define SET_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 0)
214 #define SET_HW_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 1)
216 reg_t sp
[2]; /* holding area for SPI(0)/SPU(1) */
217 #define HELD_SP(N) (State.sp[(N)] + 0)
218 #define SET_HELD_SP(N,VAL) SLOT_PEND (State.sp[(N)], (VAL))
221 struct slot slot
[NR_SLOTS
];
231 /* NOTE: everything below this line is not reset by
232 sim_create_inferior() */
234 enum _ins_type ins_type
;
238 extern struct _state State
;
241 extern uint32_t OP
[4];
242 extern uint32_t sign_flag
;
243 extern struct simops Simops
[];
274 #define PSR CREG (PSR_CR)
275 #define SET_PSR(VAL) SET_CREG (PSR_CR, (VAL))
276 #define SET_HW_PSR(VAL) SET_HW_CREG (PSR_CR, (VAL))
277 #define SET_PSR_BIT(MASK,VAL) move_to_cr (sd, cpu, PSR_CR, ~((creg_t) MASK), (VAL) ? (MASK) : 0, 1)
279 #define PSR_SM ((PSR & PSR_SM_BIT) != 0)
280 #define SET_PSR_SM(VAL) SET_PSR_BIT (PSR_SM_BIT, (VAL))
282 #define PSR_I ((PSR & PSR_I_BIT) != 0)
283 #define SET_PSR_I(VAL) SET_PSR_BIT (PSR_I_BIT, (VAL))
285 #define PSR_DB ((PSR & PSR_DB_BIT) != 0)
286 #define SET_PSR_DB(VAL) SET_PSR_BIT (PSR_DB_BIT, (VAL))
288 #define PSR_P ((PSR & PSR_P_BIT) != 0)
289 #define SET_PSR_P(VAL) SET_PSR_BIT (PSR_P_BIT, (VAL))
291 #define PSR_E ((PSR & PSR_E_BIT) != 0)
292 #define SET_PSR_E(VAL) SET_PSR_BIT (PSR_E_BIT, (VAL))
294 #define PSR_N ((PSR & PSR_N_BIT) != 0)
295 #define SET_PSR_N(VAL) SET_PSR_BIT (PSR_N_BIT, (VAL))
297 #define PSR_Z ((PSR & PSR_Z_BIT) != 0)
298 #define SET_PSR_Z(VAL) SET_PSR_BIT (PSR_Z_BIT, (VAL))
300 #define PSR_F ((PSR & PSR_F_BIT) != 0)
301 #define SET_PSR_F(VAL) SET_PSR_BIT (PSR_F_BIT, (VAL))
303 #define PSR_U ((PSR & PSR_U_BIT) != 0)
304 #define SET_PSR_U(VAL) SET_PSR_BIT (PSR_U_BIT, (VAL))
306 #define PSR_L ((PSR & PSR_L_BIT) != 0)
307 #define SET_PSR_L(VAL) SET_PSR_BIT (PSR_L_BIT, (VAL))
309 #define PSR_T ((PSR & PSR_T_BIT) != 0)
310 #define SET_PSR_T(VAL) SET_PSR_BIT (PSR_T_BIT, (VAL))
312 #define PSR_C ((PSR & PSR_C_BIT) != 0)
313 #define SET_PSR_C(VAL) SET_PSR_BIT (PSR_C_BIT, (VAL))
315 /* See simopsc.:move_to_cr() for registers that can not be read-from
316 or assigned-to directly */
318 #define PC CREG (PC_CR)
319 #define SET_PC(VAL) SET_CREG (PC_CR, (VAL))
320 //#define SET_PC(VAL) (State.cregs[PC_CR] = (VAL))
322 #define BPSR CREG (BPSR_CR)
323 #define SET_BPSR(VAL) SET_CREG (BPSR_CR, (VAL))
325 #define BPC CREG (BPC_CR)
326 #define SET_BPC(VAL) SET_CREG (BPC_CR, (VAL))
328 #define DPSR CREG (DPSR_CR)
329 #define SET_DPSR(VAL) SET_CREG (DPSR_CR, (VAL))
331 #define DPC CREG (DPC_CR)
332 #define SET_DPC(VAL) SET_CREG (DPC_CR, (VAL))
334 #define RPT_C CREG (RPT_C_CR)
335 #define SET_RPT_C(VAL) SET_CREG (RPT_C_CR, (VAL))
337 #define RPT_S CREG (RPT_S_CR)
338 #define SET_RPT_S(VAL) SET_CREG (RPT_S_CR, (VAL))
340 #define RPT_E CREG (RPT_E_CR)
341 #define SET_RPT_E(VAL) SET_CREG (RPT_E_CR, (VAL))
343 #define MOD_S CREG (MOD_S_CR)
344 #define SET_MOD_S(VAL) SET_CREG (MOD_S_CR, (VAL))
346 #define MOD_E CREG (MOD_E_CR)
347 #define SET_MOD_E(VAL) SET_CREG (MOD_E_CR, (VAL))
349 #define IBA CREG (IBA_CR)
350 #define SET_IBA(VAL) SET_CREG (IBA_CR, (VAL))
353 #define SIG_CR16_STOP -1
354 #define SIG_CR16_EXIT -2
355 #define SIG_CR16_BUS -3
356 #define SIG_CR16_IAD -4
358 /* TODO: Resolve conflicts with common headers. */
363 #define SEXT3(x) ((((x)&0x7)^(~3))+4)
365 /* sign-extend a 4-bit number */
366 #define SEXT4(x) ((((x)&0xf)^(~7))+8)
368 /* sign-extend an 8-bit number */
369 #define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80)
371 /* sign-extend a 16-bit number */
372 #define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000)
374 /* sign-extend a 24-bit number */
375 #define SEXT24(x) ((((x)&0xffffff)^(~0x7fffff))+0x800000)
377 /* sign-extend a 32-bit number */
378 #define SEXT32(x) ((((x)&0xffffffff)^(~0x7fffffff))+0x80000000)
380 #define SB(addr, data) sim_core_write_1 (cpu, PC, read_map, addr, data)
381 #define RB(addr) sim_core_read_1 (cpu, PC, read_map, addr)
382 #define SW(addr, data) sim_core_write_unaligned_2 (cpu, PC, read_map, addr, data)
383 #define RW(addr) sim_core_read_unaligned_2 (cpu, PC, read_map, addr)
384 #define SLW(addr, data) sim_core_write_unaligned_4 (cpu, PC, read_map, addr, data)
386 /* Yes, this is as whacked as it looks. The sim currently reads little endian
387 for 16 bits, but then merge them like big endian to get 32 bits. */
388 static inline uint32_t get_longword (SIM_CPU
*cpu
, address_word addr
)
390 return (RW (addr
) << 16) | RW (addr
+ 2);
392 #define RLW(addr) get_longword (cpu, addr)
394 #define JMP(x) do { SET_PC (x); State.pc_changed = 1; } while (0)
396 #define RIE_VECTOR_START 0xffc2
397 #define AE_VECTOR_START 0xffc3
398 #define TRAP_VECTOR_START 0xffc4 /* vector for trap 0 */
399 #define DBT_VECTOR_START 0xffd4
400 #define SDBT_VECTOR_START 0xffd5
402 #define INT_VECTOR_START 0xFFFE00 /*maskable interrupt - mapped to ICU */
403 #define NMI_VECTOR_START 0xFFFF00 /*non-maskable interrupt;for observability*/
404 #define ISE_VECTOR_START 0xFFFC00 /*in-system emulation trap */
405 #define ADBG_VECTOR_START 0xFFFC02 /*alternate debug trap */
406 #define ATRC_VECTOR_START 0xFFFC0C /*alternate trace trap */
407 #define ABPT_VECTOR_START 0xFFFC0E /*alternate break point trap */
410 /* Scedule a store of VAL into cr[CR]. MASK indicates the bits in
411 cr[CR] that should not be modified (i.e. cr[CR] = (cr[CR] & MASK) |
412 (VAL & ~MASK)). In addition, unless PSR_HW_P, a VAL intended for
413 PSR is masked for zero bits. */
415 extern creg_t
move_to_cr (SIM_DESC
, SIM_CPU
*, int cr
, creg_t mask
, creg_t val
, int psw_hw_p
);
420 /* Special purpose trap */
421 #define TRAP_BREAKPOINT 8