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sim: update configure.in->configure.ac docs
[binutils-gdb.git] / sim / cr16 / simops.c
1 /* Simulation code for the CR16 processor.
2 Copyright (C) 2008-2015 Free Software Foundation, Inc.
3 Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com>
4
5 This file is part of GDB, the GNU debugger.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20
21 #include "config.h"
22
23 #include <signal.h>
24 #include <errno.h>
25 #include <sys/types.h>
26 #include <sys/stat.h>
27 #ifdef HAVE_UNISTD_H
28 #include <unistd.h>
29 #endif
30 #ifdef HAVE_STRING_H
31 #include <string.h>
32 #endif
33 #ifdef HAVE_TIME_H
34 #include <time.h>
35 #endif
36 #ifdef HAVE_SYS_TIME_H
37 #include <sys/time.h>
38 #endif
39
40 #include "sim-main.h"
41 #include "simops.h"
42 #include "targ-vals.h"
43
44 #ifdef TARGET_SYS_utime
45 #include <utime.h>
46 #endif
47 #ifdef TARGET_SYS_wait
48 #include <sys/wait.h>
49 #endif
50
51 enum op_types {
52 OP_VOID,
53 OP_CONSTANT3,
54 OP_UCONSTANT3,
55 OP_CONSTANT4,
56 OP_CONSTANT4_1,
57 OP_CONSTANT5,
58 OP_CONSTANT6,
59 OP_CONSTANT16,
60 OP_UCONSTANT16,
61 OP_CONSTANT20,
62 OP_UCONSTANT20,
63 OP_CONSTANT32,
64 OP_UCONSTANT32,
65 OP_MEMREF,
66 OP_MEMREF2,
67 OP_MEMREF3,
68
69 OP_DISP5,
70 OP_DISP17,
71 OP_DISP25,
72 OP_DISPE9,
73 //OP_ABS20,
74 OP_ABS20_OUTPUT,
75 //OP_ABS24,
76 OP_ABS24_OUTPUT,
77
78 OP_R_BASE_DISPS16,
79 OP_R_BASE_DISP20,
80 OP_R_BASE_DISPS20,
81 OP_R_BASE_DISPE20,
82
83 OP_RP_BASE_DISPE0,
84 OP_RP_BASE_DISP4,
85 OP_RP_BASE_DISPE4,
86 OP_RP_BASE_DISP14,
87 OP_RP_BASE_DISP16,
88 OP_RP_BASE_DISP20,
89 OP_RP_BASE_DISPS20,
90 OP_RP_BASE_DISPE20,
91
92 OP_R_INDEX7_ABS20,
93 OP_R_INDEX8_ABS20,
94
95 OP_RP_INDEX_DISP0,
96 OP_RP_INDEX_DISP14,
97 OP_RP_INDEX_DISP20,
98 OP_RP_INDEX_DISPS20,
99
100 OP_REG,
101 OP_REGP,
102 OP_PROC_REG,
103 OP_PROC_REGP,
104 OP_COND,
105 OP_RA
106 };
107
108
109 enum {
110 PSR_MASK = (PSR_I_BIT
111 | PSR_P_BIT
112 | PSR_E_BIT
113 | PSR_N_BIT
114 | PSR_Z_BIT
115 | PSR_F_BIT
116 | PSR_U_BIT
117 | PSR_L_BIT
118 | PSR_T_BIT
119 | PSR_C_BIT),
120 /* The following bits in the PSR _can't_ be set by instructions such
121 as mvtc. */
122 PSR_HW_MASK = (PSR_MASK)
123 };
124
125 /* cond Code Condition True State
126 * EQ Equal Z flag is 1
127 * NE Not Equal Z flag is 0
128 * CS Carry Set C flag is 1
129 * CC Carry Clear C flag is 0
130 * HI Higher L flag is 1
131 * LS Lower or Same L flag is 0
132 * GT Greater Than N flag is 1
133 * LE Less Than or Equal To N flag is 0
134 * FS Flag Set F flag is 1
135 * FC Flag Clear F flag is 0
136 * LO Lower Z and L flags are 0
137 * HS Higher or Same Z or L flag is 1
138 * LT Less Than Z and N flags are 0
139 * GE Greater Than or Equal To Z or N flag is 1. */
140
141 static int cond_stat(int cc)
142 {
143 switch (cc)
144 {
145 case 0: return PSR_Z; break;
146 case 1: return !PSR_Z; break;
147 case 2: return PSR_C; break;
148 case 3: return !PSR_C; break;
149 case 4: return PSR_L; break;
150 case 5: return !PSR_L; break;
151 case 6: return PSR_N; break;
152 case 7: return !PSR_N; break;
153 case 8: return PSR_F; break;
154 case 9: return !PSR_F; break;
155 case 10: return !PSR_Z && !PSR_L; break;
156 case 11: return PSR_Z || PSR_L; break;
157 case 12: return !PSR_Z && !PSR_N; break;
158 case 13: return PSR_Z || PSR_N; break;
159 case 14: return 1; break; /*ALWAYS. */
160 default:
161 // case NEVER: return false; break;
162 //case NO_COND_CODE:
163 //panic("Shouldn't have NO_COND_CODE in an actual instruction!");
164 return 0; break;
165 }
166 return 0;
167 }
168
169
170 creg_t
171 move_to_cr (int cr, creg_t mask, creg_t val, int psw_hw_p)
172 {
173 /* A MASK bit is set when the corresponding bit in the CR should
174 be left alone. */
175 /* This assumes that (VAL & MASK) == 0. */
176 switch (cr)
177 {
178 case PSR_CR:
179 if (psw_hw_p)
180 val &= PSR_HW_MASK;
181 #if 0
182 else
183 val &= PSR_MASK;
184 (*cr16_callback->printf_filtered)
185 (cr16_callback,
186 "ERROR at PC 0x%x: ST can only be set when FX is set.\n", PC);
187 State.exception = SIGILL;
188 #endif
189 /* keep an up-to-date psw around for tracing. */
190 State.trace.psw = (State.trace.psw & mask) | val;
191 break;
192 default:
193 break;
194 }
195 /* only issue an update if the register is being changed. */
196 if ((State.cregs[cr] & ~mask) != val)
197 SLOT_PEND_MASK (State.cregs[cr], mask, val);
198
199 return val;
200 }
201
202 #ifdef DEBUG
203 static void trace_input_func (const char *name,
204 enum op_types in1,
205 enum op_types in2,
206 enum op_types in3);
207
208 #define trace_input(name, in1, in2, in3) do { if (cr16_debug) trace_input_func (name, in1, in2, in3); } while (0)
209
210 #ifndef SIZE_INSTRUCTION
211 #define SIZE_INSTRUCTION 8
212 #endif
213
214 #ifndef SIZE_OPERANDS
215 #define SIZE_OPERANDS 18
216 #endif
217
218 #ifndef SIZE_VALUES
219 #define SIZE_VALUES 13
220 #endif
221
222 #ifndef SIZE_LOCATION
223 #define SIZE_LOCATION 20
224 #endif
225
226 #ifndef SIZE_PC
227 #define SIZE_PC 4
228 #endif
229
230 #ifndef SIZE_LINE_NUMBER
231 #define SIZE_LINE_NUMBER 2
232 #endif
233
234 static void
235 trace_input_func (const char *name, enum op_types in1, enum op_types in2, enum op_types in3)
236 {
237 char *comma;
238 enum op_types in[3];
239 int i;
240 char buf[1024];
241 char *p;
242 long tmp;
243 char *type;
244 const char *filename;
245 const char *functionname;
246 unsigned int linenumber;
247 bfd_vma byte_pc;
248
249 if ((cr16_debug & DEBUG_TRACE) == 0)
250 return;
251
252 switch (State.ins_type)
253 {
254 default:
255 case INS_UNKNOWN: type = " ?"; break;
256 }
257
258 if ((cr16_debug & DEBUG_LINE_NUMBER) == 0)
259 (*cr16_callback->printf_filtered) (cr16_callback,
260 "0x%.*x %s: %-*s ",
261 SIZE_PC, (unsigned)PC,
262 type,
263 SIZE_INSTRUCTION, name);
264
265 else
266 {
267 extern SIM_DESC trace_sd;
268
269 buf[0] = '\0';
270 byte_pc = PC;
271 if (STATE_TEXT_SECTION (trace_sd)
272 && byte_pc >= STATE_TEXT_START (trace_sd)
273 && byte_pc < STATE_TEXT_END (trace_sd))
274 {
275 filename = (const char *)0;
276 functionname = (const char *)0;
277 linenumber = 0;
278 if (bfd_find_nearest_line (STATE_PROG_BFD (trace_sd),
279 STATE_TEXT_SECTION (trace_sd),
280 (struct bfd_symbol **)0,
281 byte_pc - STATE_TEXT_START (trace_sd),
282 &filename, &functionname, &linenumber))
283 {
284 p = buf;
285 if (linenumber)
286 {
287 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
288 p += strlen (p);
289 }
290 else
291 {
292 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
293 p += SIZE_LINE_NUMBER+2;
294 }
295
296 if (functionname)
297 {
298 sprintf (p, "%s ", functionname);
299 p += strlen (p);
300 }
301 else if (filename)
302 {
303 char *q = strrchr (filename, '/');
304 sprintf (p, "%s ", (q) ? q+1 : filename);
305 p += strlen (p);
306 }
307
308 if (*p == ' ')
309 *p = '\0';
310 }
311 }
312
313 (*cr16_callback->printf_filtered) (cr16_callback,
314 "0x%.*x %s: %-*.*s %-*s ",
315 SIZE_PC, (unsigned)PC,
316 type,
317 SIZE_LOCATION, SIZE_LOCATION, buf,
318 SIZE_INSTRUCTION, name);
319 }
320
321 in[0] = in1;
322 in[1] = in2;
323 in[2] = in3;
324 comma = "";
325 p = buf;
326 for (i = 0; i < 3; i++)
327 {
328 switch (in[i])
329 {
330 case OP_VOID:
331 break;
332
333 case OP_REG:
334 case OP_REGP:
335 sprintf (p, "%sr%d", comma, OP[i]);
336 p += strlen (p);
337 comma = ",";
338 break;
339
340 case OP_PROC_REG:
341 sprintf (p, "%scr%d", comma, OP[i]);
342 p += strlen (p);
343 comma = ",";
344 break;
345
346 case OP_CONSTANT16:
347 sprintf (p, "%s%d", comma, OP[i]);
348 p += strlen (p);
349 comma = ",";
350 break;
351
352 case OP_CONSTANT4:
353 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
354 p += strlen (p);
355 comma = ",";
356 break;
357
358 case OP_CONSTANT3:
359 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
360 p += strlen (p);
361 comma = ",";
362 break;
363
364 case OP_MEMREF:
365 sprintf (p, "%s@r%d", comma, OP[i]);
366 p += strlen (p);
367 comma = ",";
368 break;
369
370 case OP_MEMREF2:
371 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
372 p += strlen (p);
373 comma = ",";
374 break;
375
376 case OP_MEMREF3:
377 sprintf (p, "%s@%d", comma, OP[i]);
378 p += strlen (p);
379 comma = ",";
380 break;
381 }
382 }
383
384 if ((cr16_debug & DEBUG_VALUES) == 0)
385 {
386 *p++ = '\n';
387 *p = '\0';
388 (*cr16_callback->printf_filtered) (cr16_callback, "%s", buf);
389 }
390 else
391 {
392 *p = '\0';
393 (*cr16_callback->printf_filtered) (cr16_callback, "%-*s", SIZE_OPERANDS, buf);
394
395 p = buf;
396 for (i = 0; i < 3; i++)
397 {
398 buf[0] = '\0';
399 switch (in[i])
400 {
401 case OP_VOID:
402 (*cr16_callback->printf_filtered) (cr16_callback, "%*s", SIZE_VALUES, "");
403 break;
404
405 case OP_REG:
406 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
407 (uint16) GPR (OP[i]));
408 break;
409
410 case OP_REGP:
411 tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
412 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
413 break;
414
415 case OP_PROC_REG:
416 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
417 (uint16) CREG (OP[i]));
418 break;
419
420 case OP_CONSTANT16:
421 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
422 (uint16)OP[i]);
423 break;
424
425 case OP_CONSTANT4:
426 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
427 (uint16)SEXT4(OP[i]));
428 break;
429
430 case OP_CONSTANT3:
431 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
432 (uint16)SEXT3(OP[i]));
433 break;
434
435 case OP_MEMREF2:
436 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
437 (uint16)OP[i]);
438 (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
439 (uint16)GPR (OP[i + 1]));
440 i++;
441 break;
442 }
443 }
444 }
445
446 (*cr16_callback->flush_stdout) (cr16_callback);
447 }
448
449 static void
450 do_trace_output_flush (void)
451 {
452 (*cr16_callback->flush_stdout) (cr16_callback);
453 }
454
455 static void
456 do_trace_output_finish (void)
457 {
458 (*cr16_callback->printf_filtered) (cr16_callback,
459 " F0=%d F1=%d C=%d\n",
460 (State.trace.psw & PSR_F_BIT) != 0,
461 (State.trace.psw & PSR_F_BIT) != 0,
462 (State.trace.psw & PSR_C_BIT) != 0);
463 (*cr16_callback->flush_stdout) (cr16_callback);
464 }
465
466 #if 0
467 static void
468 trace_output_40 (uint64 val)
469 {
470 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
471 {
472 (*cr16_callback->printf_filtered) (cr16_callback,
473 " :: %*s0x%.2x%.8lx",
474 SIZE_VALUES - 12,
475 "",
476 ((int)(val >> 32) & 0xff),
477 ((unsigned long) val) & 0xffffffff);
478 do_trace_output_finish ();
479 }
480 }
481 #endif
482
483 static void
484 trace_output_32 (uint32 val)
485 {
486 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
487 {
488 (*cr16_callback->printf_filtered) (cr16_callback,
489 " :: %*s0x%.8x",
490 SIZE_VALUES - 10,
491 "",
492 (int) val);
493 do_trace_output_finish ();
494 }
495 }
496
497 static void
498 trace_output_16 (uint16 val)
499 {
500 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
501 {
502 (*cr16_callback->printf_filtered) (cr16_callback,
503 " :: %*s0x%.4x",
504 SIZE_VALUES - 6,
505 "",
506 (int) val);
507 do_trace_output_finish ();
508 }
509 }
510
511 static void
512 trace_output_void (void)
513 {
514 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
515 {
516 (*cr16_callback->printf_filtered) (cr16_callback, "\n");
517 do_trace_output_flush ();
518 }
519 }
520
521 static void
522 trace_output_flag (void)
523 {
524 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
525 {
526 (*cr16_callback->printf_filtered) (cr16_callback,
527 " :: %*s",
528 SIZE_VALUES,
529 "");
530 do_trace_output_finish ();
531 }
532 }
533
534
535
536
537 #else
538 #define trace_input(NAME, IN1, IN2, IN3)
539 #define trace_output(RESULT)
540 #endif
541
542 /* addub. */
543 void
544 OP_2C_8 (void)
545 {
546 uint8 tmp;
547 uint8 a = OP[0] & 0xff;
548 uint16 b = (GPR (OP[1])) & 0xff;
549 trace_input ("addub", OP_CONSTANT4_1, OP_REG, OP_VOID);
550 tmp = (a + b) & 0xff;
551 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
552 trace_output_16 (tmp);
553 }
554
555 /* addub. */
556 void
557 OP_2CB_C (void)
558 {
559 uint16 tmp;
560 uint8 a = ((OP[0]) & 0xff), b = (GPR (OP[1])) & 0xff;
561 trace_input ("addub", OP_CONSTANT16, OP_REG, OP_VOID);
562 tmp = (a + b) & 0xff;
563 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
564 trace_output_16 (tmp);
565 }
566
567 /* addub. */
568 void
569 OP_2D_8 (void)
570 {
571 uint8 a = (GPR (OP[0])) & 0xff;
572 uint8 b = (GPR (OP[1])) & 0xff;
573 uint16 tmp = (a + b) & 0xff;
574 trace_input ("addub", OP_REG, OP_REG, OP_VOID);
575 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
576 trace_output_16 (tmp);
577 }
578
579 /* adduw. */
580 void
581 OP_2E_8 (void)
582 {
583 uint16 a = OP[0];
584 uint16 b = GPR (OP[1]);
585 uint16 tmp = (a + b);
586 trace_input ("adduw", OP_CONSTANT4_1, OP_REG, OP_VOID);
587 SET_GPR (OP[1], tmp);
588 trace_output_16 (tmp);
589 }
590
591 /* adduw. */
592 void
593 OP_2EB_C (void)
594 {
595 uint16 a = OP[0];
596 uint16 b = GPR (OP[1]);
597 uint16 tmp = (a + b);
598 trace_input ("adduw", OP_CONSTANT16, OP_REG, OP_VOID);
599 SET_GPR (OP[1], tmp);
600 trace_output_16 (tmp);
601 }
602
603 /* adduw. */
604 void
605 OP_2F_8 (void)
606 {
607 uint16 a = GPR (OP[0]);
608 uint16 b = GPR (OP[1]);
609 uint16 tmp = (a + b);
610 trace_input ("adduw", OP_REG, OP_REG, OP_VOID);
611 SET_GPR (OP[1], tmp);
612 trace_output_16 (tmp);
613 }
614
615 /* addb. */
616 void
617 OP_30_8 (void)
618 {
619 uint8 a = OP[0];
620 uint8 b = (GPR (OP[1]) & 0xff);
621 uint16 tmp = (a + b) & 0xff;
622 trace_input ("addb", OP_CONSTANT4_1, OP_REG, OP_VOID);
623 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
624 SET_PSR_C (tmp > 0xFF);
625 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
626 trace_output_16 (tmp);
627 }
628
629 /* addb. */
630 void
631 OP_30B_C (void)
632 {
633 uint8 a = (OP[0]) & 0xff;
634 uint8 b = (GPR (OP[1]) & 0xff);
635 uint16 tmp = (a + b) & 0xff;
636 trace_input ("addb", OP_CONSTANT16, OP_REG, OP_VOID);
637 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
638 SET_PSR_C (tmp > 0xFF);
639 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
640 trace_output_16 (tmp);
641 }
642
643 /* addb. */
644 void
645 OP_31_8 (void)
646 {
647 uint8 a = (GPR (OP[0]) & 0xff);
648 uint8 b = (GPR (OP[1]) & 0xff);
649 uint16 tmp = (a + b) & 0xff;
650 trace_input ("addb", OP_REG, OP_REG, OP_VOID);
651 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
652 SET_PSR_C (tmp > 0xFF);
653 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
654 trace_output_16 (tmp);
655 }
656
657 /* addw. */
658 void
659 OP_32_8 (void)
660 {
661 int16 a = OP[0];
662 uint16 tmp, b = GPR (OP[1]);
663 tmp = (a + b);
664 trace_input ("addw", OP_CONSTANT4_1, OP_REG, OP_VOID);
665 SET_GPR (OP[1], tmp);
666 SET_PSR_C (tmp > 0xFFFF);
667 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
668 trace_output_16 (tmp);
669 }
670
671 /* addw. */
672 void
673 OP_32B_C (void)
674 {
675 int16 a = OP[0];
676 uint16 tmp, b = GPR (OP[1]);
677 tmp = (a + b);
678 trace_input ("addw", OP_CONSTANT16, OP_REG, OP_VOID);
679 SET_GPR (OP[1], tmp);
680 SET_PSR_C (tmp > 0xFFFF);
681 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
682 trace_output_16 (tmp);
683 }
684
685 /* addw. */
686 void
687 OP_33_8 (void)
688 {
689 uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
690 trace_input ("addw", OP_REG, OP_REG, OP_VOID);
691 tmp = (a + b);
692 SET_GPR (OP[1], tmp);
693 SET_PSR_C (tmp > 0xFFFF);
694 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
695 trace_output_16 (tmp);
696 }
697
698 /* addcb. */
699 void
700 OP_34_8 (void)
701 {
702 uint8 tmp, a = OP[0] & 0xff, b = (GPR (OP[1])) & 0xff;
703 trace_input ("addcb", OP_CONSTANT4_1, OP_REG, OP_REG);
704 tmp = (a + b + PSR_C) & 0xff;
705 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
706 SET_PSR_C (tmp > 0xFF);
707 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
708 trace_output_16 (tmp);
709 }
710
711 /* addcb. */
712 void
713 OP_34B_C (void)
714 {
715 int8 a = OP[0] & 0xff;
716 uint8 b = (GPR (OP[1])) & 0xff;
717 uint8 tmp = (a + b + PSR_C) & 0xff;
718 trace_input ("addcb", OP_CONSTANT16, OP_REG, OP_VOID);
719 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
720 SET_PSR_C (tmp > 0xFF);
721 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
722 trace_output_16 (tmp);
723 }
724
725 /* addcb. */
726 void
727 OP_35_8 (void)
728 {
729 uint8 a = (GPR (OP[0])) & 0xff;
730 uint8 b = (GPR (OP[1])) & 0xff;
731 uint8 tmp = (a + b + PSR_C) & 0xff;
732 trace_input ("addcb", OP_REG, OP_REG, OP_VOID);
733 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
734 SET_PSR_C (tmp > 0xFF);
735 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
736 trace_output_16 (tmp);
737 }
738
739 /* addcw. */
740 void
741 OP_36_8 (void)
742 {
743 uint16 a = OP[0];
744 uint16 b = GPR (OP[1]);
745 uint16 tmp = (a + b + PSR_C);
746 trace_input ("addcw", OP_CONSTANT4_1, OP_REG, OP_VOID);
747 SET_GPR (OP[1], tmp);
748 SET_PSR_C (tmp > 0xFFFF);
749 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
750 trace_output_16 (tmp);
751 }
752
753 /* addcw. */
754 void
755 OP_36B_C (void)
756 {
757 int16 a = OP[0];
758 uint16 b = GPR (OP[1]);
759 uint16 tmp = (a + b + PSR_C);
760 trace_input ("addcw", OP_CONSTANT16, OP_REG, OP_VOID);
761 SET_GPR (OP[1], tmp);
762 SET_PSR_C (tmp > 0xFFFF);
763 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
764 trace_output_16 (tmp);
765 }
766
767 /* addcw. */
768 void
769 OP_37_8 (void)
770 {
771 uint16 a = GPR (OP[1]);
772 uint16 b = GPR (OP[1]);
773 uint16 tmp = (a + b + PSR_C);
774 trace_input ("addcw", OP_REG, OP_REG, OP_VOID);
775 SET_GPR (OP[1], tmp);
776 SET_PSR_C (tmp > 0xFFFF);
777 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
778 trace_output_16 (tmp);
779 }
780
781 /* addd. */
782 void
783 OP_60_8 (void)
784 {
785 int16 a = (OP[0]);
786 uint32 b = GPR32 (OP[1]);
787 uint32 tmp = (a + b);
788 trace_input ("addd", OP_CONSTANT4_1, OP_REGP, OP_VOID);
789 SET_GPR32 (OP[1], tmp);
790 SET_PSR_C (tmp > 0xFFFFFFFF);
791 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
792 trace_output_32 (tmp);
793 }
794
795 /* addd. */
796 void
797 OP_60B_C (void)
798 {
799 int32 a = (SEXT16(OP[0]));
800 uint32 b = GPR32 (OP[1]);
801 uint32 tmp = (a + b);
802 trace_input ("addd", OP_CONSTANT16, OP_REGP, OP_VOID);
803 SET_GPR32 (OP[1], tmp);
804 SET_PSR_C (tmp > 0xFFFFFFFF);
805 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
806 trace_output_32 (tmp);
807 }
808
809 /* addd. */
810 void
811 OP_61_8 (void)
812 {
813 uint32 a = GPR32 (OP[0]);
814 uint32 b = GPR32 (OP[1]);
815 uint32 tmp = (a + b);
816 trace_input ("addd", OP_REGP, OP_REGP, OP_VOID);
817 SET_GPR32 (OP[1], tmp);
818 trace_output_32 (tmp);
819 SET_PSR_C (tmp > 0xFFFFFFFF);
820 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
821 }
822
823 /* addd. */
824 void
825 OP_4_8 (void)
826 {
827 uint32 a = OP[0];
828 uint32 b = GPR32 (OP[1]);
829 uint32 tmp;
830 trace_input ("addd", OP_CONSTANT20, OP_REGP, OP_VOID);
831 tmp = (a + b);
832 SET_GPR32 (OP[1], tmp);
833 SET_PSR_C (tmp > 0xFFFFFFFF);
834 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
835 trace_output_32 (tmp);
836 }
837
838 /* addd. */
839 void
840 OP_2_C (void)
841 {
842 int32 a = OP[0];
843 uint32 b = GPR32 (OP[1]);
844 uint32 tmp;
845 trace_input ("addd", OP_CONSTANT32, OP_REGP, OP_VOID);
846 tmp = (a + b);
847 SET_GPR32 (OP[1], tmp);
848 SET_PSR_C (tmp > 0xFFFFFFFF);
849 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
850 trace_output_32 (tmp);
851 }
852
853 /* andb. */
854 void
855 OP_20_8 (void)
856 {
857 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
858 trace_input ("andb", OP_CONSTANT4, OP_REG, OP_VOID);
859 tmp = a & b;
860 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
861 trace_output_16 (tmp);
862 }
863
864 /* andb. */
865 void
866 OP_20B_C (void)
867 {
868 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
869 trace_input ("andb", OP_CONSTANT16, OP_REG, OP_VOID);
870 tmp = a & b;
871 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
872 trace_output_16 (tmp);
873 }
874
875 /* andb. */
876 void
877 OP_21_8 (void)
878 {
879 uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
880 trace_input ("andb", OP_REG, OP_REG, OP_VOID);
881 tmp = a & b;
882 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
883 trace_output_16 (tmp);
884 }
885
886 /* andw. */
887 void
888 OP_22_8 (void)
889 {
890 uint16 tmp, a = OP[0], b = GPR (OP[1]);
891 trace_input ("andw", OP_CONSTANT4, OP_REG, OP_VOID);
892 tmp = a & b;
893 SET_GPR (OP[1], tmp);
894 trace_output_16 (tmp);
895 }
896
897 /* andw. */
898 void
899 OP_22B_C (void)
900 {
901 uint16 tmp, a = OP[0], b = GPR (OP[1]);
902 trace_input ("andw", OP_CONSTANT16, OP_REG, OP_VOID);
903 tmp = a & b;
904 SET_GPR (OP[1], tmp);
905 trace_output_16 (tmp);
906 }
907
908 /* andw. */
909 void
910 OP_23_8 (void)
911 {
912 uint16 tmp, a = GPR (OP[0]), b = GPR (OP[1]);
913 trace_input ("andw", OP_REG, OP_REG, OP_VOID);
914 tmp = a & b;
915 SET_GPR (OP[1], tmp);
916 trace_output_16 (tmp);
917 }
918
919 /* andd. */
920 void
921 OP_4_C (void)
922 {
923 uint32 tmp, a = OP[0], b = GPR32 (OP[1]);
924 trace_input ("andd", OP_CONSTANT32, OP_REGP, OP_VOID);
925 tmp = a & b;
926 SET_GPR32 (OP[1], tmp);
927 trace_output_32 (tmp);
928 }
929
930 /* andd. */
931 void
932 OP_14B_14 (void)
933 {
934 uint32 tmp, a = (GPR32 (OP[0])), b = (GPR32 (OP[1]));
935 trace_input ("andd", OP_REGP, OP_REGP, OP_VOID);
936 tmp = a & b;
937 SET_GPR32 (OP[1], tmp);
938 trace_output_32 (tmp);
939 }
940
941 /* ord. */
942 void
943 OP_5_C (void)
944 {
945 uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]);
946 trace_input ("ord", OP_CONSTANT32, OP_REG, OP_VOID);
947 tmp = a | b;
948 SET_GPR32 (OP[1], tmp);
949 trace_output_32 (tmp);
950 }
951
952 /* ord. */
953 void
954 OP_149_14 (void)
955 {
956 uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
957 trace_input ("ord", OP_REGP, OP_REGP, OP_VOID);
958 tmp = a | b;
959 SET_GPR32 (OP[1], tmp);
960 trace_output_32 (tmp);
961 }
962
963 /* xord. */
964 void
965 OP_6_C (void)
966 {
967 uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]);
968 trace_input ("xord", OP_CONSTANT32, OP_REG, OP_VOID);
969 tmp = a ^ b;
970 SET_GPR32 (OP[1], tmp);
971 trace_output_32 (tmp);
972 }
973
974 /* xord. */
975 void
976 OP_14A_14 (void)
977 {
978 uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
979 trace_input ("xord", OP_REGP, OP_REGP, OP_VOID);
980 tmp = a ^ b;
981 SET_GPR32 (OP[1], tmp);
982 trace_output_32 (tmp);
983 }
984
985
986 /* b. */
987 void
988 OP_1_4 (void)
989 {
990 uint32 tmp = 0, cc = cond_stat (OP[0]);
991 trace_input ("b", OP_CONSTANT4, OP_DISPE9, OP_VOID);
992 if (cc)
993 {
994 if (sign_flag)
995 tmp = (PC - (OP[1]));
996 else
997 tmp = (PC + (OP[1]));
998 /* If the resulting PC value is less than 0x00_0000 or greater
999 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1000
1001 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1002 {
1003 State.exception = SIG_CR16_BUS;
1004 State.pc_changed = 1; /* Don't increment the PC. */
1005 trace_output_void ();
1006 return;
1007 }
1008 else
1009 JMP (tmp);
1010 }
1011 sign_flag = 0; /* Reset sign_flag. */
1012 trace_output_32 (tmp);
1013 }
1014
1015 /* b. */
1016 void
1017 OP_18_8 (void)
1018 {
1019 uint32 tmp = 0, cc = cond_stat (OP[0]);
1020 trace_input ("b", OP_CONSTANT4, OP_DISP17, OP_VOID);
1021 if (cc)
1022 {
1023 if (sign_flag)
1024 tmp = (PC - OP[1]);
1025 else
1026 tmp = (PC + OP[1]);
1027 /* If the resulting PC value is less than 0x00_0000 or greater
1028 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1029
1030 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1031 {
1032 State.exception = SIG_CR16_BUS;
1033 State.pc_changed = 1; /* Don't increment the PC. */
1034 trace_output_void ();
1035 return;
1036 }
1037 else
1038 JMP (tmp);
1039 }
1040 sign_flag = 0; /* Reset sign_flag. */
1041 trace_output_32 (tmp);
1042 }
1043
1044 /* b. */
1045 void
1046 OP_10_10 (void)
1047 {
1048 uint32 tmp = 0, cc = cond_stat (OP[0]);
1049 trace_input ("b", OP_CONSTANT4, OP_DISP25, OP_VOID);
1050 if (cc)
1051 {
1052 if (sign_flag)
1053 tmp = (PC - (OP[1]));
1054 else
1055 tmp = (PC + (OP[1]));
1056 /* If the resulting PC value is less than 0x00_0000 or greater
1057 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1058
1059 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1060 {
1061 State.exception = SIG_CR16_BUS;
1062 State.pc_changed = 1; /* Don't increment the PC. */
1063 trace_output_void ();
1064 return;
1065 }
1066 else
1067 JMP (tmp);
1068 }
1069 sign_flag = 0; /* Reset sign_flag. */
1070 trace_output_32 (tmp);
1071 }
1072
1073 /* bal. */
1074 void
1075 OP_C0_8 (void)
1076 {
1077 uint32 tmp;
1078 trace_input ("bal", OP_REG, OP_DISP17, OP_VOID);
1079 tmp = ((PC + 4) >> 1); /* Store PC in RA register. */
1080 SET_GPR32 (14, tmp);
1081 if (sign_flag)
1082 tmp = (PC - (OP[1]));
1083 else
1084 tmp = (PC + (OP[1]));
1085
1086 /* If the resulting PC value is less than 0x00_0000 or greater
1087 than 0xFF_FFFF, this instruction causes an IAD trap. */
1088
1089 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1090 {
1091 State.exception = SIG_CR16_BUS;
1092 State.pc_changed = 1; /* Don't increment the PC. */
1093 trace_output_void ();
1094 return;
1095 }
1096 else
1097 JMP (tmp);
1098 sign_flag = 0; /* Reset sign_flag. */
1099 trace_output_32 (tmp);
1100 }
1101
1102
1103 /* bal. */
1104 void
1105 OP_102_14 (void)
1106 {
1107 uint32 tmp;
1108 trace_input ("bal", OP_REGP, OP_DISP25, OP_VOID);
1109 tmp = (((PC) + 4) >> 1); /* Store PC in reg pair. */
1110 SET_GPR32 (OP[0], tmp);
1111 if (sign_flag)
1112 tmp = ((PC) - (OP[1]));
1113 else
1114 tmp = ((PC) + (OP[1]));
1115 /* If the resulting PC value is less than 0x00_0000 or greater
1116 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1117
1118 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1119 {
1120 State.exception = SIG_CR16_BUS;
1121 State.pc_changed = 1; /* Don't increment the PC. */
1122 trace_output_void ();
1123 return;
1124 }
1125 else
1126 JMP (tmp);
1127 sign_flag = 0; /* Reset sign_flag. */
1128 trace_output_32 (tmp);
1129 }
1130
1131 /* jal. */
1132 void
1133 OP_148_14 (void)
1134 {
1135 uint32 tmp;
1136 trace_input ("jal", OP_REGP, OP_REGP, OP_VOID);
1137 SET_GPR32 (OP[0], (((PC) + 4) >> 1)); /* Store next PC in RA */
1138 tmp = GPR32 (OP[1]);
1139 tmp = SEXT24(tmp << 1);
1140 /* If the resulting PC value is less than 0x00_0000 or greater
1141 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1142
1143 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
1144 {
1145 State.exception = SIG_CR16_BUS;
1146 State.pc_changed = 1; /* Don't increment the PC. */
1147 trace_output_void ();
1148 return;
1149 }
1150 else
1151 JMP (tmp);
1152
1153 trace_output_32 (tmp);
1154 }
1155
1156
1157 /* jal. */
1158 void
1159 OP_D_C (void)
1160 {
1161 uint32 tmp;
1162 trace_input ("jal", OP_REGP, OP_VOID, OP_VOID);
1163 SET_GPR32 (14, (((PC) + 2) >> 1)); /* Store next PC in RA */
1164 tmp = GPR32 (OP[0]);
1165 tmp = SEXT24(tmp << 1);
1166 /* If the resulting PC value is less than 0x00_0000 or greater
1167 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1168
1169 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
1170 {
1171 State.exception = SIG_CR16_BUS;
1172 State.pc_changed = 1; /* Don't increment the PC. */
1173 trace_output_void ();
1174 return;
1175 }
1176 else
1177 JMP (tmp);
1178
1179 trace_output_32 (tmp);
1180 }
1181
1182
1183 /* beq0b. */
1184 void
1185 OP_C_8 (void)
1186 {
1187 uint32 addr;
1188 uint8 a = (GPR (OP[0]) & 0xFF);
1189 trace_input ("beq0b", OP_REG, OP_DISP5, OP_VOID);
1190 addr = OP[1];
1191 if (a == 0)
1192 {
1193 if (sign_flag)
1194 addr = (PC - OP[1]);
1195 else
1196 addr = (PC + OP[1]);
1197
1198 JMP (addr);
1199 }
1200 sign_flag = 0; /* Reset sign_flag. */
1201 trace_output_void ();
1202 }
1203
1204 /* bne0b. */
1205 void
1206 OP_D_8 (void)
1207 {
1208 uint32 addr;
1209 uint8 a = (GPR (OP[0]) & 0xFF);
1210 trace_input ("bne0b", OP_REG, OP_DISP5, OP_VOID);
1211 addr = OP[1];
1212 if (a != 0)
1213 {
1214 if (sign_flag)
1215 addr = (PC - OP[1]);
1216 else
1217 addr = (PC + OP[1]);
1218
1219 JMP (addr);
1220 }
1221 sign_flag = 0; /* Reset sign_flag. */
1222 trace_output_void ();
1223 }
1224
1225 /* beq0w. */
1226 void
1227 OP_E_8 (void)
1228 {
1229 uint32 addr;
1230 uint16 a = GPR (OP[0]);
1231 trace_input ("beq0w", OP_REG, OP_DISP5, OP_VOID);
1232 addr = OP[1];
1233 if (a == 0)
1234 {
1235 if (sign_flag)
1236 addr = (PC - OP[1]);
1237 else
1238 addr = (PC + OP[1]);
1239
1240 JMP (addr);
1241 }
1242 sign_flag = 0; /* Reset sign_flag. */
1243 trace_output_void ();
1244 }
1245
1246 /* bne0w. */
1247 void
1248 OP_F_8 (void)
1249 {
1250 uint32 addr;
1251 uint16 a = GPR (OP[0]);
1252 trace_input ("bne0w", OP_REG, OP_DISP5, OP_VOID);
1253 addr = OP[1];
1254 if (a != 0)
1255 {
1256 if (sign_flag)
1257 addr = (PC - OP[1]);
1258 else
1259 addr = (PC + OP[1]);
1260
1261 JMP (addr);
1262 }
1263 sign_flag = 0; /* Reset sign_flag. */
1264 trace_output_void ();
1265 }
1266
1267
1268 /* jeq. */
1269 void
1270 OP_A0_C (void)
1271 {
1272 uint32 tmp = 0;
1273 trace_input ("jeq", OP_REGP, OP_VOID, OP_VOID);
1274 if ((PSR_Z) == 1)
1275 {
1276 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */
1277 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */
1278 }
1279 trace_output_32 (tmp);
1280 }
1281
1282 /* jne. */
1283 void
1284 OP_A1_C (void)
1285 {
1286 uint32 tmp = 0;
1287 trace_input ("jne", OP_REGP, OP_VOID, OP_VOID);
1288 if ((PSR_Z) == 0)
1289 {
1290 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */
1291 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */
1292 }
1293 trace_output_32 (tmp);
1294 }
1295
1296 /* jcs. */
1297 void
1298 OP_A2_C (void)
1299 {
1300 uint32 tmp = 0;
1301 trace_input ("jcs", OP_REGP, OP_VOID, OP_VOID);
1302 if ((PSR_C) == 1)
1303 {
1304 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1305 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1306 }
1307 trace_output_32 (tmp);
1308 }
1309
1310 /* jcc. */
1311 void
1312 OP_A3_C (void)
1313 {
1314 uint32 tmp = 0;
1315 trace_input ("jcc", OP_REGP, OP_VOID, OP_VOID);
1316 if ((PSR_C) == 0)
1317 {
1318 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1319 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1320 }
1321 trace_output_32 (tmp);
1322 }
1323
1324 /* jhi. */
1325 void
1326 OP_A4_C (void)
1327 {
1328 uint32 tmp = 0;
1329 trace_input ("jhi", OP_REGP, OP_VOID, OP_VOID);
1330 if ((PSR_L) == 1)
1331 {
1332 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1333 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1334 }
1335 trace_output_32 (tmp);
1336 }
1337
1338 /* jls. */
1339 void
1340 OP_A5_C (void)
1341 {
1342 uint32 tmp = 0;
1343 trace_input ("jls", OP_REGP, OP_VOID, OP_VOID);
1344 if ((PSR_L) == 0)
1345 {
1346 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1347 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1348 }
1349 trace_output_32 (tmp);
1350 }
1351
1352 /* jgt. */
1353 void
1354 OP_A6_C (void)
1355 {
1356 uint32 tmp = 0;
1357 trace_input ("jgt", OP_REGP, OP_VOID, OP_VOID);
1358 if ((PSR_N) == 1)
1359 {
1360 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1361 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1362 }
1363 trace_output_32 (tmp);
1364 }
1365
1366 /* jle. */
1367 void
1368 OP_A7_C (void)
1369 {
1370 uint32 tmp = 0;
1371 trace_input ("jle", OP_REGP, OP_VOID, OP_VOID);
1372 if ((PSR_N) == 0)
1373 {
1374 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1375 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1376 }
1377 trace_output_32 (tmp);
1378 }
1379
1380
1381 /* jfs. */
1382 void
1383 OP_A8_C (void)
1384 {
1385 uint32 tmp = 0;
1386 trace_input ("jfs", OP_REGP, OP_VOID, OP_VOID);
1387 if ((PSR_F) == 1)
1388 {
1389 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1390 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1391 }
1392 trace_output_32 (tmp);
1393 }
1394
1395 /* jfc. */
1396 void
1397 OP_A9_C (void)
1398 {
1399 uint32 tmp = 0;
1400 trace_input ("jfc", OP_REGP, OP_VOID, OP_VOID);
1401 if ((PSR_F) == 0)
1402 {
1403 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1404 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1405 }
1406 trace_output_32 (tmp);
1407 }
1408
1409 /* jlo. */
1410 void
1411 OP_AA_C (void)
1412 {
1413 uint32 tmp = 0;
1414 trace_input ("jlo", OP_REGP, OP_VOID, OP_VOID);
1415 if (((PSR_Z) == 0) & ((PSR_L) == 0))
1416 {
1417 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1418 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1419 }
1420 trace_output_32 (tmp);
1421 }
1422
1423 /* jhs. */
1424 void
1425 OP_AB_C (void)
1426 {
1427 uint32 tmp = 0;
1428 trace_input ("jhs", OP_REGP, OP_VOID, OP_VOID);
1429 if (((PSR_Z) == 1) | ((PSR_L) == 1))
1430 {
1431 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1432 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1433 }
1434 trace_output_32 (tmp);
1435 }
1436
1437 /* jlt. */
1438 void
1439 OP_AC_C (void)
1440 {
1441 uint32 tmp = 0;
1442 trace_input ("jlt", OP_REGP, OP_VOID, OP_VOID);
1443 if (((PSR_Z) == 0) & ((PSR_N) == 0))
1444 {
1445 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1446 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1447 }
1448 trace_output_32 (tmp);
1449 }
1450
1451 /* jge. */
1452 void
1453 OP_AD_C (void)
1454 {
1455 uint32 tmp = 0;
1456 trace_input ("jge", OP_REGP, OP_VOID, OP_VOID);
1457 if (((PSR_Z) == 1) | ((PSR_N) == 1))
1458 {
1459 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1460 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1461 }
1462 trace_output_32 (tmp);
1463 }
1464
1465 /* jump. */
1466 void
1467 OP_AE_C (void)
1468 {
1469 uint32 tmp;
1470 trace_input ("jump", OP_REGP, OP_VOID, OP_VOID);
1471 tmp = GPR32 (OP[0]) /*& 0x3fffff*/; /* Use only 0 - 22 bits */
1472 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1473 trace_output_32 (tmp);
1474 }
1475
1476 /* jusr. */
1477 void
1478 OP_AF_C (void)
1479 {
1480 uint32 tmp;
1481 trace_input ("jusr", OP_REGP, OP_VOID, OP_VOID);
1482 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1483 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1484 SET_PSR_U(1);
1485 trace_output_32 (tmp);
1486 }
1487
1488 /* seq. */
1489 void
1490 OP_80_C (void)
1491 {
1492 trace_input ("seq", OP_REG, OP_VOID, OP_VOID);
1493 if ((PSR_Z) == 1)
1494 SET_GPR (OP[0], 1);
1495 else
1496 SET_GPR (OP[0], 0);
1497 trace_output_void ();
1498 }
1499 /* sne. */
1500 void
1501 OP_81_C (void)
1502 {
1503 trace_input ("sne", OP_REG, OP_VOID, OP_VOID);
1504 if ((PSR_Z) == 0)
1505 SET_GPR (OP[0], 1);
1506 else
1507 SET_GPR (OP[0], 0);
1508 trace_output_void ();
1509 }
1510
1511 /* scs. */
1512 void
1513 OP_82_C (void)
1514 {
1515 trace_input ("scs", OP_REG, OP_VOID, OP_VOID);
1516 if ((PSR_C) == 1)
1517 SET_GPR (OP[0], 1);
1518 else
1519 SET_GPR (OP[0], 0);
1520 trace_output_void ();
1521 }
1522
1523 /* scc. */
1524 void
1525 OP_83_C (void)
1526 {
1527 trace_input ("scc", OP_REG, OP_VOID, OP_VOID);
1528 if ((PSR_C) == 0)
1529 SET_GPR (OP[0], 1);
1530 else
1531 SET_GPR (OP[0], 0);
1532 trace_output_void ();
1533 }
1534
1535 /* shi. */
1536 void
1537 OP_84_C (void)
1538 {
1539 trace_input ("shi", OP_REG, OP_VOID, OP_VOID);
1540 if ((PSR_L) == 1)
1541 SET_GPR (OP[0], 1);
1542 else
1543 SET_GPR (OP[0], 0);
1544 trace_output_void ();
1545 }
1546
1547 /* sls. */
1548 void
1549 OP_85_C (void)
1550 {
1551 trace_input ("sls", OP_REG, OP_VOID, OP_VOID);
1552 if ((PSR_L) == 0)
1553 SET_GPR (OP[0], 1);
1554 else
1555 SET_GPR (OP[0], 0);
1556 trace_output_void ();
1557 }
1558
1559 /* sgt. */
1560 void
1561 OP_86_C (void)
1562 {
1563 trace_input ("sgt", OP_REG, OP_VOID, OP_VOID);
1564 if ((PSR_N) == 1)
1565 SET_GPR (OP[0], 1);
1566 else
1567 SET_GPR (OP[0], 0);
1568 trace_output_void ();
1569 }
1570
1571 /* sle. */
1572 void
1573 OP_87_C (void)
1574 {
1575 trace_input ("sle", OP_REG, OP_VOID, OP_VOID);
1576 if ((PSR_N) == 0)
1577 SET_GPR (OP[0], 1);
1578 else
1579 SET_GPR (OP[0], 0);
1580 trace_output_void ();
1581 }
1582
1583 /* sfs. */
1584 void
1585 OP_88_C (void)
1586 {
1587 trace_input ("sfs", OP_REG, OP_VOID, OP_VOID);
1588 if ((PSR_F) == 1)
1589 SET_GPR (OP[0], 1);
1590 else
1591 SET_GPR (OP[0], 0);
1592 trace_output_void ();
1593 }
1594
1595 /* sfc. */
1596 void
1597 OP_89_C (void)
1598 {
1599 trace_input ("sfc", OP_REG, OP_VOID, OP_VOID);
1600 if ((PSR_F) == 0)
1601 SET_GPR (OP[0], 1);
1602 else
1603 SET_GPR (OP[0], 0);
1604 trace_output_void ();
1605 }
1606
1607
1608 /* slo. */
1609 void
1610 OP_8A_C (void)
1611 {
1612 trace_input ("slo", OP_REG, OP_VOID, OP_VOID);
1613 if (((PSR_Z) == 0) & ((PSR_L) == 0))
1614 SET_GPR (OP[0], 1);
1615 else
1616 SET_GPR (OP[0], 0);
1617 trace_output_void ();
1618 }
1619
1620 /* shs. */
1621 void
1622 OP_8B_C (void)
1623 {
1624 trace_input ("shs", OP_REG, OP_VOID, OP_VOID);
1625 if ( ((PSR_Z) == 1) | ((PSR_L) == 1))
1626 SET_GPR (OP[0], 1);
1627 else
1628 SET_GPR (OP[0], 0);
1629 trace_output_void ();
1630 }
1631
1632 /* slt. */
1633 void
1634 OP_8C_C (void)
1635 {
1636 trace_input ("slt", OP_REG, OP_VOID, OP_VOID);
1637 if (((PSR_Z) == 0) & ((PSR_N) == 0))
1638 SET_GPR (OP[0], 1);
1639 else
1640 SET_GPR (OP[0], 0);
1641 trace_output_void ();
1642 }
1643
1644 /* sge. */
1645 void
1646 OP_8D_C (void)
1647 {
1648 trace_input ("sge", OP_REG, OP_VOID, OP_VOID);
1649 if (((PSR_Z) == 1) | ((PSR_N) == 1))
1650 SET_GPR (OP[0], 1);
1651 else
1652 SET_GPR (OP[0], 0);
1653 trace_output_void ();
1654 }
1655
1656 /* cbitb. */
1657 void
1658 OP_D7_9 (void)
1659 {
1660 uint8 a = OP[0] & 0xff;
1661 uint32 addr = OP[1], tmp;
1662 trace_input ("cbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1663 tmp = RB (addr);
1664 SET_PSR_F (tmp & (1 << a));
1665 tmp = tmp & ~(1 << a);
1666 SB (addr, tmp);
1667 trace_output_32 (tmp);
1668 }
1669
1670 /* cbitb. */
1671 void
1672 OP_107_14 (void)
1673 {
1674 uint8 a = OP[0] & 0xff;
1675 uint32 addr = OP[1], tmp;
1676 trace_input ("cbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1677 tmp = RB (addr);
1678 SET_PSR_F (tmp & (1 << a));
1679 tmp = tmp & ~(1 << a);
1680 SB (addr, tmp);
1681 trace_output_32 (tmp);
1682 }
1683
1684 /* cbitb. */
1685 void
1686 OP_68_8 (void)
1687 {
1688 uint8 a = (OP[0]) & 0xff;
1689 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1690 trace_input ("cbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
1691 tmp = RB (addr);
1692 SET_PSR_F (tmp & (1 << a));
1693 tmp = tmp & ~(1 << a);
1694 SB (addr, tmp);
1695 trace_output_32 (addr);
1696 }
1697
1698 /* cbitb. */
1699 void
1700 OP_1AA_A (void)
1701 {
1702 uint8 a = (OP[0]) & 0xff;
1703 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1704 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1705 tmp = RB (addr);
1706 SET_PSR_F (tmp & (1 << a));
1707 tmp = tmp & ~(1 << a);
1708 SB (addr, tmp);
1709 trace_output_32 (addr);
1710 }
1711
1712 /* cbitb. */
1713 void
1714 OP_104_14 (void)
1715 {
1716 uint8 a = (OP[0]) & 0xff;
1717 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1718 trace_input ("cbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1719 tmp = RB (addr);
1720 SET_PSR_F (tmp & (1 << a));
1721 tmp = tmp & ~(1 << a);
1722 SB (addr, tmp);
1723 trace_output_32 (addr);
1724 }
1725
1726 /* cbitb. */
1727 void
1728 OP_D4_9 (void)
1729 {
1730 uint8 a = (OP[0]) & 0xff;
1731 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1732 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1733 tmp = RB (addr);
1734 SET_PSR_F (tmp & (1 << a));
1735 tmp = tmp & ~(1 << a);
1736 SB (addr, tmp);
1737 trace_output_32 (addr);
1738 }
1739
1740 /* cbitb. */
1741 void
1742 OP_D6_9 (void)
1743 {
1744 uint8 a = (OP[0]) & 0xff;
1745 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1746 trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
1747 tmp = RB (addr);
1748 SET_PSR_F (tmp & (1 << a));
1749 tmp = tmp & ~(1 << a);
1750 SB (addr, tmp);
1751 trace_output_32 (addr);
1752
1753 }
1754
1755 /* cbitb. */
1756 void
1757 OP_105_14 (void)
1758 {
1759 uint8 a = (OP[0]) & 0xff;
1760 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1761 trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
1762 tmp = RB (addr);
1763 SET_PSR_F (tmp & (1 << a));
1764 tmp = tmp & ~(1 << a);
1765 SB (addr, tmp);
1766 trace_output_32 (addr);
1767 }
1768
1769 /* cbitb. */
1770 void
1771 OP_106_14 (void)
1772 {
1773 uint8 a = (OP[0]) & 0xff;
1774 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1775 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
1776 tmp = RB (addr);
1777 SET_PSR_F (tmp & (1 << a));
1778 tmp = tmp & ~(1 << a);
1779 SB (addr, tmp);
1780 trace_output_32 (addr);
1781 }
1782
1783
1784 /* cbitw. */
1785 void
1786 OP_6F_8 (void)
1787 {
1788 uint16 a = OP[0];
1789 uint32 addr = OP[1], tmp;
1790 trace_input ("cbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1791 tmp = RW (addr);
1792 SET_PSR_F (tmp & (1 << a));
1793 tmp = tmp & ~(1 << a);
1794 SW (addr, tmp);
1795 trace_output_32 (tmp);
1796 }
1797
1798 /* cbitw. */
1799 void
1800 OP_117_14 (void)
1801 {
1802 uint16 a = OP[0];
1803 uint32 addr = OP[1], tmp;
1804 trace_input ("cbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1805 tmp = RW (addr);
1806 SET_PSR_F (tmp & (1 << a));
1807 tmp = tmp & ~(1 << a);
1808 SW (addr, tmp);
1809 trace_output_32 (tmp);
1810 }
1811
1812 /* cbitw. */
1813 void
1814 OP_36_7 (void)
1815 {
1816 uint32 addr;
1817 uint16 a = (OP[0]), tmp;
1818 trace_input ("cbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
1819
1820 if (OP[1] == 0)
1821 addr = (GPR32 (12)) + OP[2];
1822 else
1823 addr = (GPR32 (13)) + OP[2];
1824
1825 tmp = RW (addr);
1826 SET_PSR_F (tmp & (1 << a));
1827 tmp = tmp & ~(1 << a);
1828 SW (addr, tmp);
1829 trace_output_32 (addr);
1830
1831 }
1832
1833 /* cbitw. */
1834 void
1835 OP_1AB_A (void)
1836 {
1837 uint16 a = (OP[0]);
1838 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1839 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1840 tmp = RW (addr);
1841 SET_PSR_F (tmp & (1 << a));
1842 tmp = tmp & ~(1 << a);
1843 SW (addr, tmp);
1844 trace_output_32 (addr);
1845 }
1846
1847 /* cbitw. */
1848 void
1849 OP_114_14 (void)
1850 {
1851 uint16 a = (OP[0]);
1852 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1853 trace_input ("cbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1854 tmp = RW (addr);
1855 SET_PSR_F (tmp & (1 << a));
1856 tmp = tmp & ~(1 << a);
1857 SW (addr, tmp);
1858 trace_output_32 (addr);
1859 }
1860
1861
1862 /* cbitw. */
1863 void
1864 OP_6E_8 (void)
1865 {
1866 uint16 a = (OP[0]);
1867 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1868 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1869 tmp = RW (addr);
1870 SET_PSR_F (tmp & (1 << a));
1871 tmp = tmp & ~(1 << a);
1872 SW (addr, tmp);
1873 trace_output_32 (addr);
1874 }
1875
1876 /* cbitw. */
1877 void
1878 OP_69_8 (void)
1879 {
1880 uint16 a = (OP[0]);
1881 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1882 trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
1883 tmp = RW (addr);
1884 SET_PSR_F (tmp & (1 << a));
1885 tmp = tmp & ~(1 << a);
1886 SW (addr, tmp);
1887 trace_output_32 (addr);
1888 }
1889
1890
1891 /* cbitw. */
1892 void
1893 OP_115_14 (void)
1894 {
1895 uint16 a = (OP[0]);
1896 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1897 trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
1898 tmp = RW (addr);
1899 SET_PSR_F (tmp & (1 << a));
1900 tmp = tmp & ~(1 << a);
1901 SW (addr, tmp);
1902 trace_output_32 (addr);
1903 }
1904
1905 /* cbitw. */
1906 void
1907 OP_116_14 (void)
1908 {
1909 uint16 a = (OP[0]);
1910 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1911 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
1912 tmp = RW (addr);
1913 SET_PSR_F (tmp & (1 << a));
1914 tmp = tmp & ~(1 << a);
1915 SW (addr, tmp);
1916 trace_output_32 (addr);
1917 }
1918
1919 /* sbitb. */
1920 void
1921 OP_E7_9 (void)
1922 {
1923 uint8 a = OP[0] & 0xff;
1924 uint32 addr = OP[1], tmp;
1925 trace_input ("sbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1926 tmp = RB (addr);
1927 SET_PSR_F (tmp & (1 << a));
1928 tmp = tmp | (1 << a);
1929 SB (addr, tmp);
1930 trace_output_32 (tmp);
1931 }
1932
1933 /* sbitb. */
1934 void
1935 OP_10B_14 (void)
1936 {
1937 uint8 a = OP[0] & 0xff;
1938 uint32 addr = OP[1], tmp;
1939 trace_input ("sbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1940 tmp = RB (addr);
1941 SET_PSR_F (tmp & (1 << a));
1942 tmp = tmp | (1 << a);
1943 SB (addr, tmp);
1944 trace_output_32 (tmp);
1945 }
1946
1947 /* sbitb. */
1948 void
1949 OP_70_8 (void)
1950 {
1951 uint8 a = OP[0] & 0xff;
1952 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1953 trace_input ("sbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
1954 tmp = RB (addr);
1955 SET_PSR_F (tmp & (1 << a));
1956 tmp = tmp | (1 << a);
1957 SB (addr, tmp);
1958 trace_output_32 (tmp);
1959 }
1960
1961 /* sbitb. */
1962 void
1963 OP_1CA_A (void)
1964 {
1965 uint8 a = OP[0] & 0xff;
1966 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1967 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1968 tmp = RB (addr);
1969 SET_PSR_F (tmp & (1 << a));
1970 tmp = tmp | (1 << a);
1971 SB (addr, tmp);
1972 trace_output_32 (tmp);
1973 }
1974
1975 /* sbitb. */
1976 void
1977 OP_108_14 (void)
1978 {
1979 uint8 a = OP[0] & 0xff;
1980 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1981 trace_input ("sbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1982 tmp = RB (addr);
1983 SET_PSR_F (tmp & (1 << a));
1984 tmp = tmp | (1 << a);
1985 SB (addr, tmp);
1986 trace_output_32 (tmp);
1987 }
1988
1989
1990 /* sbitb. */
1991 void
1992 OP_E4_9 (void)
1993 {
1994 uint8 a = OP[0] & 0xff;
1995 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1996 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1997 tmp = RB (addr);
1998 SET_PSR_F (tmp & (1 << a));
1999 tmp = tmp | (1 << a);
2000 SB (addr, tmp);
2001 trace_output_32 (tmp);
2002 }
2003
2004 /* sbitb. */
2005 void
2006 OP_E6_9 (void)
2007 {
2008 uint8 a = OP[0] & 0xff;
2009 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2010 trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2011 tmp = RB (addr);
2012 SET_PSR_F (tmp & (1 << a));
2013 tmp = tmp | (1 << a);
2014 SB (addr, tmp);
2015 trace_output_32 (tmp);
2016 }
2017
2018
2019 /* sbitb. */
2020 void
2021 OP_109_14 (void)
2022 {
2023 uint8 a = OP[0] & 0xff;
2024 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2025 trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2026 tmp = RB (addr);
2027 SET_PSR_F (tmp & (1 << a));
2028 tmp = tmp | (1 << a);
2029 SB (addr, tmp);
2030 trace_output_32 (tmp);
2031 }
2032
2033
2034 /* sbitb. */
2035 void
2036 OP_10A_14 (void)
2037 {
2038 uint8 a = OP[0] & 0xff;
2039 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2040 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2041 tmp = RB (addr);
2042 SET_PSR_F (tmp & (1 << a));
2043 tmp = tmp | (1 << a);
2044 SB (addr, tmp);
2045 trace_output_32 (tmp);
2046 }
2047
2048
2049 /* sbitw. */
2050 void
2051 OP_77_8 (void)
2052 {
2053 uint16 a = OP[0];
2054 uint32 addr = OP[1], tmp;
2055 trace_input ("sbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2056 tmp = RW (addr);
2057 SET_PSR_F (tmp & (1 << a));
2058 tmp = tmp | (1 << a);
2059 SW (addr, tmp);
2060 trace_output_32 (tmp);
2061 }
2062
2063 /* sbitw. */
2064 void
2065 OP_11B_14 (void)
2066 {
2067 uint16 a = OP[0];
2068 uint32 addr = OP[1], tmp;
2069 trace_input ("sbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2070 tmp = RW (addr);
2071 SET_PSR_F (tmp & (1 << a));
2072 tmp = tmp | (1 << a);
2073 SW (addr, tmp);
2074 trace_output_32 (tmp);
2075 }
2076
2077 /* sbitw. */
2078 void
2079 OP_3A_7 (void)
2080 {
2081 uint32 addr;
2082 uint16 a = (OP[0]), tmp;
2083 trace_input ("sbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
2084
2085 if (OP[1] == 0)
2086 addr = (GPR32 (12)) + OP[2];
2087 else
2088 addr = (GPR32 (13)) + OP[2];
2089
2090 tmp = RW (addr);
2091 SET_PSR_F (tmp & (1 << a));
2092 tmp = tmp | (1 << a);
2093 SW (addr, tmp);
2094 trace_output_32 (addr);
2095 }
2096
2097 /* sbitw. */
2098 void
2099 OP_1CB_A (void)
2100 {
2101 uint16 a = (OP[0]);
2102 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2103 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2104 tmp = RW (addr);
2105 SET_PSR_F (tmp & (1 << a));
2106 tmp = tmp | (1 << a);
2107 SW (addr, tmp);
2108 trace_output_32 (addr);
2109 }
2110
2111 /* sbitw. */
2112 void
2113 OP_118_14 (void)
2114 {
2115 uint16 a = (OP[0]);
2116 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2117 trace_input ("sbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2118 tmp = RW (addr);
2119 SET_PSR_F (tmp & (1 << a));
2120 tmp = tmp | (1 << a);
2121 SW (addr, tmp);
2122 trace_output_32 (addr);
2123 }
2124
2125 /* sbitw. */
2126 void
2127 OP_76_8 (void)
2128 {
2129 uint16 a = (OP[0]);
2130 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2131 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2132 tmp = RW (addr);
2133 SET_PSR_F (tmp & (1 << a));
2134 tmp = tmp | (1 << a);
2135 SW (addr, tmp);
2136 trace_output_32 (addr);
2137 }
2138
2139 /* sbitw. */
2140 void
2141 OP_71_8 (void)
2142 {
2143 uint16 a = (OP[0]);
2144 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2145 trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2146 tmp = RW (addr);
2147 SET_PSR_F (tmp & (1 << a));
2148 tmp = tmp | (1 << a);
2149 SW (addr, tmp);
2150 trace_output_32 (addr);
2151 }
2152
2153 /* sbitw. */
2154 void
2155 OP_119_14 (void)
2156 {
2157 uint16 a = (OP[0]);
2158 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2159 trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2160 tmp = RW (addr);
2161 SET_PSR_F (tmp & (1 << a));
2162 tmp = tmp | (1 << a);
2163 SW (addr, tmp);
2164 trace_output_32 (addr);
2165 }
2166
2167 /* sbitw. */
2168 void
2169 OP_11A_14 (void)
2170 {
2171 uint16 a = (OP[0]);
2172 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2173 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2174 tmp = RW (addr);
2175 SET_PSR_F (tmp & (1 << a));
2176 tmp = tmp | (1 << a);
2177 SW (addr, tmp);
2178 trace_output_32 (addr);
2179 }
2180
2181
2182 /* tbitb. */
2183 void
2184 OP_F7_9 (void)
2185 {
2186 uint8 a = OP[0] & 0xff;
2187 uint32 addr = OP[1], tmp;
2188 trace_input ("tbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2189 tmp = RB (addr);
2190 SET_PSR_F (tmp & (1 << a));
2191 trace_output_32 (tmp);
2192 }
2193
2194 /* tbitb. */
2195 void
2196 OP_10F_14 (void)
2197 {
2198 uint8 a = OP[0] & 0xff;
2199 uint32 addr = OP[1], tmp;
2200 trace_input ("tbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2201 tmp = RB (addr);
2202 SET_PSR_F (tmp & (1 << a));
2203 trace_output_32 (tmp);
2204 }
2205
2206 /* tbitb. */
2207 void
2208 OP_78_8 (void)
2209 {
2210 uint8 a = (OP[0]) & 0xff;
2211 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2212 trace_input ("tbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
2213 tmp = RB (addr);
2214 SET_PSR_F (tmp & (1 << a));
2215 trace_output_32 (addr);
2216 }
2217
2218 /* tbitb. */
2219 void
2220 OP_1EA_A (void)
2221 {
2222 uint8 a = (OP[0]) & 0xff;
2223 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2224 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2225 tmp = RB (addr);
2226 SET_PSR_F (tmp & (1 << a));
2227 trace_output_32 (addr);
2228 }
2229
2230 /* tbitb. */
2231 void
2232 OP_10C_14 (void)
2233 {
2234 uint8 a = (OP[0]) & 0xff;
2235 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2236 trace_input ("tbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2237 tmp = RB (addr);
2238 SET_PSR_F (tmp & (1 << a));
2239 trace_output_32 (addr);
2240 }
2241
2242 /* tbitb. */
2243 void
2244 OP_F4_9 (void)
2245 {
2246 uint8 a = (OP[0]) & 0xff;
2247 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2248 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2249 tmp = RB (addr);
2250 SET_PSR_F (tmp & (1 << a));
2251 trace_output_32 (addr);
2252 }
2253
2254 /* tbitb. */
2255 void
2256 OP_F6_9 (void)
2257 {
2258 uint8 a = (OP[0]) & 0xff;
2259 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2260 trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2261 tmp = RB (addr);
2262 SET_PSR_F (tmp & (1 << a));
2263 trace_output_32 (addr);
2264 }
2265
2266 /* tbitb. */
2267 void
2268 OP_10D_14 (void)
2269 {
2270 uint8 a = (OP[0]) & 0xff;
2271 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2272 trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2273 tmp = RB (addr);
2274 SET_PSR_F (tmp & (1 << a));
2275 trace_output_32 (addr);
2276 }
2277
2278 /* tbitb. */
2279 void
2280 OP_10E_14 (void)
2281 {
2282 uint8 a = (OP[0]) & 0xff;
2283 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2284 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2285 tmp = RB (addr);
2286 SET_PSR_F (tmp & (1 << a));
2287 trace_output_32 (addr);
2288 }
2289
2290
2291 /* tbitw. */
2292 void
2293 OP_7F_8 (void)
2294 {
2295 uint16 a = OP[0];
2296 uint32 addr = OP[1], tmp;
2297 trace_input ("tbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2298 tmp = RW (addr);
2299 SET_PSR_F (tmp & (1 << a));
2300 trace_output_32 (tmp);
2301 }
2302
2303 /* tbitw. */
2304 void
2305 OP_11F_14 (void)
2306 {
2307 uint16 a = OP[0];
2308 uint32 addr = OP[1], tmp;
2309 trace_input ("tbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2310 tmp = RW (addr);
2311 SET_PSR_F (tmp & (1 << a));
2312 trace_output_32 (tmp);
2313 }
2314
2315
2316 /* tbitw. */
2317 void
2318 OP_3E_7 (void)
2319 {
2320 uint32 addr;
2321 uint16 a = (OP[0]), tmp;
2322 trace_input ("tbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
2323
2324 if (OP[1] == 0)
2325 addr = (GPR32 (12)) + OP[2];
2326 else
2327 addr = (GPR32 (13)) + OP[2];
2328
2329 tmp = RW (addr);
2330 SET_PSR_F (tmp & (1 << a));
2331 trace_output_32 (addr);
2332 }
2333
2334 /* tbitw. */
2335 void
2336 OP_1EB_A (void)
2337 {
2338 uint16 a = (OP[0]);
2339 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2340 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2341 tmp = RW (addr);
2342 SET_PSR_F (tmp & (1 << a));
2343 trace_output_32 (addr);
2344 }
2345
2346 /* tbitw. */
2347 void
2348 OP_11C_14 (void)
2349 {
2350 uint16 a = (OP[0]);
2351 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2352 trace_input ("tbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2353 tmp = RW (addr);
2354 SET_PSR_F (tmp & (1 << a));
2355 trace_output_32 (addr);
2356 }
2357
2358 /* tbitw. */
2359 void
2360 OP_7E_8 (void)
2361 {
2362 uint16 a = (OP[0]);
2363 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2364 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2365 tmp = RW (addr);
2366 SET_PSR_F (tmp & (1 << a));
2367 trace_output_32 (addr);
2368 }
2369
2370 /* tbitw. */
2371 void
2372 OP_79_8 (void)
2373 {
2374 uint16 a = (OP[0]);
2375 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2376 trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2377 tmp = RW (addr);
2378 SET_PSR_F (tmp & (1 << a));
2379 trace_output_32 (addr);
2380 }
2381
2382 /* tbitw. */
2383 void
2384 OP_11D_14 (void)
2385 {
2386 uint16 a = (OP[0]);
2387 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2388 trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2389 tmp = RW (addr);
2390 SET_PSR_F (tmp & (1 << a));
2391 trace_output_32 (addr);
2392 }
2393
2394
2395 /* tbitw. */
2396 void
2397 OP_11E_14 (void)
2398 {
2399 uint16 a = (OP[0]);
2400 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2401 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2402 tmp = RW (addr);
2403 SET_PSR_F (tmp & (1 << a));
2404 trace_output_32 (addr);
2405 }
2406
2407
2408 /* tbit. */
2409 void
2410 OP_6_8 (void)
2411 {
2412 uint16 a = OP[0];
2413 uint16 b = (GPR (OP[1]));
2414 trace_input ("tbit", OP_CONSTANT4, OP_REG, OP_VOID);
2415 SET_PSR_F (b & (1 << a));
2416 trace_output_16 (b);
2417 }
2418
2419 /* tbit. */
2420 void
2421 OP_7_8 (void)
2422 {
2423 uint16 a = GPR (OP[0]);
2424 uint16 b = (GPR (OP[1]));
2425 trace_input ("tbit", OP_REG, OP_REG, OP_VOID);
2426 SET_PSR_F (b & (1 << a));
2427 trace_output_16 (b);
2428 }
2429
2430
2431 /* cmpb. */
2432 void
2433 OP_50_8 (void)
2434 {
2435 uint8 a = (OP[0]) & 0xFF;
2436 uint8 b = (GPR (OP[1])) & 0xFF;
2437 trace_input ("cmpb", OP_CONSTANT4, OP_REG, OP_VOID);
2438 SET_PSR_Z (a == b);
2439 SET_PSR_N ((int8)a > (int8)b);
2440 SET_PSR_L (a > b);
2441 trace_output_flag ();
2442 }
2443
2444 /* cmpb. */
2445 void
2446 OP_50B_C (void)
2447 {
2448 uint8 a = (OP[0]) & 0xFF;
2449 uint8 b = (GPR (OP[1])) & 0xFF;
2450 trace_input ("cmpb", OP_CONSTANT16, OP_REG, OP_VOID);
2451 SET_PSR_Z (a == b);
2452 SET_PSR_N ((int8)a > (int8)b);
2453 SET_PSR_L (a > b);
2454 trace_output_flag ();
2455 }
2456
2457 /* cmpb. */
2458 void
2459 OP_51_8 (void)
2460 {
2461 uint8 a = (GPR (OP[0])) & 0xFF;
2462 uint8 b = (GPR (OP[1])) & 0xFF;
2463 trace_input ("cmpb", OP_REG, OP_REG, OP_VOID);
2464 SET_PSR_Z (a == b);
2465 SET_PSR_N ((int8)a > (int8)b);
2466 SET_PSR_L (a > b);
2467 trace_output_flag ();
2468 }
2469
2470 /* cmpw. */
2471 void
2472 OP_52_8 (void)
2473 {
2474 uint16 a = (OP[0]);
2475 uint16 b = GPR (OP[1]);
2476 trace_input ("cmpw", OP_CONSTANT4, OP_REG, OP_VOID);
2477 SET_PSR_Z (a == b);
2478 SET_PSR_N ((int16)a > (int16)b);
2479 SET_PSR_L (a > b);
2480 trace_output_flag ();
2481 }
2482
2483 /* cmpw. */
2484 void
2485 OP_52B_C (void)
2486 {
2487 uint16 a = (OP[0]);
2488 uint16 b = GPR (OP[1]);
2489 trace_input ("cmpw", OP_CONSTANT16, OP_REG, OP_VOID);
2490 SET_PSR_Z (a == b);
2491 SET_PSR_N ((int16)a > (int16)b);
2492 SET_PSR_L (a > b);
2493 trace_output_flag ();
2494 }
2495
2496 /* cmpw. */
2497 void
2498 OP_53_8 (void)
2499 {
2500 uint16 a = GPR (OP[0]) ;
2501 uint16 b = GPR (OP[1]) ;
2502 trace_input ("cmpw", OP_REG, OP_REG, OP_VOID);
2503 SET_PSR_Z (a == b);
2504 SET_PSR_N ((int16)a > (int16)b);
2505 SET_PSR_L (a > b);
2506 trace_output_flag ();
2507 }
2508
2509 /* cmpd. */
2510 void
2511 OP_56_8 (void)
2512 {
2513 uint32 a = (OP[0]);
2514 uint32 b = GPR32 (OP[1]);
2515 trace_input ("cmpd", OP_CONSTANT4, OP_REGP, OP_VOID);
2516 SET_PSR_Z (a == b);
2517 SET_PSR_N ((int32)a > (int32)b);
2518 SET_PSR_L (a > b);
2519 trace_output_flag ();
2520 }
2521
2522 /* cmpd. */
2523 void
2524 OP_56B_C (void)
2525 {
2526 uint32 a = (SEXT16(OP[0]));
2527 uint32 b = GPR32 (OP[1]);
2528 trace_input ("cmpd", OP_CONSTANT16, OP_REGP, OP_VOID);
2529 SET_PSR_Z (a == b);
2530 SET_PSR_N ((int32)a > (int32)b);
2531 SET_PSR_L (a > b);
2532 trace_output_flag ();
2533 }
2534
2535 /* cmpd. */
2536 void
2537 OP_57_8 (void)
2538 {
2539 uint32 a = GPR32 (OP[0]) ;
2540 uint32 b = GPR32 (OP[1]) ;
2541 trace_input ("cmpd", OP_REGP, OP_REGP, OP_VOID);
2542 SET_PSR_Z (a == b);
2543 SET_PSR_N ((int32)a > (int32)b);
2544 SET_PSR_L (a > b);
2545 trace_output_flag ();
2546 }
2547
2548 /* cmpd. */
2549 void
2550 OP_9_C (void)
2551 {
2552 uint32 a = (OP[0]);
2553 uint32 b = GPR32 (OP[1]);
2554 trace_input ("cmpd", OP_CONSTANT32, OP_REGP, OP_VOID);
2555 SET_PSR_Z (a == b);
2556 SET_PSR_N ((int32)a > (int32)b);
2557 SET_PSR_L (a > b);
2558 trace_output_flag ();
2559 }
2560
2561
2562 /* movb. */
2563 void
2564 OP_58_8 (void)
2565 {
2566 uint8 tmp = OP[0] & 0xFF;
2567 uint16 a = (GPR (OP[1])) & 0xFF00;
2568 trace_input ("movb", OP_CONSTANT4, OP_REG, OP_VOID);
2569 SET_GPR (OP[1], (a | tmp));
2570 trace_output_16 (tmp);
2571 }
2572
2573 /* movb. */
2574 void
2575 OP_58B_C (void)
2576 {
2577 uint8 tmp = OP[0] & 0xFF;
2578 uint16 a = (GPR (OP[1])) & 0xFF00;
2579 trace_input ("movb", OP_CONSTANT16, OP_REG, OP_VOID);
2580 SET_GPR (OP[1], (a | tmp));
2581 trace_output_16 (tmp);
2582 }
2583
2584 /* movb. */
2585 void
2586 OP_59_8 (void)
2587 {
2588 uint8 tmp = (GPR (OP[0])) & 0xFF;
2589 uint16 a = (GPR (OP[1])) & 0xFF00;
2590 trace_input ("movb", OP_REG, OP_REG, OP_VOID);
2591 SET_GPR (OP[1], (a | tmp));
2592 trace_output_16 (tmp);
2593 }
2594
2595 /* movw. */
2596 void
2597 OP_5A_8 (void)
2598 {
2599 uint16 tmp = OP[0];
2600 trace_input ("movw", OP_CONSTANT4_1, OP_REG, OP_VOID);
2601 SET_GPR (OP[1], (tmp & 0xffff));
2602 trace_output_16 (tmp);
2603 }
2604
2605 /* movw. */
2606 void
2607 OP_5AB_C (void)
2608 {
2609 int16 tmp = OP[0];
2610 trace_input ("movw", OP_CONSTANT16, OP_REG, OP_VOID);
2611 SET_GPR (OP[1], (tmp & 0xffff));
2612 trace_output_16 (tmp);
2613 }
2614
2615 /* movw. */
2616 void
2617 OP_5B_8 (void)
2618 {
2619 uint16 tmp = GPR (OP[0]);
2620 uint32 a = GPR32 (OP[1]);
2621 trace_input ("movw", OP_REG, OP_REGP, OP_VOID);
2622 a = (a & 0xffff0000) | tmp;
2623 SET_GPR32 (OP[1], a);
2624 trace_output_16 (tmp);
2625 }
2626
2627 /* movxb. */
2628 void
2629 OP_5C_8 (void)
2630 {
2631 uint8 tmp = (GPR (OP[0])) & 0xFF;
2632 trace_input ("movxb", OP_REG, OP_REG, OP_VOID);
2633 SET_GPR (OP[1], ((SEXT8(tmp)) & 0xffff));
2634 trace_output_16 (tmp);
2635 }
2636
2637 /* movzb. */
2638 void
2639 OP_5D_8 (void)
2640 {
2641 uint8 tmp = (GPR (OP[0])) & 0xFF;
2642 trace_input ("movzb", OP_REG, OP_REG, OP_VOID);
2643 SET_GPR (OP[1], tmp);
2644 trace_output_16 (tmp);
2645 }
2646
2647 /* movxw. */
2648 void
2649 OP_5E_8 (void)
2650 {
2651 uint16 tmp = GPR (OP[0]);
2652 trace_input ("movxw", OP_REG, OP_REGP, OP_VOID);
2653 SET_GPR32 (OP[1], SEXT16(tmp));
2654 trace_output_16 (tmp);
2655 }
2656
2657 /* movzw. */
2658 void
2659 OP_5F_8 (void)
2660 {
2661 uint16 tmp = GPR (OP[0]);
2662 trace_input ("movzw", OP_REG, OP_REGP, OP_VOID);
2663 SET_GPR32 (OP[1], (tmp & 0x0000FFFF));
2664 trace_output_16 (tmp);
2665 }
2666
2667 /* movd. */
2668 void
2669 OP_54_8 (void)
2670 {
2671 int32 tmp = OP[0];
2672 trace_input ("movd", OP_CONSTANT4, OP_REGP, OP_VOID);
2673 SET_GPR32 (OP[1], tmp);
2674 trace_output_32 (tmp);
2675 }
2676
2677 /* movd. */
2678 void
2679 OP_54B_C (void)
2680 {
2681 int32 tmp = SEXT16(OP[0]);
2682 trace_input ("movd", OP_CONSTANT16, OP_REGP, OP_VOID);
2683 SET_GPR32 (OP[1], tmp);
2684 trace_output_32 (tmp);
2685 }
2686
2687 /* movd. */
2688 void
2689 OP_55_8 (void)
2690 {
2691 uint32 tmp = GPR32 (OP[0]);
2692 trace_input ("movd", OP_REGP, OP_REGP, OP_VOID);
2693 SET_GPR32 (OP[1], tmp);
2694 trace_output_32 (tmp);
2695 }
2696
2697 /* movd. */
2698 void
2699 OP_5_8 (void)
2700 {
2701 uint32 tmp = OP[0];
2702 trace_input ("movd", OP_CONSTANT20, OP_REGP, OP_VOID);
2703 SET_GPR32 (OP[1], tmp);
2704 trace_output_32 (tmp);
2705 }
2706
2707 /* movd. */
2708 void
2709 OP_7_C (void)
2710 {
2711 int32 tmp = OP[0];
2712 trace_input ("movd", OP_CONSTANT32, OP_REGP, OP_VOID);
2713 SET_GPR32 (OP[1], tmp);
2714 trace_output_32 (tmp);
2715 }
2716
2717 /* loadm. */
2718 void
2719 OP_14_D (void)
2720 {
2721 uint32 addr = GPR (0);
2722 uint16 count = OP[0], reg = 2, tmp;
2723 trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID);
2724 if ((addr & 1))
2725 {
2726 State.exception = SIG_CR16_BUS;
2727 State.pc_changed = 1; /* Don't increment the PC. */
2728 trace_output_void ();
2729 return;
2730 }
2731
2732 while (count)
2733 {
2734 tmp = RW (addr);
2735 SET_GPR (reg, tmp);
2736 addr +=2;
2737 --count;
2738 reg++;
2739 if (reg == 6) reg = 8;
2740 };
2741
2742 SET_GPR (0, addr);
2743 trace_output_void ();
2744 }
2745
2746
2747 /* loadmp. */
2748 void
2749 OP_15_D (void)
2750 {
2751 uint32 addr = GPR32 (0);
2752 uint16 count = OP[0], reg = 2, tmp;
2753 trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID);
2754 if ((addr & 1))
2755 {
2756 State.exception = SIG_CR16_BUS;
2757 State.pc_changed = 1; /* Don't increment the PC. */
2758 trace_output_void ();
2759 return;
2760 }
2761
2762 while (count)
2763 {
2764 tmp = RW (addr);
2765 SET_GPR (reg, tmp);
2766 addr +=2;
2767 --count;
2768 reg++;
2769 if (reg == 6) reg = 8;
2770 };
2771
2772 SET_GPR32 (0, addr);
2773 trace_output_void ();
2774 }
2775
2776
2777 /* loadb. */
2778 void
2779 OP_88_8 (void)
2780 {
2781 /* loadb ABS20, REG
2782 * ADDR = zext24(abs20) | remap (ie 0xF00000)
2783 * REG = [ADDR]
2784 * NOTE: remap is
2785 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
2786 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
2787 * by the core to 16M-64k to 16M. */
2788
2789 uint16 tmp, a = (GPR (OP[1])) & 0xFF00;
2790 uint32 addr = OP[0];
2791 trace_input ("loadb", OP_ABS20, OP_REG, OP_VOID);
2792 if (addr > 0xEFFFF) addr |= 0xF00000;
2793 tmp = (RB (addr));
2794 SET_GPR (OP[1], (a | tmp));
2795 trace_output_16 (tmp);
2796 }
2797
2798 /* loadb. */
2799 void
2800 OP_127_14 (void)
2801 {
2802 /* loadb ABS24, REG
2803 * ADDR = abs24
2804 * REGR = [ADDR]. */
2805
2806 uint16 tmp, a = (GPR (OP[1])) & 0xFF00;
2807 uint32 addr = OP[0];
2808 trace_input ("loadb", OP_ABS24, OP_REG, OP_VOID);
2809 tmp = (RB (addr));
2810 SET_GPR (OP[1], (a | tmp));
2811 trace_output_16 (tmp);
2812 }
2813
2814 /* loadb. */
2815 void
2816 OP_45_7 (void)
2817 {
2818 /* loadb [Rindex]ABS20 REG
2819 * ADDR = Rindex + zext24(disp20)
2820 * REGR = [ADDR]. */
2821
2822 uint32 addr;
2823 uint16 tmp, a = (GPR (OP[2])) & 0xFF00;
2824 trace_input ("loadb", OP_R_INDEX8_ABS20, OP_REG, OP_VOID);
2825
2826 if (OP[0] == 0)
2827 addr = (GPR32 (12)) + OP[1];
2828 else
2829 addr = (GPR32 (13)) + OP[1];
2830
2831 tmp = (RB (addr));
2832 SET_GPR (OP[2], (a | tmp));
2833 trace_output_16 (tmp);
2834 }
2835
2836
2837 /* loadb. */
2838 void
2839 OP_B_4 (void)
2840 {
2841 /* loadb DIPS4(REGP) REG
2842 * ADDR = RPBASE + zext24(DISP4)
2843 * REG = [ADDR]. */
2844 uint16 tmp, a = (GPR (OP[2])) & 0xFF00;
2845 uint32 addr = (GPR32 (OP[1])) + OP[0];
2846 trace_input ("loadb", OP_RP_BASE_DISP4, OP_REG, OP_VOID);
2847 tmp = (RB (addr));
2848 SET_GPR (OP[2], (a | tmp));
2849 trace_output_16 (tmp);
2850 }
2851
2852 /* loadb. */
2853 void
2854 OP_BE_8 (void)
2855 {
2856 /* loadb [Rindex]disp0(RPbasex) REG
2857 * ADDR = Rpbasex + Rindex
2858 * REGR = [ADDR] */
2859
2860 uint32 addr;
2861 uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
2862 trace_input ("loadb", OP_RP_INDEX_DISP0, OP_REG, OP_VOID);
2863
2864 addr = (GPR32 (OP[2])) + OP[1];
2865
2866 if (OP[0] == 0)
2867 addr = (GPR32 (12)) + addr;
2868 else
2869 addr = (GPR32 (13)) + addr;
2870
2871 tmp = (RB (addr));
2872 SET_GPR (OP[3], (a | tmp));
2873 trace_output_16 (tmp);
2874 }
2875
2876 /* loadb. */
2877 void
2878 OP_219_A (void)
2879 {
2880 /* loadb [Rindex]disp14(RPbasex) REG
2881 * ADDR = Rpbasex + Rindex + zext24(disp14)
2882 * REGR = [ADDR] */
2883
2884 uint32 addr;
2885 uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
2886
2887 addr = (GPR32 (OP[2])) + OP[1];
2888
2889 if (OP[0] == 0)
2890 addr = (GPR32 (12)) + addr;
2891 else
2892 addr = (GPR32 (13)) + addr;
2893
2894 trace_input ("loadb", OP_RP_INDEX_DISP14, OP_REG, OP_VOID);
2895 tmp = (RB (addr));
2896 SET_GPR (OP[3], (a | tmp));
2897 trace_output_16 (tmp);
2898 }
2899
2900
2901 /* loadb. */
2902 void
2903 OP_184_14 (void)
2904 {
2905 /* loadb DISPE20(REG) REG
2906 * zext24(Rbase) + zext24(dispe20)
2907 * REG = [ADDR] */
2908
2909 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2910 uint32 addr = OP[0] + (GPR (OP[1]));
2911 trace_input ("loadb", OP_R_BASE_DISPE20, OP_REG, OP_VOID);
2912 tmp = (RB (addr));
2913 SET_GPR (OP[2], (a | tmp));
2914 trace_output_16 (tmp);
2915 }
2916
2917 /* loadb. */
2918 void
2919 OP_124_14 (void)
2920 {
2921 /* loadb DISP20(REG) REG
2922 * ADDR = zext24(Rbase) + zext24(disp20)
2923 * REG = [ADDR] */
2924
2925 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2926 uint32 addr = OP[0] + (GPR (OP[1]));
2927 trace_input ("loadb", OP_R_BASE_DISP20, OP_REG, OP_VOID);
2928 tmp = (RB (addr));
2929 SET_GPR (OP[2], (a | tmp));
2930 trace_output_16 (tmp);
2931 }
2932
2933 /* loadb. */
2934 void
2935 OP_BF_8 (void)
2936 {
2937 /* loadb disp16(REGP) REG
2938 * ADDR = RPbase + zext24(disp16)
2939 * REGR = [ADDR] */
2940
2941 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2942 uint32 addr = (GPR32 (OP[1])) + OP[0];
2943 trace_input ("loadb", OP_RP_BASE_DISP16, OP_REG, OP_VOID);
2944 tmp = (RB (addr));
2945 SET_GPR (OP[2], (a | tmp));
2946 trace_output_16 (tmp);
2947 }
2948
2949 /* loadb. */
2950 void
2951 OP_125_14 (void)
2952 {
2953 /* loadb disp20(REGP) REG
2954 * ADDR = RPbase + zext24(disp20)
2955 * REGR = [ADDR] */
2956 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2957 uint32 addr = (GPR32 (OP[1])) + OP[0];
2958 trace_input ("loadb", OP_RP_BASE_DISP20, OP_REG, OP_VOID);
2959 tmp = (RB (addr));
2960 SET_GPR (OP[2], (a | tmp));
2961 trace_output_16 (tmp);
2962 }
2963
2964
2965 /* loadb. */
2966 void
2967 OP_185_14 (void)
2968 {
2969 /* loadb -disp20(REGP) REG
2970 * ADDR = RPbase + zext24(-disp20)
2971 * REGR = [ADDR] */
2972 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2973 uint32 addr = (GPR32 (OP[1])) + OP[1];
2974 trace_input ("loadb", OP_RP_BASE_DISPE20, OP_REG, OP_VOID);
2975 tmp = (RB (addr));
2976 SET_GPR (OP[2], (a | tmp));
2977 trace_output_16 (tmp);
2978 }
2979
2980 /* loadb. */
2981 void
2982 OP_126_14 (void)
2983 {
2984 /* loadb [Rindex]disp20(RPbasexb) REG
2985 * ADDR = RPbasex + Rindex + zext24(disp20)
2986 * REGR = [ADDR] */
2987
2988 uint32 addr;
2989 uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
2990 trace_input ("loadb", OP_RP_INDEX_DISP20, OP_REG, OP_VOID);
2991
2992 addr = (GPR32 (OP[2])) + OP[1];
2993
2994 if (OP[0] == 0)
2995 addr = (GPR32 (12)) + addr;
2996 else
2997 addr = (GPR32 (13)) + addr;
2998
2999 tmp = (RB (addr));
3000 SET_GPR (OP[3], (a | tmp));
3001 trace_output_16 (tmp);
3002 }
3003
3004
3005 /* loadw. */
3006 void
3007 OP_89_8 (void)
3008 {
3009 /* loadw ABS20, REG
3010 * ADDR = zext24(abs20) | remap
3011 * REGR = [ADDR]
3012 * NOTE: remap is
3013 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3014 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3015 * by the core to 16M-64k to 16M. */
3016
3017 uint16 tmp;
3018 uint32 addr = OP[0];
3019 trace_input ("loadw", OP_ABS20, OP_REG, OP_VOID);
3020 if (addr > 0xEFFFF) addr |= 0xF00000;
3021 tmp = (RW (addr));
3022 SET_GPR (OP[1], tmp);
3023 trace_output_16 (tmp);
3024 }
3025
3026
3027 /* loadw. */
3028 void
3029 OP_12F_14 (void)
3030 {
3031 /* loadw ABS24, REG
3032 * ADDR = abs24
3033 * REGR = [ADDR] */
3034 uint16 tmp;
3035 uint32 addr = OP[0];
3036 trace_input ("loadw", OP_ABS24, OP_REG, OP_VOID);
3037 tmp = (RW (addr));
3038 SET_GPR (OP[1], tmp);
3039 trace_output_16 (tmp);
3040 }
3041
3042 /* loadw. */
3043 void
3044 OP_47_7 (void)
3045 {
3046 /* loadw [Rindex]ABS20 REG
3047 * ADDR = Rindex + zext24(disp20)
3048 * REGR = [ADDR] */
3049
3050 uint32 addr;
3051 uint16 tmp;
3052 trace_input ("loadw", OP_R_INDEX8_ABS20, OP_REG, OP_VOID);
3053
3054 if (OP[0] == 0)
3055 addr = (GPR32 (12)) + OP[1];
3056 else
3057 addr = (GPR32 (13)) + OP[1];
3058
3059 tmp = (RW (addr));
3060 SET_GPR (OP[2], tmp);
3061 trace_output_16 (tmp);
3062 }
3063
3064
3065 /* loadw. */
3066 void
3067 OP_9_4 (void)
3068 {
3069 /* loadw DIPS4(REGP) REGP
3070 * ADDR = RPBASE + zext24(DISP4)
3071 * REGP = [ADDR]. */
3072 uint16 tmp;
3073 uint32 addr, a;
3074 trace_input ("loadw", OP_RP_BASE_DISP4, OP_REG, OP_VOID);
3075 addr = (GPR32 (OP[1])) + OP[0];
3076 tmp = (RW (addr));
3077 if (OP[2] > 11)
3078 {
3079 a = (GPR32 (OP[2])) & 0xffff0000;
3080 SET_GPR32 (OP[2], (a | tmp));
3081 }
3082 else
3083 SET_GPR (OP[2], tmp);
3084
3085 trace_output_16 (tmp);
3086 }
3087
3088
3089 /* loadw. */
3090 void
3091 OP_9E_8 (void)
3092 {
3093 /* loadw [Rindex]disp0(RPbasex) REG
3094 * ADDR = Rpbasex + Rindex
3095 * REGR = [ADDR] */
3096
3097 uint32 addr;
3098 uint16 tmp;
3099 trace_input ("loadw", OP_RP_INDEX_DISP0, OP_REG, OP_VOID);
3100
3101 addr = (GPR32 (OP[2])) + OP[1];
3102
3103 if (OP[0] == 0)
3104 addr = (GPR32 (12)) + addr;
3105 else
3106 addr = (GPR32 (13)) + addr;
3107
3108 tmp = RW (addr);
3109 SET_GPR (OP[3], tmp);
3110 trace_output_16 (tmp);
3111 }
3112
3113
3114 /* loadw. */
3115 void
3116 OP_21B_A (void)
3117 {
3118 /* loadw [Rindex]disp14(RPbasex) REG
3119 * ADDR = Rpbasex + Rindex + zext24(disp14)
3120 * REGR = [ADDR] */
3121
3122 uint32 addr;
3123 uint16 tmp;
3124 trace_input ("loadw", OP_RP_INDEX_DISP14, OP_REG, OP_VOID);
3125 addr = (GPR32 (OP[2])) + OP[1];
3126
3127 if (OP[0] == 0)
3128 addr = (GPR32 (12)) + addr;
3129 else
3130 addr = (GPR32 (13)) + addr;
3131
3132 tmp = (RW (addr));
3133 SET_GPR (OP[3], tmp);
3134 trace_output_16 (tmp);
3135 }
3136
3137 /* loadw. */
3138 void
3139 OP_18C_14 (void)
3140 {
3141 /* loadw dispe20(REG) REGP
3142 * REGP = [DISPE20+[REG]] */
3143
3144 uint16 tmp;
3145 uint32 addr, a;
3146 trace_input ("loadw", OP_R_BASE_DISPE20, OP_REGP, OP_VOID);
3147 addr = OP[0] + (GPR (OP[1]));
3148 tmp = (RW (addr));
3149 if (OP[2] > 11)
3150 {
3151 a = (GPR32 (OP[2])) & 0xffff0000;
3152 SET_GPR32 (OP[2], (a | tmp));
3153 }
3154 else
3155 SET_GPR (OP[2], tmp);
3156
3157 trace_output_16 (tmp);
3158 }
3159
3160
3161 /* loadw. */
3162 void
3163 OP_12C_14 (void)
3164 {
3165 /* loadw DISP20(REG) REGP
3166 * ADDR = zext24(Rbase) + zext24(disp20)
3167 * REGP = [ADDR] */
3168
3169 uint16 tmp;
3170 uint32 addr, a;
3171 trace_input ("loadw", OP_R_BASE_DISP20, OP_REGP, OP_VOID);
3172 addr = OP[0] + (GPR (OP[1]));
3173 tmp = (RW (addr));
3174 if (OP[2] > 11)
3175 {
3176 a = (GPR32 (OP[2])) & 0xffff0000;
3177 SET_GPR32 (OP[2], (a | tmp));
3178 }
3179 else
3180 SET_GPR (OP[2], tmp);
3181
3182 trace_output_16 (tmp);
3183 }
3184
3185 /* loadw. */
3186 void
3187 OP_9F_8 (void)
3188 {
3189 /* loadw disp16(REGP) REGP
3190 * ADDR = RPbase + zext24(disp16)
3191 * REGP = [ADDR] */
3192 uint16 tmp;
3193 uint32 addr, a;
3194 trace_input ("loadw", OP_RP_BASE_DISP16, OP_REGP, OP_VOID);
3195 addr = (GPR32 (OP[1])) + OP[0];
3196 tmp = (RW (addr));
3197 if (OP[2] > 11)
3198 {
3199 a = (GPR32 (OP[2])) & 0xffff0000;
3200 SET_GPR32 (OP[2], (a | tmp));
3201 }
3202 else
3203 SET_GPR (OP[2], tmp);
3204
3205 trace_output_16 (tmp);
3206 }
3207
3208 /* loadw. */
3209 void
3210 OP_12D_14 (void)
3211 {
3212 /* loadw disp20(REGP) REGP
3213 * ADDR = RPbase + zext24(disp20)
3214 * REGP = [ADDR] */
3215 uint16 tmp;
3216 uint32 addr, a;
3217 trace_input ("loadw", OP_RP_BASE_DISP20, OP_REG, OP_VOID);
3218 addr = (GPR32 (OP[1])) + OP[0];
3219 tmp = (RW (addr));
3220 if (OP[2] > 11)
3221 {
3222 a = (GPR32 (OP[2])) & 0xffff0000;
3223 SET_GPR32 (OP[2], (a | tmp));
3224 }
3225 else
3226 SET_GPR (OP[2], tmp);
3227
3228 trace_output_16 (tmp);
3229 }
3230
3231 /* loadw. */
3232 void
3233 OP_18D_14 (void)
3234 {
3235 /* loadw -disp20(REGP) REG
3236 * ADDR = RPbase + zext24(-disp20)
3237 * REGR = [ADDR] */
3238
3239 uint16 tmp;
3240 uint32 addr, a;
3241 trace_input ("loadw", OP_RP_BASE_DISPE20, OP_REG, OP_VOID);
3242 addr = (GPR32 (OP[1])) + OP[0];
3243 tmp = (RB (addr));
3244 if (OP[2] > 11)
3245 {
3246 a = (GPR32 (OP[2])) & 0xffff0000;
3247 SET_GPR32 (OP[2], (a | tmp));
3248 }
3249 else
3250 SET_GPR (OP[2], tmp);
3251
3252 trace_output_16 (tmp);
3253 }
3254
3255
3256 /* loadw. */
3257 void
3258 OP_12E_14 (void)
3259 {
3260 /* loadw [Rindex]disp20(RPbasexb) REG
3261 * ADDR = RPbasex + Rindex + zext24(disp20)
3262 * REGR = [ADDR] */
3263
3264 uint32 addr;
3265 uint16 tmp;
3266 trace_input ("loadw", OP_RP_INDEX_DISP20, OP_REG, OP_VOID);
3267
3268 if (OP[0] == 0)
3269 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3270 else
3271 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3272
3273 tmp = (RW (addr));
3274 SET_GPR (OP[3], tmp);
3275 trace_output_16 (tmp);
3276 }
3277
3278
3279 /* loadd. */
3280 void
3281 OP_87_8 (void)
3282 {
3283 /* loadd ABS20, REGP
3284 * ADDR = zext24(abs20) | remap
3285 * REGP = [ADDR]
3286 * NOTE: remap is
3287 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3288 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3289 * by the core to 16M-64k to 16M. */
3290
3291 uint32 addr, tmp;
3292 addr = OP[0];
3293 trace_input ("loadd", OP_ABS20, OP_REGP, OP_VOID);
3294 if (addr > 0xEFFFF) addr |= 0xF00000;
3295 tmp = RLW (addr);
3296 tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff);
3297 SET_GPR32 (OP[1], tmp);
3298 trace_output_32 (tmp);
3299 }
3300
3301 /* loadd. */
3302 void
3303 OP_12B_14 (void)
3304 {
3305 /* loadd ABS24, REGP
3306 * ADDR = abs24
3307 * REGP = [ADDR] */
3308
3309 uint32 addr = OP[0];
3310 uint32 tmp;
3311 trace_input ("loadd", OP_ABS24, OP_REGP, OP_VOID);
3312 tmp = RLW (addr);
3313 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3314 SET_GPR32 (OP[1],tmp);
3315 trace_output_32 (tmp);
3316 }
3317
3318
3319 /* loadd. */
3320 void
3321 OP_46_7 (void)
3322 {
3323 /* loadd [Rindex]ABS20 REGP
3324 * ADDR = Rindex + zext24(disp20)
3325 * REGP = [ADDR] */
3326
3327 uint32 addr, tmp;
3328 trace_input ("loadd", OP_R_INDEX8_ABS20, OP_REGP, OP_VOID);
3329
3330 if (OP[0] == 0)
3331 addr = (GPR32 (12)) + OP[1];
3332 else
3333 addr = (GPR32 (13)) + OP[1];
3334
3335 tmp = RLW (addr);
3336 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3337 SET_GPR32 (OP[2], tmp);
3338 trace_output_32 (tmp);
3339 }
3340
3341
3342 /* loadd. */
3343 void
3344 OP_A_4 (void)
3345 {
3346 /* loadd dips4(regp) REGP
3347 * ADDR = Rpbase + zext24(disp4)
3348 * REGP = [ADDR] */
3349
3350 uint32 tmp, addr = (GPR32 (OP[1])) + OP[0];
3351 trace_input ("loadd", OP_RP_BASE_DISP4, OP_REGP, OP_VOID);
3352 tmp = RLW (addr);
3353 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3354 SET_GPR32 (OP[2], tmp);
3355 trace_output_32 (tmp);
3356 }
3357
3358
3359 /* loadd. */
3360 void
3361 OP_AE_8 (void)
3362 {
3363 /* loadd [Rindex]disp0(RPbasex) REGP
3364 * ADDR = Rpbasex + Rindex
3365 * REGP = [ADDR] */
3366
3367 uint32 addr, tmp;
3368 trace_input ("loadd", OP_RP_INDEX_DISP0, OP_REGP, OP_VOID);
3369
3370 if (OP[0] == 0)
3371 addr = (GPR32 (12)) + (GPR32 (OP[2])) + OP[1];
3372 else
3373 addr = (GPR32 (13)) + (GPR32 (OP[2])) + OP[1];
3374
3375 tmp = RLW (addr);
3376 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3377 SET_GPR32 (OP[3], tmp);
3378 trace_output_32 (tmp);
3379 }
3380
3381
3382 /* loadd. */
3383 void
3384 OP_21A_A (void)
3385 {
3386 /* loadd [Rindex]disp14(RPbasex) REGP
3387 * ADDR = Rpbasex + Rindex + zext24(disp14)
3388 * REGR = [ADDR] */
3389
3390 uint32 addr, tmp;
3391 trace_input ("loadd", OP_RP_INDEX_DISP14, OP_REGP, OP_VOID);
3392
3393 if (OP[0] == 0)
3394 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3395 else
3396 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3397
3398 tmp = RLW (addr);
3399 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3400 SET_GPR (OP[3],tmp);
3401 trace_output_32 (tmp);
3402 }
3403
3404
3405 /* loadd. */
3406 void
3407 OP_188_14 (void)
3408 {
3409 /* loadd dispe20(REG) REG
3410 * zext24(Rbase) + zext24(dispe20)
3411 * REG = [ADDR] */
3412
3413 uint32 tmp, addr = OP[0] + (GPR (OP[1]));
3414 trace_input ("loadd", OP_R_BASE_DISPE20, OP_REGP, OP_VOID);
3415 tmp = RLW (addr);
3416 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3417 SET_GPR32 (OP[2], tmp);
3418 trace_output_32 (tmp);
3419 }
3420
3421
3422 /* loadd. */
3423 void
3424 OP_128_14 (void)
3425 {
3426 /* loadd DISP20(REG) REG
3427 * ADDR = zext24(Rbase) + zext24(disp20)
3428 * REG = [ADDR] */
3429
3430 uint32 tmp, addr = OP[0] + (GPR (OP[1]));
3431 trace_input ("loadd", OP_R_BASE_DISP20, OP_REGP, OP_VOID);
3432 tmp = RLW (addr);
3433 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3434 SET_GPR32 (OP[2], tmp);
3435 trace_output_32 (tmp);
3436 }
3437
3438 /* loadd. */
3439 void
3440 OP_AF_8 (void)
3441 {
3442 /* loadd disp16(REGP) REGP
3443 * ADDR = RPbase + zext24(disp16)
3444 * REGR = [ADDR] */
3445 uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
3446 trace_input ("loadd", OP_RP_BASE_DISP16, OP_REGP, OP_VOID);
3447 tmp = RLW (addr);
3448 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3449 SET_GPR32 (OP[2], tmp);
3450 trace_output_32 (tmp);
3451 }
3452
3453
3454 /* loadd. */
3455 void
3456 OP_129_14 (void)
3457 {
3458 /* loadd disp20(REGP) REGP
3459 * ADDR = RPbase + zext24(disp20)
3460 * REGP = [ADDR] */
3461 uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
3462 trace_input ("loadd", OP_RP_BASE_DISP20, OP_REGP, OP_VOID);
3463 tmp = RLW (addr);
3464 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3465 SET_GPR32 (OP[2], tmp);
3466 trace_output_32 (tmp);
3467 }
3468
3469 /* loadd. */
3470 void
3471 OP_189_14 (void)
3472 {
3473 /* loadd -disp20(REGP) REGP
3474 * ADDR = RPbase + zext24(-disp20)
3475 * REGP = [ADDR] */
3476
3477 uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
3478 trace_input ("loadd", OP_RP_BASE_DISPE20, OP_REGP, OP_VOID);
3479 tmp = RLW (addr);
3480 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3481 SET_GPR32 (OP[2], tmp);
3482 trace_output_32 (tmp);
3483 }
3484
3485 /* loadd. */
3486 void
3487 OP_12A_14 (void)
3488 {
3489 /* loadd [Rindex]disp20(RPbasexb) REGP
3490 * ADDR = RPbasex + Rindex + zext24(disp20)
3491 * REGP = [ADDR] */
3492
3493 uint32 addr, tmp;
3494 trace_input ("loadd", OP_RP_INDEX_DISP20, OP_REGP, OP_VOID);
3495
3496 if (OP[0] == 0)
3497 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3498 else
3499 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3500
3501 tmp = RLW (addr);
3502 tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff);
3503 SET_GPR32 (OP[3], tmp);
3504 trace_output_32 (tmp);
3505 }
3506
3507
3508 /* storb. */
3509 void
3510 OP_C8_8 (void)
3511 {
3512 /* storb REG, ABS20
3513 * ADDR = zext24(abs20) | remap
3514 * [ADDR] = REGR
3515 * NOTE: remap is
3516 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3517 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3518 * by the core to 16M-64k to 16M. */
3519
3520 uint8 a = ((GPR (OP[0])) & 0xff);
3521 uint32 addr = OP[1];
3522 trace_input ("storb", OP_REG, OP_ABS20_OUTPUT, OP_VOID);
3523 SB (addr, a);
3524 trace_output_32 (addr);
3525 }
3526
3527 /* storb. */
3528 void
3529 OP_137_14 (void)
3530 {
3531 /* storb REG, ABS24
3532 * ADDR = abs24
3533 * [ADDR] = REGR. */
3534
3535 uint8 a = ((GPR (OP[0])) & 0xff);
3536 uint32 addr = OP[1];
3537 trace_input ("storb", OP_REG, OP_ABS24_OUTPUT, OP_VOID);
3538 SB (addr, a);
3539 trace_output_32 (addr);
3540 }
3541
3542 /* storb. */
3543 void
3544 OP_65_7 (void)
3545 {
3546 /* storb REG, [Rindex]ABS20
3547 * ADDR = Rindex + zext24(disp20)
3548 * [ADDR] = REGR */
3549
3550 uint32 addr;
3551 uint8 a = ((GPR (OP[0])) & 0xff);
3552 trace_input ("storb", OP_REG, OP_R_INDEX8_ABS20, OP_VOID);
3553
3554 if (OP[1] == 0)
3555 addr = (GPR32 (12)) + OP[2];
3556 else
3557 addr = (GPR32 (13)) + OP[2];
3558
3559 SB (addr, a);
3560 trace_output_32 (addr);
3561 }
3562
3563 /* storb. */
3564 void
3565 OP_F_4 (void)
3566 {
3567 /* storb REG, DIPS4(REGP)
3568 * ADDR = RPBASE + zext24(DISP4)
3569 * [ADDR] = REG. */
3570
3571 uint16 a = ((GPR (OP[0])) & 0xff);
3572 uint32 addr = (GPR32 (OP[2])) + OP[1];
3573 trace_input ("storb", OP_REG, OP_RP_BASE_DISPE4, OP_VOID);
3574 SB (addr, a);
3575 trace_output_32 (addr);
3576 }
3577
3578 /* storb. */
3579 void
3580 OP_FE_8 (void)
3581 {
3582 /* storb [Rindex]disp0(RPbasex) REG
3583 * ADDR = Rpbasex + Rindex
3584 * [ADDR] = REGR */
3585
3586 uint32 addr;
3587 uint8 a = ((GPR (OP[0])) & 0xff);
3588 trace_input ("storb", OP_REG, OP_RP_INDEX_DISP0, OP_VOID);
3589
3590 if (OP[1] == 0)
3591 addr = (GPR32 (12)) + (GPR32 (OP[3])) + OP[2];
3592 else
3593 addr = (GPR32 (13)) + (GPR32 (OP[3])) + OP[2];
3594
3595 SB (addr, a);
3596 trace_output_32 (addr);
3597 }
3598
3599 /* storb. */
3600 void
3601 OP_319_A (void)
3602 {
3603 /* storb REG, [Rindex]disp14(RPbasex)
3604 * ADDR = Rpbasex + Rindex + zext24(disp14)
3605 * [ADDR] = REGR */
3606
3607 uint8 a = ((GPR (OP[0])) & 0xff);
3608 uint32 addr = (GPR32 (OP[2])) + OP[1];
3609 trace_input ("storb", OP_REG, OP_RP_INDEX_DISP14, OP_VOID);
3610 SB (addr, a);
3611 trace_output_32 (addr);
3612 }
3613
3614 /* storb. */
3615 void
3616 OP_194_14 (void)
3617 {
3618 /* storb REG, DISPE20(REG)
3619 * zext24(Rbase) + zext24(dispe20)
3620 * [ADDR] = REG */
3621
3622 uint8 a = ((GPR (OP[0])) & 0xff);
3623 uint32 addr = OP[1] + (GPR (OP[2]));
3624 trace_input ("storb", OP_REG, OP_R_BASE_DISPE20, OP_VOID);
3625 SB (addr, a);
3626 trace_output_32 (addr);
3627 }
3628
3629 /* storb. */
3630 void
3631 OP_134_14 (void)
3632 {
3633 /* storb REG, DISP20(REG)
3634 * ADDR = zext24(Rbase) + zext24(disp20)
3635 * [ADDR] = REG */
3636
3637 uint8 a = (GPR (OP[0]) & 0xff);
3638 uint32 addr = OP[1] + (GPR (OP[2]));
3639 trace_input ("storb", OP_REG, OP_R_BASE_DISPS20, OP_VOID);
3640 SB (addr, a);
3641 trace_output_32 (addr);
3642 }
3643
3644 /* storb. */
3645 void
3646 OP_FF_8 (void)
3647 {
3648 /* storb REG, disp16(REGP)
3649 * ADDR = RPbase + zext24(disp16)
3650 * [ADDR] = REGP */
3651
3652 uint8 a = ((GPR (OP[0])) & 0xff);
3653 uint32 addr = (GPR32 (OP[2])) + OP[1];
3654 trace_input ("storb", OP_REG, OP_RP_BASE_DISP16, OP_VOID);
3655 SB (addr, a);
3656 trace_output_32 (addr);
3657 }
3658
3659 /* storb. */
3660 void
3661 OP_135_14 (void)
3662 {
3663 /* storb REG, disp20(REGP)
3664 * ADDR = RPbase + zext24(disp20)
3665 * [ADDR] = REGP */
3666
3667 uint8 a = ((GPR (OP[0])) & 0xff);
3668 uint32 addr = (GPR32 (OP[2])) + OP[1];
3669 trace_input ("storb", OP_REG, OP_RP_BASE_DISPS20, OP_VOID);
3670 SB (addr, a);
3671 trace_output_32 (addr);
3672 }
3673
3674 /* storb. */
3675 void
3676 OP_195_14 (void)
3677 {
3678 /* storb REG, -disp20(REGP)
3679 * ADDR = RPbase + zext24(-disp20)
3680 * [ADDR] = REGP */
3681
3682 uint8 a = (GPR (OP[0]) & 0xff);
3683 uint32 addr = (GPR32 (OP[2])) + OP[1];
3684 trace_input ("storb", OP_REG, OP_RP_BASE_DISPE20, OP_VOID);
3685 SB (addr, a);
3686 trace_output_32 (addr);
3687 }
3688
3689 /* storb. */
3690 void
3691 OP_136_14 (void)
3692 {
3693 /* storb REG, [Rindex]disp20(RPbase)
3694 * ADDR = RPbasex + Rindex + zext24(disp20)
3695 * [ADDR] = REGP */
3696
3697 uint8 a = (GPR (OP[0])) & 0xff;
3698 uint32 addr = (GPR32 (OP[2])) + OP[1];
3699 trace_input ("storb", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID);
3700 SB (addr, a);
3701 trace_output_32 (addr);
3702 }
3703
3704 /* STR_IMM instructions. */
3705 /* storb . */
3706 void
3707 OP_81_8 (void)
3708 {
3709 uint8 a = (OP[0]) & 0xff;
3710 uint32 addr = OP[1];
3711 trace_input ("storb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
3712 SB (addr, a);
3713 trace_output_32 (addr);
3714 }
3715
3716 /* storb. */
3717 void
3718 OP_123_14 (void)
3719 {
3720 uint8 a = (OP[0]) & 0xff;
3721 uint32 addr = OP[1];
3722 trace_input ("storb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
3723 SB (addr, a);
3724 trace_output_32 (addr);
3725 }
3726
3727 /* storb. */
3728 void
3729 OP_42_7 (void)
3730 {
3731 uint32 addr;
3732 uint8 a = (OP[0]) & 0xff;
3733 trace_input ("storb", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
3734
3735 if (OP[1] == 0)
3736 addr = (GPR32 (12)) + OP[2];
3737 else
3738 addr = (GPR32 (13)) + OP[2];
3739
3740 SB (addr, a);
3741 trace_output_32 (addr);
3742 }
3743
3744 /* storb. */
3745 void
3746 OP_218_A (void)
3747 {
3748 uint8 a = (OP[0]) & 0xff;
3749 uint32 addr = (GPR32 (OP[2])) + OP[1];
3750 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID);
3751 SB (addr, a);
3752 trace_output_32 (addr);
3753 }
3754
3755 /* storb. */
3756 void
3757 OP_82_8 (void)
3758 {
3759 uint8 a = (OP[0]) & 0xff;
3760 uint32 addr = (GPR32 (OP[2])) + OP[1];
3761 trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
3762 SB (addr, a);
3763 trace_output_32 (addr);
3764 }
3765
3766 /* storb. */
3767 void
3768 OP_120_14 (void)
3769 {
3770 uint8 a = (OP[0]) & 0xff;
3771 uint32 addr = (GPR (OP[2])) + OP[1];
3772 trace_input ("storb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
3773 SB (addr, a);
3774 trace_output_32 (addr);
3775 }
3776
3777 /* storb. */
3778 void
3779 OP_83_8 (void)
3780 {
3781 uint8 a = (OP[0]) & 0xff;
3782 uint32 addr = (GPR32 (OP[2])) + OP[1];
3783 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
3784 SB (addr, a);
3785 trace_output_32 (addr);
3786 }
3787
3788 /* storb. */
3789 void
3790 OP_121_14 (void)
3791 {
3792 uint8 a = (OP[0]) & 0xff;
3793 uint32 addr = (GPR32 (OP[2])) + OP[1];
3794 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
3795 SB (addr, a);
3796 trace_output_32 (addr);
3797 }
3798
3799 /* storb. */
3800 void
3801 OP_122_14 (void)
3802 {
3803 uint8 a = (OP[0]) & 0xff;
3804 uint32 addr = (GPR32 (OP[2])) + OP[1];
3805 trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
3806 SB (addr, a);
3807 trace_output_32 (addr);
3808 }
3809 /* endif for STR_IMM. */
3810
3811 /* storw . */
3812 void
3813 OP_C9_8 (void)
3814 {
3815 uint16 a = GPR (OP[0]);
3816 uint32 addr = OP[1];
3817 trace_input ("storw", OP_REG, OP_ABS20_OUTPUT, OP_VOID);
3818 SW (addr, a);
3819 trace_output_32 (addr);
3820 }
3821
3822 /* storw. */
3823 void
3824 OP_13F_14 (void)
3825 {
3826 uint16 a = GPR (OP[0]);
3827 uint32 addr = OP[1];
3828 trace_input ("storw", OP_REG, OP_ABS24_OUTPUT, OP_VOID);
3829 SW (addr, a);
3830 trace_output_32 (addr);
3831 }
3832
3833 /* storw. */
3834 void
3835 OP_67_7 (void)
3836 {
3837 uint32 addr;
3838 uint16 a = GPR (OP[0]);
3839 trace_input ("storw", OP_REG, OP_R_INDEX8_ABS20, OP_VOID);
3840
3841 if (OP[1] == 0)
3842 addr = (GPR32 (12)) + OP[2];
3843 else
3844 addr = (GPR32 (13)) + OP[2];
3845
3846 SW (addr, a);
3847 trace_output_32 (addr);
3848 }
3849
3850
3851 /* storw. */
3852 void
3853 OP_D_4 (void)
3854 {
3855 uint16 a = (GPR (OP[0]));
3856 uint32 addr = (GPR32 (OP[2])) + OP[1];
3857 trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID);
3858 SW (addr, a);
3859 trace_output_32 (addr);
3860 }
3861
3862 /* storw. */
3863 void
3864 OP_DE_8 (void)
3865 {
3866 uint16 a = GPR (OP[0]);
3867 uint32 addr = (GPR32 (OP[2])) + OP[1];
3868 trace_input ("storw", OP_REG, OP_RP_INDEX_DISP0, OP_VOID);
3869 SW (addr, a);
3870 trace_output_32 (addr);
3871 }
3872
3873 /* storw. */
3874 void
3875 OP_31B_A (void)
3876 {
3877 uint16 a = GPR (OP[0]);
3878 uint32 addr = (GPR32 (OP[2])) + OP[1];
3879 trace_input ("storw", OP_REG, OP_RP_INDEX_DISP14, OP_VOID);
3880 SW (addr, a);
3881 trace_output_32 (addr);
3882 }
3883
3884 /* storw. */
3885 void
3886 OP_19C_14 (void)
3887 {
3888 uint16 a = (GPR (OP[0]));
3889 uint32 addr = (GPR32 (OP[2])) + OP[1];
3890 trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID);
3891 SW (addr, a);
3892 trace_output_32 (addr);
3893 }
3894
3895 /* storw. */
3896 void
3897 OP_13C_14 (void)
3898 {
3899 uint16 a = (GPR (OP[0]));
3900 uint32 addr = (GPR (OP[2])) + OP[1];
3901 trace_input ("storw", OP_REG, OP_R_BASE_DISPS20, OP_VOID);
3902 SW (addr, a);
3903 trace_output_32 (addr);
3904 }
3905
3906 /* storw. */
3907 void
3908 OP_DF_8 (void)
3909 {
3910 uint16 a = (GPR (OP[0]));
3911 uint32 addr = (GPR32 (OP[2])) + OP[1];
3912 trace_input ("storw", OP_REG, OP_RP_BASE_DISP16, OP_VOID);
3913 SW (addr, a);
3914 trace_output_32 (addr);
3915 }
3916
3917 /* storw. */
3918 void
3919 OP_13D_14 (void)
3920 {
3921 uint16 a = (GPR (OP[0]));
3922 uint32 addr = (GPR32 (OP[2])) + OP[1];
3923 trace_input ("storw", OP_REG, OP_RP_BASE_DISPS20, OP_VOID);
3924 SW (addr, a);
3925 trace_output_32 (addr);
3926 }
3927
3928 /* storw. */
3929 void
3930 OP_19D_14 (void)
3931 {
3932 uint16 a = (GPR (OP[0]));
3933 uint32 addr = (GPR32 (OP[2])) + OP[1];
3934 trace_input ("storw", OP_REG, OP_RP_BASE_DISPE20, OP_VOID);
3935 SW (addr, a);
3936 trace_output_32 (addr);
3937 }
3938
3939 /* storw. */
3940 void
3941 OP_13E_14 (void)
3942 {
3943 uint16 a = (GPR (OP[0]));
3944 uint32 addr = (GPR32 (OP[2])) + OP[1];
3945 trace_input ("storw", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID);
3946 SW (addr, a);
3947 trace_output_32 (addr);
3948 }
3949
3950 /* STORE-w IMM instruction *****/
3951 /* storw . */
3952 void
3953 OP_C1_8 (void)
3954 {
3955 uint16 a = OP[0];
3956 uint32 addr = OP[1];
3957 trace_input ("storw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
3958 SW (addr, a);
3959 trace_output_32 (addr);
3960 }
3961
3962 /* storw. */
3963 void
3964 OP_133_14 (void)
3965 {
3966 uint16 a = OP[0];
3967 uint32 addr = OP[1];
3968 trace_input ("storw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
3969 SW (addr, a);
3970 trace_output_32 (addr);
3971 }
3972
3973 /* storw. */
3974 void
3975 OP_62_7 (void)
3976 {
3977 uint32 addr;
3978 uint16 a = OP[0];
3979 trace_input ("storw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
3980
3981 if (OP[1] == 0)
3982 addr = (GPR32 (12)) + OP[2];
3983 else
3984 addr = (GPR32 (13)) + OP[2];
3985
3986 SW (addr, a);
3987 trace_output_32 (addr);
3988 }
3989
3990 /* storw. */
3991 void
3992 OP_318_A (void)
3993 {
3994 uint16 a = OP[0];
3995 uint32 addr = (GPR32 (OP[2])) + OP[1];
3996 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID);
3997 SW (addr, a);
3998 trace_output_32 (addr);
3999 }
4000
4001 /* storw. */
4002 void
4003 OP_C2_8 (void)
4004 {
4005 uint16 a = OP[0];
4006 uint32 addr = (GPR32 (OP[2])) + OP[1];
4007 trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
4008 SW (addr, a);
4009 trace_output_32 (addr);
4010 }
4011
4012 /* storw. */
4013 void
4014 OP_130_14 (void)
4015 {
4016 uint16 a = OP[0];
4017 uint32 addr = (GPR32 (OP[2])) + OP[1];
4018 trace_input ("storw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
4019 SW (addr, a);
4020 trace_output_32 (addr);
4021 }
4022
4023 /* storw. */
4024 void
4025 OP_C3_8 (void)
4026 {
4027 uint16 a = OP[0];
4028 uint32 addr = (GPR32 (OP[2])) + OP[1];
4029 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
4030 SW (addr, a);
4031 trace_output_32 (addr);
4032 }
4033
4034
4035 /* storw. */
4036 void
4037 OP_131_14 (void)
4038 {
4039 uint16 a = OP[0];
4040 uint32 addr = (GPR32 (OP[2])) + OP[1];
4041 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
4042 SW (addr, a);
4043 trace_output_32 (addr);
4044 }
4045
4046 /* storw. */
4047 void
4048 OP_132_14 (void)
4049 {
4050 uint16 a = OP[0];
4051 uint32 addr = (GPR32 (OP[2])) + OP[1];
4052 trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
4053 SW (addr, a);
4054 trace_output_32 (addr);
4055 }
4056
4057
4058 /* stord. */
4059 void
4060 OP_C7_8 (void)
4061 {
4062 uint32 a = GPR32 (OP[0]);
4063 uint32 addr = OP[1];
4064 trace_input ("stord", OP_REGP, OP_ABS20_OUTPUT, OP_VOID);
4065 SLW (addr, a);
4066 trace_output_32 (addr);
4067 }
4068
4069 /* stord. */
4070 void
4071 OP_13B_14 (void)
4072 {
4073 uint32 a = GPR32 (OP[0]);
4074 uint32 addr = OP[1];
4075 trace_input ("stord", OP_REGP, OP_ABS24_OUTPUT, OP_VOID);
4076 SLW (addr, a);
4077 trace_output_32 (addr);
4078 }
4079
4080 /* stord. */
4081 void
4082 OP_66_7 (void)
4083 {
4084 uint32 addr, a = GPR32 (OP[0]);
4085 trace_input ("stord", OP_REGP, OP_R_INDEX8_ABS20, OP_VOID);
4086
4087 if (OP[1] == 0)
4088 addr = (GPR32 (12)) + OP[2];
4089 else
4090 addr = (GPR32 (13)) + OP[2];
4091
4092 SLW (addr, a);
4093 trace_output_32 (addr);
4094 }
4095
4096 /* stord. */
4097 void
4098 OP_E_4 (void)
4099 {
4100 uint32 a = GPR32 (OP[0]);
4101 uint32 addr = (GPR32 (OP[2])) + OP[1];
4102 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID);
4103 SLW (addr, a);
4104 trace_output_32 (addr);
4105 }
4106
4107 /* stord. */
4108 void
4109 OP_EE_8 (void)
4110 {
4111 uint32 a = GPR32 (OP[0]);
4112 uint32 addr = (GPR32 (OP[2])) + OP[1];
4113 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP0, OP_VOID);
4114 SLW (addr, a);
4115 trace_output_32 (addr);
4116 }
4117
4118 /* stord. */
4119 void
4120 OP_31A_A (void)
4121 {
4122 uint32 a = GPR32 (OP[0]);
4123 uint32 addr = (GPR32 (OP[2])) + OP[1];
4124 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP14, OP_VOID);
4125 SLW (addr, a);
4126 trace_output_32 (addr);
4127 }
4128
4129 /* stord. */
4130 void
4131 OP_198_14 (void)
4132 {
4133 uint32 a = GPR32 (OP[0]);
4134 uint32 addr = (GPR32 (OP[2])) + OP[1];
4135 trace_input ("stord", OP_REGP, OP_R_BASE_DISPE20, OP_VOID);
4136 SLW (addr, a);
4137 trace_output_32 (addr);
4138 }
4139
4140 /* stord. */
4141 void
4142 OP_138_14 (void)
4143 {
4144 uint32 a = GPR32 (OP[0]);
4145 uint32 addr = (GPR32 (OP[2])) + OP[1];
4146 trace_input ("stord", OP_REGP, OP_R_BASE_DISPS20, OP_VOID);
4147 SLW (addr, a);
4148 trace_output_32 (addr);
4149 }
4150
4151 /* stord. */
4152 void
4153 OP_EF_8 (void)
4154 {
4155 uint32 a = GPR32 (OP[0]);
4156 uint32 addr = (GPR32 (OP[2])) + OP[1];
4157 trace_input ("stord", OP_REGP, OP_RP_BASE_DISP16, OP_VOID);
4158 SLW (addr, a);
4159 trace_output_32 (addr);
4160 }
4161
4162 /* stord. */
4163 void
4164 OP_139_14 (void)
4165 {
4166 uint32 a = GPR32 (OP[0]);
4167 uint32 addr = (GPR32 (OP[2])) + OP[1];
4168 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPS20, OP_VOID);
4169 SLW (addr, a);
4170 trace_output_32 (addr);
4171 }
4172
4173 /* stord. */
4174 void
4175 OP_199_14 (void)
4176 {
4177 uint32 a = GPR32 (OP[0]);
4178 uint32 addr = (GPR32 (OP[2])) + OP[1];
4179 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID);
4180 SLW (addr, a);
4181 trace_output_32 (addr);
4182 }
4183
4184 /* stord. */
4185 void
4186 OP_13A_14 (void)
4187 {
4188 uint32 a = GPR32 (OP[0]);
4189 uint32 addr = (GPR32 (OP[2])) + OP[1];
4190 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISPS20, OP_VOID);
4191 SLW (addr, a);
4192 trace_output_32 (addr);
4193 }
4194
4195 /* macqu. */
4196 void
4197 OP_14D_14 (void)
4198 {
4199 int32 tmp;
4200 int16 src1, src2;
4201 trace_input ("macuw", OP_REG, OP_REG, OP_REGP);
4202 src1 = GPR (OP[0]);
4203 src2 = GPR (OP[1]);
4204 tmp = src1 * src2;
4205 /*REVISIT FOR SATURATION and Q FORMAT. */
4206 SET_GPR32 (OP[2], tmp);
4207 trace_output_32 (tmp);
4208 }
4209
4210 /* macuw. */
4211 void
4212 OP_14E_14 (void)
4213 {
4214 uint32 tmp;
4215 uint16 src1, src2;
4216 trace_input ("macuw", OP_REG, OP_REG, OP_REGP);
4217 src1 = GPR (OP[0]);
4218 src2 = GPR (OP[1]);
4219 tmp = src1 * src2;
4220 /*REVISIT FOR SATURATION. */
4221 SET_GPR32 (OP[2], tmp);
4222 trace_output_32 (tmp);
4223 }
4224
4225 /* macsw. */
4226 void
4227 OP_14F_14 (void)
4228 {
4229 int32 tmp;
4230 int16 src1, src2;
4231 trace_input ("macsw", OP_REG, OP_REG, OP_REGP);
4232 src1 = GPR (OP[0]);
4233 src2 = GPR (OP[1]);
4234 tmp = src1 * src2;
4235 /*REVISIT FOR SATURATION. */
4236 SET_GPR32 (OP[2], tmp);
4237 trace_output_32 (tmp);
4238 }
4239
4240
4241 /* mulb. */
4242 void
4243 OP_64_8 (void)
4244 {
4245 int16 tmp;
4246 int8 a = (OP[0]) & 0xff;
4247 int8 b = (GPR (OP[1])) & 0xff;
4248 trace_input ("mulb", OP_CONSTANT4_1, OP_REG, OP_VOID);
4249 tmp = (a * b) & 0xff;
4250 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4251 trace_output_16 (tmp);
4252 }
4253
4254 /* mulb. */
4255 void
4256 OP_64B_C (void)
4257 {
4258 int16 tmp;
4259 int8 a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
4260 trace_input ("mulb", OP_CONSTANT4, OP_REG, OP_VOID);
4261 tmp = (a * b) & 0xff;
4262 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4263 trace_output_16 (tmp);
4264 }
4265
4266
4267 /* mulb. */
4268 void
4269 OP_65_8 (void)
4270 {
4271 int16 tmp;
4272 int8 a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
4273 trace_input ("mulb", OP_REG, OP_REG, OP_VOID);
4274 tmp = (a * b) & 0xff;
4275 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4276 trace_output_16 (tmp);
4277 }
4278
4279
4280 /* mulw. */
4281 void
4282 OP_66_8 (void)
4283 {
4284 int32 tmp;
4285 uint16 a = OP[0];
4286 int16 b = (GPR (OP[1]));
4287 trace_input ("mulw", OP_CONSTANT4_1, OP_REG, OP_VOID);
4288 tmp = (a * b) & 0xffff;
4289 SET_GPR (OP[1], tmp);
4290 trace_output_32 (tmp);
4291 }
4292
4293 /* mulw. */
4294 void
4295 OP_66B_C (void)
4296 {
4297 int32 tmp;
4298 int16 a = OP[0], b = (GPR (OP[1]));
4299 trace_input ("mulw", OP_CONSTANT4, OP_REG, OP_VOID);
4300 tmp = (a * b) & 0xffff;
4301 SET_GPR (OP[1], tmp);
4302 trace_output_32 (tmp);
4303 }
4304
4305
4306 /* mulw. */
4307 void
4308 OP_67_8 (void)
4309 {
4310 int32 tmp;
4311 int16 a = (GPR (OP[0])), b = (GPR (OP[1]));
4312 trace_input ("mulw", OP_REG, OP_REG, OP_VOID);
4313 tmp = (a * b) & 0xffff;
4314 SET_GPR (OP[1], tmp);
4315 trace_output_32 (tmp);
4316 }
4317
4318
4319 /* mulsb. */
4320 void
4321 OP_B_8 (void)
4322 {
4323 int16 tmp;
4324 int8 a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
4325 trace_input ("mulsb", OP_REG, OP_REG, OP_VOID);
4326 tmp = a * b;
4327 SET_GPR (OP[1], tmp);
4328 trace_output_32 (tmp);
4329 }
4330
4331 /* mulsw. */
4332 void
4333 OP_62_8 (void)
4334 {
4335 int32 tmp;
4336 int16 a = (GPR (OP[0])), b = (GPR (OP[1]));
4337 trace_input ("mulsw", OP_REG, OP_REGP, OP_VOID);
4338 tmp = a * b;
4339 SET_GPR32 (OP[1], tmp);
4340 trace_output_32 (tmp);
4341 }
4342
4343 /* muluw. */
4344 void
4345 OP_63_8 (void)
4346 {
4347 uint32 tmp;
4348 uint16 a = (GPR (OP[0])), b = (GPR (OP[1]));
4349 trace_input ("muluw", OP_REG, OP_REGP, OP_VOID);
4350 tmp = a * b;
4351 SET_GPR32 (OP[1], tmp);
4352 trace_output_32 (tmp);
4353 }
4354
4355
4356 /* nop. */
4357 void
4358 OP_2C00_10 (void)
4359 {
4360 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
4361
4362 #if 0
4363 State.exception = SIGTRAP;
4364 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
4365 switch (State.ins_type)
4366 {
4367 default:
4368 ins_type_counters[ (int)INS_UNKNOWN ]++;
4369 break;
4370
4371 }
4372
4373 #endif
4374 trace_output_void ();
4375 }
4376
4377
4378 /* orb. */
4379 void
4380 OP_24_8 (void)
4381 {
4382 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
4383 trace_input ("orb", OP_CONSTANT4, OP_REG, OP_VOID);
4384 tmp = a | b;
4385 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
4386 trace_output_16 (tmp);
4387 }
4388
4389 /* orb. */
4390 void
4391 OP_24B_C (void)
4392 {
4393 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
4394 trace_input ("orb", OP_CONSTANT16, OP_REG, OP_VOID);
4395 tmp = a | b;
4396 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
4397 trace_output_16 (tmp);
4398 }
4399
4400 /* orb. */
4401 void
4402 OP_25_8 (void)
4403 {
4404 uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
4405 trace_input ("orb", OP_REG, OP_REG, OP_VOID);
4406 tmp = a | b;
4407 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
4408 trace_output_16 (tmp);
4409 }
4410
4411 /* orw. */
4412 void
4413 OP_26_8 (void)
4414 {
4415 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
4416 trace_input ("orw", OP_CONSTANT4, OP_REG, OP_VOID);
4417 tmp = a | b;
4418 SET_GPR (OP[1], tmp);
4419 trace_output_16 (tmp);
4420 }
4421
4422
4423 /* orw. */
4424 void
4425 OP_26B_C (void)
4426 {
4427 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
4428 trace_input ("orw", OP_CONSTANT16, OP_REG, OP_VOID);
4429 tmp = a | b;
4430 SET_GPR (OP[1], tmp);
4431 trace_output_16 (tmp);
4432 }
4433
4434 /* orw. */
4435 void
4436 OP_27_8 (void)
4437 {
4438 uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
4439 trace_input ("orw", OP_REG, OP_REG, OP_VOID);
4440 tmp = a | b;
4441 SET_GPR (OP[1], tmp);
4442 trace_output_16 (tmp);
4443 }
4444
4445
4446 /* lshb. */
4447 void
4448 OP_13_9 (void)
4449 {
4450 uint16 a = OP[0];
4451 uint16 tmp, b = (GPR (OP[1])) & 0xFF;
4452 trace_input ("lshb", OP_CONSTANT4, OP_REG, OP_VOID);
4453 /* A positive count specifies a shift to the left;
4454 * A negative count specifies a shift to the right. */
4455 if (sign_flag)
4456 tmp = b >> a;
4457 else
4458 tmp = b << a;
4459
4460 sign_flag = 0; /* Reset sign_flag. */
4461
4462 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4463 trace_output_16 (tmp);
4464 }
4465
4466 /* lshb. */
4467 void
4468 OP_44_8 (void)
4469 {
4470 uint16 a = (GPR (OP[0])) & 0xff;
4471 uint16 tmp, b = (GPR (OP[1])) & 0xFF;
4472 trace_input ("lshb", OP_REG, OP_REG, OP_VOID);
4473 if (a & ((long)1 << 3))
4474 {
4475 sign_flag = 1;
4476 a = ~(a) + 1;
4477 }
4478 a = (unsigned int) (a & 0x7);
4479
4480 /* A positive count specifies a shift to the left;
4481 * A negative count specifies a shift to the right. */
4482 if (sign_flag)
4483 tmp = b >> a;
4484 else
4485 tmp = b << a;
4486
4487 sign_flag = 0; /* Reset sign_flag. */
4488 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4489 trace_output_16 (tmp);
4490 }
4491
4492 /* lshw. */
4493 void
4494 OP_46_8 (void)
4495 {
4496 uint16 tmp, b = GPR (OP[1]);
4497 int16 a = GPR (OP[0]);
4498 trace_input ("lshw", OP_REG, OP_REG, OP_VOID);
4499 if (a & ((long)1 << 4))
4500 {
4501 sign_flag = 1;
4502 a = ~(a) + 1;
4503 }
4504 a = (unsigned int) (a & 0xf);
4505
4506 /* A positive count specifies a shift to the left;
4507 * A negative count specifies a shift to the right. */
4508 if (sign_flag)
4509 tmp = b >> a;
4510 else
4511 tmp = b << a;
4512
4513 sign_flag = 0; /* Reset sign_flag. */
4514 SET_GPR (OP[1], (tmp & 0xffff));
4515 trace_output_16 (tmp);
4516 }
4517
4518 /* lshw. */
4519 void
4520 OP_49_8 (void)
4521 {
4522 uint16 tmp, b = GPR (OP[1]);
4523 uint16 a = OP[0];
4524 trace_input ("lshw", OP_CONSTANT5, OP_REG, OP_VOID);
4525 /* A positive count specifies a shift to the left;
4526 * A negative count specifies a shift to the right. */
4527 if (sign_flag)
4528 tmp = b >> a;
4529 else
4530 tmp = b << a;
4531
4532 sign_flag = 0; /* Reset sign_flag. */
4533 SET_GPR (OP[1], (tmp & 0xffff));
4534 trace_output_16 (tmp);
4535 }
4536
4537 /* lshd. */
4538 void
4539 OP_25_7 (void)
4540 {
4541 uint32 tmp, b = GPR32 (OP[1]);
4542 uint16 a = OP[0];
4543 trace_input ("lshd", OP_CONSTANT6, OP_REGP, OP_VOID);
4544 /* A positive count specifies a shift to the left;
4545 * A negative count specifies a shift to the right. */
4546 if (sign_flag)
4547 tmp = b >> a;
4548 else
4549 tmp = b << a;
4550
4551 sign_flag = 0; /* Reset sign flag. */
4552
4553 SET_GPR32 (OP[1], tmp);
4554 trace_output_32 (tmp);
4555 }
4556
4557 /* lshd. */
4558 void
4559 OP_47_8 (void)
4560 {
4561 uint32 tmp, b = GPR32 (OP[1]);
4562 uint16 a = GPR (OP[0]);
4563 trace_input ("lshd", OP_REG, OP_REGP, OP_VOID);
4564 if (a & ((long)1 << 5))
4565 {
4566 sign_flag = 1;
4567 a = ~(a) + 1;
4568 }
4569 a = (unsigned int) (a & 0x1f);
4570 /* A positive count specifies a shift to the left;
4571 * A negative count specifies a shift to the right. */
4572 if (sign_flag)
4573 tmp = b >> a;
4574 else
4575 tmp = b << a;
4576
4577 sign_flag = 0; /* Reset sign flag. */
4578
4579 SET_GPR32 (OP[1], tmp);
4580 trace_output_32 (tmp);
4581 }
4582
4583 /* ashub. */
4584 void
4585 OP_80_9 (void)
4586 {
4587 uint16 a = OP[0];
4588 int8 tmp, b = (GPR (OP[1])) & 0xFF;
4589 trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID);
4590 /* A positive count specifies a shift to the left;
4591 * A negative count specifies a shift to the right. */
4592 if (sign_flag)
4593 tmp = b >> a;
4594 else
4595 tmp = b << a;
4596
4597 sign_flag = 0; /* Reset sign flag. */
4598
4599 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xff00)));
4600 trace_output_16 (tmp);
4601 }
4602
4603 /* ashub. */
4604 void
4605 OP_81_9 (void)
4606 {
4607 uint16 a = OP[0];
4608 int8 tmp, b = (GPR (OP[1])) & 0xFF;
4609 trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID);
4610 /* A positive count specifies a shift to the left;
4611 * A negative count specifies a shift to the right. */
4612 if (sign_flag)
4613 tmp = b >> a;
4614 else
4615 tmp = b << a;
4616
4617 sign_flag = 0; /* Reset sign flag. */
4618
4619 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4620 trace_output_16 (tmp);
4621 }
4622
4623
4624 /* ashub. */
4625 void
4626 OP_41_8 (void)
4627 {
4628 int16 a = (GPR (OP[0]));
4629 int8 tmp, b = (GPR (OP[1])) & 0xFF;
4630 trace_input ("ashub", OP_REG, OP_REG, OP_VOID);
4631
4632 if (a & ((long)1 << 3))
4633 {
4634 sign_flag = 1;
4635 a = ~(a) + 1;
4636 }
4637 a = (unsigned int) (a & 0x7);
4638
4639 /* A positive count specifies a shift to the left;
4640 * A negative count specifies a shift to the right. */
4641 if (sign_flag)
4642 tmp = b >> a;
4643 else
4644 tmp = b << a;
4645
4646 sign_flag = 0; /* Reset sign flag. */
4647
4648 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4649 trace_output_16 (tmp);
4650 }
4651
4652
4653 /* ashuw. */
4654 void
4655 OP_42_8 (void)
4656 {
4657 int16 tmp, b = GPR (OP[1]);
4658 uint16 a = OP[0];
4659 trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID);
4660 /* A positive count specifies a shift to the left;
4661 * A negative count specifies a shift to the right. */
4662 if (sign_flag)
4663 tmp = b >> a;
4664 else
4665 tmp = b << a;
4666
4667 sign_flag = 0; /* Reset sign flag. */
4668
4669 SET_GPR (OP[1], (tmp & 0xffff));
4670 trace_output_16 (tmp);
4671 }
4672
4673 /* ashuw. */
4674 void
4675 OP_43_8 (void)
4676 {
4677 int16 tmp, b = GPR (OP[1]);
4678 uint16 a = OP[0];
4679 trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID);
4680 /* A positive count specifies a shift to the left;
4681 * A negative count specifies a shift to the right. */
4682 if (sign_flag)
4683 tmp = b >> a;
4684 else
4685 tmp = b << a;
4686
4687 sign_flag = 0; /* Reset sign flag. */
4688 SET_GPR (OP[1], (tmp & 0xffff));
4689 trace_output_16 (tmp);
4690 }
4691
4692 /* ashuw. */
4693 void
4694 OP_45_8 (void)
4695 {
4696 int16 tmp;
4697 int16 a = GPR (OP[0]), b = GPR (OP[1]);
4698 trace_input ("ashuw", OP_REG, OP_REG, OP_VOID);
4699
4700 if (a & ((long)1 << 4))
4701 {
4702 sign_flag = 1;
4703 a = ~(a) + 1;
4704 }
4705 a = (unsigned int) (a & 0xf);
4706 /* A positive count specifies a shift to the left;
4707 * A negative count specifies a shift to the right. */
4708
4709 if (sign_flag)
4710 tmp = b >> a;
4711 else
4712 tmp = b << a;
4713
4714 sign_flag = 0; /* Reset sign flag. */
4715 SET_GPR (OP[1], (tmp & 0xffff));
4716 trace_output_16 (tmp);
4717 }
4718
4719 /* ashud. */
4720 void
4721 OP_26_7 (void)
4722 {
4723 int32 tmp,b = GPR32 (OP[1]);
4724 uint32 a = OP[0];
4725 trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID);
4726 /* A positive count specifies a shift to the left;
4727 * A negative count specifies a shift to the right. */
4728 if (sign_flag)
4729 tmp = b >> a;
4730 else
4731 tmp = b << a;
4732
4733 sign_flag = 0; /* Reset sign flag. */
4734 SET_GPR32 (OP[1], tmp);
4735 trace_output_32 (tmp);
4736 }
4737
4738 /* ashud. */
4739 void
4740 OP_27_7 (void)
4741 {
4742 int32 tmp;
4743 int32 a = OP[0], b = GPR32 (OP[1]);
4744 trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID);
4745 /* A positive count specifies a shift to the left;
4746 * A negative count specifies a shift to the right. */
4747 if (sign_flag)
4748 tmp = b >> a;
4749 else
4750 tmp = b << a;
4751
4752 sign_flag = 0; /* Reset sign flag. */
4753 SET_GPR32 (OP[1], tmp);
4754 trace_output_32 (tmp);
4755 }
4756
4757 /* ashud. */
4758 void
4759 OP_48_8 (void)
4760 {
4761 int32 tmp;
4762 int32 a = GPR32 (OP[0]), b = GPR32 (OP[1]);
4763 trace_input ("ashud", OP_REGP, OP_REGP, OP_VOID);
4764
4765 if (a & ((long)1 << 5))
4766 {
4767 sign_flag = 1;
4768 a = ~(a) + 1;
4769 }
4770 a = (unsigned int) (a & 0x1f);
4771 /* A positive count specifies a shift to the left;
4772 * A negative count specifies a shift to the right. */
4773 if (sign_flag)
4774 tmp = b >> a;
4775 else
4776 tmp = b << a;
4777
4778 sign_flag = 0; /* Reset sign flag. */
4779 SET_GPR32 (OP[1], tmp);
4780 trace_output_32 (tmp);
4781 }
4782
4783
4784 /* storm. */
4785 void
4786 OP_16_D (void)
4787 {
4788 uint32 addr = GPR (1);
4789 uint16 count = OP[0], reg = 2;
4790 trace_input ("storm", OP_CONSTANT4, OP_VOID, OP_VOID);
4791 if ((addr & 1))
4792 {
4793 State.exception = SIG_CR16_BUS;
4794 State.pc_changed = 1; /* Don't increment the PC. */
4795 trace_output_void ();
4796 return;
4797 }
4798
4799 while (count)
4800 {
4801 SW (addr, (GPR (reg)));
4802 addr +=2;
4803 --count;
4804 reg++;
4805 if (reg == 6) reg = 8;
4806 };
4807
4808 SET_GPR (1, addr);
4809
4810 trace_output_void ();
4811 }
4812
4813
4814 /* stormp. */
4815 void
4816 OP_17_D (void)
4817 {
4818 uint32 addr = GPR32 (6);
4819 uint16 count = OP[0], reg = 2;
4820 trace_input ("stormp", OP_CONSTANT4, OP_VOID, OP_VOID);
4821 if ((addr & 1))
4822 {
4823 State.exception = SIG_CR16_BUS;
4824 State.pc_changed = 1; /* Don't increment the PC. */
4825 trace_output_void ();
4826 return;
4827 }
4828
4829 while (count)
4830 {
4831 SW (addr, (GPR (reg)));
4832 addr +=2;
4833 --count;
4834 reg++;
4835 if (reg == 6) reg = 8;
4836 };
4837
4838 SET_GPR32 (6, addr);
4839 trace_output_void ();
4840 }
4841
4842 /* subb. */
4843 void
4844 OP_38_8 (void)
4845 {
4846 uint8 a = OP[0];
4847 uint8 b = (GPR (OP[1])) & 0xff;
4848 uint16 tmp = (~a + 1 + b) & 0xff;
4849 trace_input ("subb", OP_CONSTANT4, OP_REG, OP_VOID);
4850 /* see ../common/sim-alu.h for a more extensive discussion on how to
4851 compute the carry/overflow bits. */
4852 SET_PSR_C (tmp > 0xff);
4853 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4854 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4855 trace_output_16 (tmp);
4856 }
4857
4858 /* subb. */
4859 void
4860 OP_38B_C (void)
4861 {
4862 uint8 a = OP[0] & 0xFF;
4863 uint8 b = (GPR (OP[1])) & 0xFF;
4864 uint16 tmp = (~a + 1 + b) & 0xFF;
4865 trace_input ("subb", OP_CONSTANT16, OP_REG, OP_VOID);
4866 /* see ../common/sim-alu.h for a more extensive discussion on how to
4867 compute the carry/overflow bits. */
4868 SET_PSR_C (tmp > 0xff);
4869 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4870 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4871 trace_output_16 (tmp);
4872 }
4873
4874 /* subb. */
4875 void
4876 OP_39_8 (void)
4877 {
4878 uint8 a = (GPR (OP[0])) & 0xFF;
4879 uint8 b = (GPR (OP[1])) & 0xFF;
4880 uint16 tmp = (~a + 1 + b) & 0xff;
4881 trace_input ("subb", OP_REG, OP_REG, OP_VOID);
4882 /* see ../common/sim-alu.h for a more extensive discussion on how to
4883 compute the carry/overflow bits. */
4884 SET_PSR_C (tmp > 0xff);
4885 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4886 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4887 trace_output_16 (tmp);
4888 }
4889
4890 /* subw. */
4891 void
4892 OP_3A_8 (void)
4893 {
4894 uint16 a = OP[0];
4895 uint16 b = GPR (OP[1]);
4896 uint16 tmp = (~a + 1 + b);
4897 trace_input ("subw", OP_CONSTANT4, OP_REG, OP_VOID);
4898 /* see ../common/sim-alu.h for a more extensive discussion on how to
4899 compute the carry/overflow bits. */
4900 SET_PSR_C (tmp > 0xffff);
4901 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4902 SET_GPR (OP[1], tmp);
4903 trace_output_16 (tmp);
4904 }
4905
4906 /* subw. */
4907 void
4908 OP_3AB_C (void)
4909 {
4910 uint16 a = OP[0];
4911 uint16 b = GPR (OP[1]);
4912 uint32 tmp = (~a + 1 + b);
4913 trace_input ("subw", OP_CONSTANT16, OP_REG, OP_VOID);
4914 /* see ../common/sim-alu.h for a more extensive discussion on how to
4915 compute the carry/overflow bits. */
4916 SET_PSR_C (tmp > 0xffff);
4917 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4918 SET_GPR (OP[1], tmp & 0xffff);
4919 trace_output_16 (tmp);
4920 }
4921
4922 /* subw. */
4923 void
4924 OP_3B_8 (void)
4925 {
4926 uint16 a = GPR (OP[0]);
4927 uint16 b = GPR (OP[1]);
4928 uint32 tmp = (~a + 1 + b);
4929 trace_input ("subw", OP_REG, OP_REG, OP_VOID);
4930 /* see ../common/sim-alu.h for a more extensive discussion on how to
4931 compute the carry/overflow bits. */
4932 SET_PSR_C (tmp > 0xffff);
4933 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4934 SET_GPR (OP[1], tmp & 0xffff);
4935 trace_output_16 (tmp);
4936 }
4937
4938 /* subcb. */
4939 void
4940 OP_3C_8 (void)
4941 {
4942 uint8 a = OP[0];
4943 uint8 b = (GPR (OP[1])) & 0xff;
4944 //uint16 tmp1 = a + 1;
4945 uint16 tmp1 = a + (PSR_C);
4946 uint16 tmp = (~tmp1 + 1 + b);
4947 trace_input ("subcb", OP_CONSTANT4, OP_REG, OP_VOID);
4948 /* see ../common/sim-alu.h for a more extensive discussion on how to
4949 compute the carry/overflow bits. */
4950 SET_PSR_C (tmp > 0xff);
4951 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4952 SET_GPR (OP[1], tmp);
4953 trace_output_16 (tmp);
4954 }
4955
4956 /* subcb. */
4957 void
4958 OP_3CB_C (void)
4959 {
4960 uint16 a = OP[0];
4961 uint16 b = (GPR (OP[1])) & 0xff;
4962 //uint16 tmp1 = a + 1;
4963 uint16 tmp1 = a + (PSR_C);
4964 uint16 tmp = (~tmp1 + 1 + b);
4965 trace_input ("subcb", OP_CONSTANT16, OP_REG, OP_VOID);
4966 /* see ../common/sim-alu.h for a more extensive discussion on how to
4967 compute the carry/overflow bits. */
4968 SET_PSR_C (tmp > 0xff);
4969 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4970 SET_GPR (OP[1], tmp);
4971 trace_output_16 (tmp);
4972 }
4973
4974 /* subcb. */
4975 void
4976 OP_3D_8 (void)
4977 {
4978 uint16 a = (GPR (OP[0])) & 0xff;
4979 uint16 b = (GPR (OP[1])) & 0xff;
4980 uint16 tmp1 = a + (PSR_C);
4981 uint16 tmp = (~tmp1 + 1 + b);
4982 trace_input ("subcb", OP_REG, OP_REG, OP_VOID);
4983 /* see ../common/sim-alu.h for a more extensive discussion on how to
4984 compute the carry/overflow bits. */
4985 SET_PSR_C (tmp > 0xff);
4986 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4987 SET_GPR (OP[1], tmp);
4988 trace_output_16 (tmp);
4989 }
4990
4991 /* subcw. */
4992 void
4993 OP_3E_8 (void)
4994 {
4995 uint16 a = OP[0], b = (GPR (OP[1]));
4996 uint16 tmp1 = a + (PSR_C);
4997 uint16 tmp = (~tmp1 + 1 + b);
4998 trace_input ("subcw", OP_CONSTANT4, OP_REG, OP_VOID);
4999 /* see ../common/sim-alu.h for a more extensive discussion on how to
5000 compute the carry/overflow bits. */
5001 SET_PSR_C (tmp > 0xffff);
5002 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
5003 SET_GPR (OP[1], tmp);
5004 trace_output_16 (tmp);
5005 }
5006
5007 /* subcw. */
5008 void
5009 OP_3EB_C (void)
5010 {
5011 int16 a = OP[0];
5012 uint16 b = GPR (OP[1]);
5013 uint16 tmp1 = a + (PSR_C);
5014 uint16 tmp = (~tmp1 + 1 + b);
5015 trace_input ("subcw", OP_CONSTANT16, OP_REG, OP_VOID);
5016 /* see ../common/sim-alu.h for a more extensive discussion on how to
5017 compute the carry/overflow bits. */
5018 SET_PSR_C (tmp > 0xffff);
5019 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
5020 SET_GPR (OP[1], tmp);
5021 trace_output_16 (tmp);
5022 }
5023
5024 /* subcw. */
5025 void
5026 OP_3F_8 (void)
5027 {
5028 uint16 a = (GPR (OP[0])), b = (GPR (OP[1]));
5029 uint16 tmp1 = a + (PSR_C);
5030 uint16 tmp = (~tmp1 + 1 + b);
5031 trace_input ("subcw", OP_REG, OP_REG, OP_VOID);
5032 /* see ../common/sim-alu.h for a more extensive discussion on how to
5033 compute the carry/overflow bits. */
5034 SET_PSR_C (tmp > 0xffff);
5035 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
5036 SET_GPR (OP[1], tmp);
5037 trace_output_16 (tmp);
5038 }
5039
5040 /* subd. */
5041 void
5042 OP_3_C (void)
5043 {
5044 int32 a = OP[0];
5045 uint32 b = GPR32 (OP[1]);
5046 uint32 tmp = (~a + 1 + b);
5047 trace_input ("subd", OP_CONSTANT32, OP_REGP, OP_VOID);
5048 /* see ../common/sim-alu.h for a more extensive discussion on how to
5049 compute the carry/overflow bits. */
5050 SET_PSR_C (tmp > 0xffffffff);
5051 SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) &&
5052 ((b & 0x80000000) != (tmp & 0x80000000)));
5053 SET_GPR32 (OP[1], tmp);
5054 trace_output_32 (tmp);
5055 }
5056
5057 /* subd. */
5058 void
5059 OP_14C_14 (void)
5060 {
5061 uint32 a = GPR32 (OP[0]);
5062 uint32 b = GPR32 (OP[1]);
5063 uint32 tmp = (~a + 1 + b);
5064 trace_input ("subd", OP_REGP, OP_REGP, OP_VOID);
5065 /* see ../common/sim-alu.h for a more extensive discussion on how to
5066 compute the carry/overflow bits. */
5067 SET_PSR_C (tmp > 0xffffffff);
5068 SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) &&
5069 ((b & 0x80000000) != (tmp & 0x80000000)));
5070 SET_GPR32 (OP[1], tmp);
5071 trace_output_32 (tmp);
5072 }
5073
5074 /* excp. */
5075 void
5076 OP_C_C (void)
5077 {
5078 uint32 tmp;
5079 uint16 a;
5080 trace_input ("excp", OP_CONSTANT4, OP_VOID, OP_VOID);
5081 switch (OP[0])
5082 {
5083 default:
5084 #if (DEBUG & DEBUG_TRAP) == 0
5085 {
5086 #if 0
5087 uint16 vec = OP[0] + TRAP_VECTOR_START;
5088 SET_BPC (PC + 1);
5089 SET_BPSR (PSR);
5090 SET_PSR (PSR & PSR_SM_BIT);
5091 JMP (vec);
5092 break;
5093 #endif
5094 }
5095 #else /* if debugging use trap to print registers */
5096 {
5097 int i;
5098 static int first_time = 1;
5099
5100 if (first_time)
5101 {
5102 first_time = 0;
5103 (*cr16_callback->printf_filtered) (cr16_callback, "Trap # PC ");
5104 for (i = 0; i < 16; i++)
5105 (*cr16_callback->printf_filtered) (cr16_callback, " %sr%d", (i > 9) ? "" : " ", i);
5106 (*cr16_callback->printf_filtered) (cr16_callback, " a0 a1 f0 f1 c\n");
5107 }
5108
5109 (*cr16_callback->printf_filtered) (cr16_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
5110
5111 for (i = 0; i < 16; i++)
5112 (*cr16_callback->printf_filtered) (cr16_callback, " %.4x", (int) GPR (i));
5113
5114 for (i = 0; i < 2; i++)
5115 (*cr16_callback->printf_filtered) (cr16_callback, " %.2x%.8lx",
5116 ((int)(ACC (i) >> 32) & 0xff),
5117 ((unsigned long) ACC (i)) & 0xffffffff);
5118
5119 (*cr16_callback->printf_filtered) (cr16_callback, " %d %d %d\n",
5120 PSR_F != 0, PSR_F != 0, PSR_C != 0);
5121 (*cr16_callback->flush_stdout) (cr16_callback);
5122 break;
5123 }
5124 #endif
5125 case 8: /* new system call trap */
5126 /* Trap 8 is used for simulating low-level I/O */
5127 {
5128 unsigned32 result = 0;
5129 errno = 0;
5130
5131 /* Registers passed to trap 0. */
5132
5133 #define FUNC GPR (0) /* function number. */
5134 #define PARM1 GPR (2) /* optional parm 1. */
5135 #define PARM2 GPR (3) /* optional parm 2. */
5136 #define PARM3 GPR (4) /* optional parm 3. */
5137 #define PARM4 GPR (5) /* optional parm 4. */
5138
5139 /* Registers set by trap 0 */
5140
5141 #define RETVAL(X) do { result = (0xffff & (X));SET_GPR (0, result);} while (0)
5142 #define RETVAL32(X) do { result = (X); SET_GPR32 (0, result);} while (0)
5143 #define RETERR(X) SET_GPR (4, (X)) /* return error code. */
5144
5145 /* Turn a pointer in a register into a pointer into real memory. */
5146
5147 #define MEMPTR(x) ((char *)(dmem_addr(x)))
5148
5149 switch (FUNC)
5150 {
5151 #if !defined(__GO32__) && !defined(_WIN32)
5152 #ifdef TARGET_SYS_fork
5153 case TARGET_SYS_fork:
5154 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
5155 RETVAL (fork ());
5156 trace_output_16 (result);
5157 break;
5158 #endif
5159
5160 #define getpid() 47
5161 case TARGET_SYS_getpid:
5162 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
5163 RETVAL (getpid ());
5164 trace_output_16 (result);
5165 break;
5166
5167 case TARGET_SYS_kill:
5168 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
5169 if (PARM1 == getpid ())
5170 {
5171 trace_output_void ();
5172 State.exception = PARM2;
5173 }
5174 else
5175 {
5176 int os_sig = -1;
5177 switch (PARM2)
5178 {
5179 #ifdef SIGHUP
5180 case 1: os_sig = SIGHUP; break;
5181 #endif
5182 #ifdef SIGINT
5183 case 2: os_sig = SIGINT; break;
5184 #endif
5185 #ifdef SIGQUIT
5186 case 3: os_sig = SIGQUIT; break;
5187 #endif
5188 #ifdef SIGILL
5189 case 4: os_sig = SIGILL; break;
5190 #endif
5191 #ifdef SIGTRAP
5192 case 5: os_sig = SIGTRAP; break;
5193 #endif
5194 #ifdef SIGABRT
5195 case 6: os_sig = SIGABRT; break;
5196 #elif defined(SIGIOT)
5197 case 6: os_sig = SIGIOT; break;
5198 #endif
5199 #ifdef SIGEMT
5200 case 7: os_sig = SIGEMT; break;
5201 #endif
5202 #ifdef SIGFPE
5203 case 8: os_sig = SIGFPE; break;
5204 #endif
5205 #ifdef SIGKILL
5206 case 9: os_sig = SIGKILL; break;
5207 #endif
5208 #ifdef SIGBUS
5209 case 10: os_sig = SIGBUS; break;
5210 #endif
5211 #ifdef SIGSEGV
5212 case 11: os_sig = SIGSEGV; break;
5213 #endif
5214 #ifdef SIGSYS
5215 case 12: os_sig = SIGSYS; break;
5216 #endif
5217 #ifdef SIGPIPE
5218 case 13: os_sig = SIGPIPE; break;
5219 #endif
5220 #ifdef SIGALRM
5221 case 14: os_sig = SIGALRM; break;
5222 #endif
5223 #ifdef SIGTERM
5224 case 15: os_sig = SIGTERM; break;
5225 #endif
5226 #ifdef SIGURG
5227 case 16: os_sig = SIGURG; break;
5228 #endif
5229 #ifdef SIGSTOP
5230 case 17: os_sig = SIGSTOP; break;
5231 #endif
5232 #ifdef SIGTSTP
5233 case 18: os_sig = SIGTSTP; break;
5234 #endif
5235 #ifdef SIGCONT
5236 case 19: os_sig = SIGCONT; break;
5237 #endif
5238 #ifdef SIGCHLD
5239 case 20: os_sig = SIGCHLD; break;
5240 #elif defined(SIGCLD)
5241 case 20: os_sig = SIGCLD; break;
5242 #endif
5243 #ifdef SIGTTIN
5244 case 21: os_sig = SIGTTIN; break;
5245 #endif
5246 #ifdef SIGTTOU
5247 case 22: os_sig = SIGTTOU; break;
5248 #endif
5249 #ifdef SIGIO
5250 case 23: os_sig = SIGIO; break;
5251 #elif defined (SIGPOLL)
5252 case 23: os_sig = SIGPOLL; break;
5253 #endif
5254 #ifdef SIGXCPU
5255 case 24: os_sig = SIGXCPU; break;
5256 #endif
5257 #ifdef SIGXFSZ
5258 case 25: os_sig = SIGXFSZ; break;
5259 #endif
5260 #ifdef SIGVTALRM
5261 case 26: os_sig = SIGVTALRM; break;
5262 #endif
5263 #ifdef SIGPROF
5264 case 27: os_sig = SIGPROF; break;
5265 #endif
5266 #ifdef SIGWINCH
5267 case 28: os_sig = SIGWINCH; break;
5268 #endif
5269 #ifdef SIGLOST
5270 case 29: os_sig = SIGLOST; break;
5271 #endif
5272 #ifdef SIGUSR1
5273 case 30: os_sig = SIGUSR1; break;
5274 #endif
5275 #ifdef SIGUSR2
5276 case 31: os_sig = SIGUSR2; break;
5277 #endif
5278 }
5279
5280 if (os_sig == -1)
5281 {
5282 trace_output_void ();
5283 (*cr16_callback->printf_filtered) (cr16_callback, "Unknown signal %d\n", PARM2);
5284 (*cr16_callback->flush_stdout) (cr16_callback);
5285 State.exception = SIGILL;
5286 }
5287 else
5288 {
5289 RETVAL (kill (PARM1, PARM2));
5290 trace_output_16 (result);
5291 }
5292 }
5293 break;
5294
5295 #ifdef TARGET_SYS_execve
5296 case TARGET_SYS_execve:
5297 trace_input ("<execve>", OP_VOID, OP_VOID, OP_VOID);
5298 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2<<16|PARM3),
5299 (char **)MEMPTR (PARM4)));
5300 trace_output_16 (result);
5301 break;
5302 #endif
5303
5304 #ifdef TARGET_SYS_execv
5305 case TARGET_SYS_execv:
5306 trace_input ("<execv>", OP_VOID, OP_VOID, OP_VOID);
5307 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
5308 trace_output_16 (result);
5309 break;
5310 #endif
5311
5312 #ifdef TARGET_SYS_pipe
5313 case TARGET_SYS_pipe:
5314 {
5315 reg_t buf;
5316 int host_fd[2];
5317
5318 trace_input ("<pipe>", OP_VOID, OP_VOID, OP_VOID);
5319 buf = PARM1;
5320 RETVAL (pipe (host_fd));
5321 SW (buf, host_fd[0]);
5322 buf += sizeof(uint16);
5323 SW (buf, host_fd[1]);
5324 trace_output_16 (result);
5325 }
5326 break;
5327 #endif
5328
5329 #ifdef TARGET_SYS_wait
5330 case TARGET_SYS_wait:
5331 {
5332 int status;
5333 trace_input ("<wait>", OP_REG, OP_VOID, OP_VOID);
5334 RETVAL (wait (&status));
5335 if (PARM1)
5336 SW (PARM1, status);
5337 trace_output_16 (result);
5338 }
5339 break;
5340 #endif
5341 #else
5342 case TARGET_SYS_getpid:
5343 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
5344 RETVAL (1);
5345 trace_output_16 (result);
5346 break;
5347
5348 case TARGET_SYS_kill:
5349 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
5350 trace_output_void ();
5351 State.exception = PARM2;
5352 break;
5353 #endif
5354
5355 case TARGET_SYS_read:
5356 trace_input ("<read>", OP_REG, OP_MEMREF, OP_REG);
5357 RETVAL (cr16_callback->read (cr16_callback, PARM1,
5358 MEMPTR (((unsigned long)PARM3 << 16)
5359 |((unsigned long)PARM2)), PARM4));
5360 trace_output_16 (result);
5361 break;
5362
5363 case TARGET_SYS_write:
5364 trace_input ("<write>", OP_REG, OP_MEMREF, OP_REG);
5365 RETVAL ((int)cr16_callback->write (cr16_callback, PARM1,
5366 MEMPTR (((unsigned long)PARM3 << 16) | PARM2), PARM4));
5367 trace_output_16 (result);
5368 break;
5369
5370 case TARGET_SYS_lseek:
5371 trace_input ("<lseek>", OP_REG, OP_REGP, OP_REG);
5372 RETVAL32 (cr16_callback->lseek (cr16_callback, PARM1,
5373 ((((long) PARM3) << 16) | PARM2),
5374 PARM4));
5375 trace_output_32 (result);
5376 break;
5377
5378 case TARGET_SYS_close:
5379 trace_input ("<close>", OP_REG, OP_VOID, OP_VOID);
5380 RETVAL (cr16_callback->close (cr16_callback, PARM1));
5381 trace_output_16 (result);
5382 break;
5383
5384 case TARGET_SYS_open:
5385 trace_input ("<open>", OP_MEMREF, OP_REG, OP_VOID);
5386 RETVAL32 (cr16_callback->open (cr16_callback,
5387 MEMPTR ((((unsigned long)PARM2)<<16)|PARM1),
5388 PARM3));
5389 trace_output_32 (result);
5390 break;
5391
5392 #ifdef TARGET_SYS_rename
5393 case TARGET_SYS_rename:
5394 trace_input ("<rename>", OP_MEMREF, OP_MEMREF, OP_VOID);
5395 RETVAL (cr16_callback->rename (cr16_callback,
5396 MEMPTR ((((unsigned long)PARM2)<<16) |PARM1),
5397 MEMPTR ((((unsigned long)PARM4)<<16) |PARM3)));
5398 trace_output_16 (result);
5399 break;
5400 #endif
5401
5402 case 0x408: /* REVISIT: Added a dummy getenv call. */
5403 trace_input ("<getenv>", OP_MEMREF, OP_MEMREF, OP_VOID);
5404 RETVAL32 (0);
5405 trace_output_32 (result);
5406 break;
5407
5408 case TARGET_SYS_exit:
5409 trace_input ("<exit>", OP_VOID, OP_VOID, OP_VOID);
5410 State.exception = SIG_CR16_EXIT;
5411 trace_output_void ();
5412 break;
5413
5414 case TARGET_SYS_unlink:
5415 trace_input ("<unlink>", OP_MEMREF, OP_VOID, OP_VOID);
5416 RETVAL (cr16_callback->unlink (cr16_callback,
5417 MEMPTR (((unsigned long)PARM2<<16)|PARM1)));
5418 trace_output_16 (result);
5419 break;
5420
5421
5422 #ifdef TARGET_SYS_stat
5423 case TARGET_SYS_stat:
5424 trace_input ("<stat>", OP_VOID, OP_VOID, OP_VOID);
5425 /* stat system call. */
5426 {
5427 struct stat host_stat;
5428 reg_t buf;
5429
5430 RETVAL (stat (MEMPTR ((((unsigned long)PARM2) << 16)|PARM1), &host_stat));
5431
5432 buf = PARM2;
5433
5434 /* The hard-coded offsets and sizes were determined by using
5435 * the CR16 compiler on a test program that used struct stat.
5436 */
5437 SW (buf, host_stat.st_dev);
5438 SW (buf+2, host_stat.st_ino);
5439 SW (buf+4, host_stat.st_mode);
5440 SW (buf+6, host_stat.st_nlink);
5441 SW (buf+8, host_stat.st_uid);
5442 SW (buf+10, host_stat.st_gid);
5443 SW (buf+12, host_stat.st_rdev);
5444 SLW (buf+16, host_stat.st_size);
5445 SLW (buf+20, host_stat.st_atime);
5446 SLW (buf+28, host_stat.st_mtime);
5447 SLW (buf+36, host_stat.st_ctime);
5448 }
5449 trace_output_16 (result);
5450 break;
5451 #endif
5452
5453 #ifdef TARGET_SYS_chown
5454 case TARGET_SYS_chown:
5455 trace_input ("<chown>", OP_VOID, OP_VOID, OP_VOID);
5456 RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
5457 trace_output_16 (result);
5458 break;
5459 #endif
5460
5461 case TARGET_SYS_chmod:
5462 trace_input ("<chmod>", OP_VOID, OP_VOID, OP_VOID);
5463 RETVAL (chmod (MEMPTR (PARM1), PARM2));
5464 trace_output_16 (result);
5465 break;
5466
5467 #ifdef TARGET_SYS_utime
5468 case TARGET_SYS_utime:
5469 trace_input ("<utime>", OP_REG, OP_REG, OP_REG);
5470 /* Cast the second argument to void *, to avoid type mismatch
5471 if a prototype is present. */
5472 RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
5473 trace_output_16 (result);
5474 break;
5475 #endif
5476
5477 #ifdef TARGET_SYS_time
5478 case TARGET_SYS_time:
5479 trace_input ("<time>", OP_VOID, OP_VOID, OP_REG);
5480 RETVAL32 (time (NULL));
5481 trace_output_32 (result);
5482 break;
5483 #endif
5484
5485 default:
5486 a = OP[0];
5487 switch (a)
5488 {
5489 case TRAP_BREAKPOINT:
5490 State.exception = SIGTRAP;
5491 tmp = (PC);
5492 JMP(tmp);
5493 trace_output_void ();
5494 break;
5495 case SIGTRAP: /* supervisor call ? */
5496 State.exception = SIG_CR16_EXIT;
5497 trace_output_void ();
5498 break;
5499 default:
5500 cr16_callback->error (cr16_callback, "Unknown syscall %d", FUNC);
5501 break;
5502 }
5503 }
5504 if ((uint16) result == (uint16) -1)
5505 RETERR (cr16_callback->get_errno(cr16_callback));
5506 else
5507 RETERR (0);
5508 break;
5509 }
5510 }
5511 }
5512
5513
5514 /* push. */
5515 void
5516 OP_3_9 (void)
5517 {
5518 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5519 uint32 tmp, sp_addr = (GPR32 (15)) - (a * 2) - 4, is_regp = 0;
5520 trace_input ("push", OP_CONSTANT3, OP_REG, OP_REG);
5521
5522 for (; i < a; ++i)
5523 {
5524 if ((b+i) <= 11)
5525 {
5526 SW (sp_addr, (GPR (b+i)));
5527 sp_addr +=2;
5528 }
5529 else
5530 {
5531 if (is_regp == 0)
5532 tmp = (GPR32 (b+i));
5533 else
5534 tmp = (GPR32 (b+i-1));
5535
5536 if ((a-i) > 1)
5537 {
5538 SLW (sp_addr, tmp);
5539 sp_addr +=4;
5540 }
5541 else
5542 {
5543 SW (sp_addr, tmp);
5544 sp_addr +=2;
5545 }
5546 ++i;
5547 is_regp = 1;
5548 }
5549 }
5550
5551 sp_addr +=4;
5552
5553 /* Store RA address. */
5554 tmp = (GPR32 (14));
5555 SLW(sp_addr,tmp);
5556
5557 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5558 SET_GPR32 (15, sp_addr); /* Update SP address. */
5559
5560 trace_output_void ();
5561 }
5562
5563 /* push. */
5564 void
5565 OP_1_8 (void)
5566 {
5567 uint32 sp_addr, tmp, is_regp = 0;
5568 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5569 trace_input ("push", OP_CONSTANT3, OP_REG, OP_VOID);
5570
5571 if (c == 1)
5572 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5573 else
5574 sp_addr = (GPR32 (15)) - (a * 2);
5575
5576 for (; i < a; ++i)
5577 {
5578 if ((b+i) <= 11)
5579 {
5580 SW (sp_addr, (GPR (b+i)));
5581 sp_addr +=2;
5582 }
5583 else
5584 {
5585 if (is_regp == 0)
5586 tmp = (GPR32 (b+i));
5587 else
5588 tmp = (GPR32 (b+i-1));
5589
5590 if ((a-i) > 1)
5591 {
5592 SLW (sp_addr, tmp);
5593 sp_addr +=4;
5594 }
5595 else
5596 {
5597 SW (sp_addr, tmp);
5598 sp_addr +=2;
5599 }
5600 ++i;
5601 is_regp = 1;
5602 }
5603 }
5604
5605 if (c == 1)
5606 {
5607 /* Store RA address. */
5608 tmp = (GPR32 (14));
5609 SLW(sp_addr,tmp);
5610 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5611 }
5612 else
5613 sp_addr = (GPR32 (15)) - (a * 2);
5614
5615 SET_GPR32 (15, sp_addr); /* Update SP address. */
5616
5617 trace_output_void ();
5618 }
5619
5620
5621 /* push. */
5622 void
5623 OP_11E_10 (void)
5624 {
5625 uint32 sp_addr = (GPR32 (15)), tmp;
5626 trace_input ("push", OP_VOID, OP_VOID, OP_VOID);
5627 tmp = (GPR32 (14));
5628 SLW(sp_addr-4,tmp); /* Store RA address. */
5629 SET_GPR32 (15, (sp_addr - 4)); /* Update SP address. */
5630 trace_output_void ();
5631 }
5632
5633
5634 /* pop. */
5635 void
5636 OP_5_9 (void)
5637 {
5638 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5639 uint32 tmp, sp_addr = (GPR32 (15)), is_regp = 0;;
5640 trace_input ("pop", OP_CONSTANT3, OP_REG, OP_REG);
5641
5642 for (; i < a; ++i)
5643 {
5644 if ((b+i) <= 11)
5645 {
5646 SET_GPR ((b+i), RW(sp_addr));
5647 sp_addr +=2;
5648 }
5649 else
5650 {
5651 if ((a-i) > 1)
5652 {
5653 tmp = RLW(sp_addr);
5654 sp_addr +=4;
5655 }
5656 else
5657 {
5658 tmp = RW(sp_addr);
5659 sp_addr +=2;
5660
5661 if (is_regp == 0)
5662 tmp = (tmp << 16) | (GPR32 (b+i));
5663 else
5664 tmp = (tmp << 16) | (GPR32 (b+i-1));
5665 }
5666
5667 if (is_regp == 0)
5668 SET_GPR32 ((b+i), (((tmp & 0xffff) << 16)
5669 | ((tmp >> 16) & 0xffff)));
5670 else
5671 SET_GPR32 ((b+i-1), (((tmp & 0xffff) << 16)
5672 | ((tmp >> 16) & 0xffff)));
5673
5674 ++i;
5675 is_regp = 1;
5676 }
5677 }
5678
5679 tmp = RLW(sp_addr); /* store RA also. */
5680 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5681
5682 SET_GPR32 (15, (sp_addr + 4)); /* Update SP address. */
5683
5684 trace_output_void ();
5685 }
5686
5687 /* pop. */
5688 void
5689 OP_2_8 (void)
5690 {
5691 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5692 uint32 tmp, sp_addr = (GPR32 (15)), is_regp = 0;
5693 trace_input ("pop", OP_CONSTANT3, OP_REG, OP_VOID);
5694
5695 for (; i < a; ++i)
5696 {
5697 if ((b+i) <= 11)
5698 {
5699 SET_GPR ((b+i), RW(sp_addr));
5700 sp_addr +=2;
5701 }
5702 else
5703 {
5704 if ((a-i) > 1)
5705 {
5706 tmp = RLW(sp_addr);
5707 sp_addr +=4;
5708 }
5709 else
5710 {
5711 tmp = RW(sp_addr);
5712 sp_addr +=2;
5713
5714 if (is_regp == 0)
5715 tmp = ((tmp << 16) & 0xffffffff) | (GPR32 (b+i));
5716 else
5717 tmp = ((tmp << 16) & 0xffffffff) | (GPR32 (b+i-1));
5718 }
5719
5720 if (is_regp == 0)
5721 SET_GPR32 ((b+i), (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5722 else
5723 SET_GPR32 ((b+i-1), (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5724 ++i;
5725 is_regp = 1;
5726 }
5727 }
5728
5729 if (c == 1)
5730 {
5731 tmp = RLW(sp_addr); /* Store RA Reg. */
5732 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5733 sp_addr +=4;
5734 }
5735
5736 SET_GPR32 (15, sp_addr); /* Update SP address. */
5737
5738 trace_output_void ();
5739 }
5740
5741 /* pop. */
5742 void
5743 OP_21E_10 (void)
5744 {
5745 uint32 sp_addr = GPR32 (15);
5746 uint32 tmp;
5747 trace_input ("pop", OP_VOID, OP_VOID, OP_VOID);
5748
5749 tmp = RLW(sp_addr);
5750 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5751 SET_GPR32 (15, (sp_addr+4)); /* Update SP address. */
5752
5753 trace_output_void ();
5754 }
5755
5756 /* popret. */
5757 void
5758 OP_7_9 (void)
5759 {
5760 uint16 a = OP[0], b = OP[1];
5761 trace_input ("popret", OP_CONSTANT3, OP_REG, OP_REG);
5762 OP_5_9 ();
5763 JMP(((GPR32(14)) << 1) & 0xffffff);
5764
5765 trace_output_void ();
5766 }
5767
5768 /* popret. */
5769 void
5770 OP_3_8 (void)
5771 {
5772 uint16 a = OP[0], b = OP[1];
5773 trace_input ("popret", OP_CONSTANT3, OP_REG, OP_VOID);
5774 OP_2_8 ();
5775 JMP(((GPR32(14)) << 1) & 0xffffff);
5776
5777 trace_output_void ();
5778 }
5779
5780 /* popret. */
5781 void
5782 OP_31E_10 (void)
5783 {
5784 uint32 tmp;
5785 trace_input ("popret", OP_VOID, OP_VOID, OP_VOID);
5786 OP_21E_10 ();
5787 tmp = (((GPR32(14)) << 1) & 0xffffff);
5788 /* If the resulting PC value is less than 0x00_0000 or greater
5789 than 0xFF_FFFF, this instruction causes an IAD trap.*/
5790
5791 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
5792 {
5793 State.exception = SIG_CR16_BUS;
5794 State.pc_changed = 1; /* Don't increment the PC. */
5795 trace_output_void ();
5796 return;
5797 }
5798 else
5799 JMP (tmp);
5800
5801 trace_output_32 (tmp);
5802 }
5803
5804
5805 /* cinv[i]. */
5806 void
5807 OP_A_10 (void)
5808 {
5809 trace_input ("cinv[i]", OP_VOID, OP_VOID, OP_VOID);
5810 SET_PSR_I (1);
5811 trace_output_void ();
5812 }
5813
5814 /* cinv[i,u]. */
5815 void
5816 OP_B_10 (void)
5817 {
5818 trace_input ("cinv[i,u]", OP_VOID, OP_VOID, OP_VOID);
5819 SET_PSR_I (1);
5820 trace_output_void ();
5821 }
5822
5823 /* cinv[d]. */
5824 void
5825 OP_C_10 (void)
5826 {
5827 trace_input ("cinv[d]", OP_VOID, OP_VOID, OP_VOID);
5828 SET_PSR_I (1);
5829 trace_output_void ();
5830 }
5831
5832 /* cinv[d,u]. */
5833 void
5834 OP_D_10 (void)
5835 {
5836 trace_input ("cinv[i,u]", OP_VOID, OP_VOID, OP_VOID);
5837 SET_PSR_I (1);
5838 trace_output_void ();
5839 }
5840
5841 /* cinv[d,i]. */
5842 void
5843 OP_E_10 (void)
5844 {
5845 trace_input ("cinv[d,i]", OP_VOID, OP_VOID, OP_VOID);
5846 SET_PSR_I (1);
5847 trace_output_void ();
5848 }
5849
5850 /* cinv[d,i,u]. */
5851 void
5852 OP_F_10 (void)
5853 {
5854 trace_input ("cinv[d,i,u]", OP_VOID, OP_VOID, OP_VOID);
5855 SET_PSR_I (1);
5856 trace_output_void ();
5857 }
5858
5859 /* retx. */
5860 void
5861 OP_3_10 (void)
5862 {
5863 trace_input ("retx", OP_VOID, OP_VOID, OP_VOID);
5864 SET_PSR_I (1);
5865 trace_output_void ();
5866 }
5867
5868 /* di. */
5869 void
5870 OP_4_10 (void)
5871 {
5872 trace_input ("di", OP_VOID, OP_VOID, OP_VOID);
5873 SET_PSR_I (1);
5874 trace_output_void ();
5875 }
5876
5877 /* ei. */
5878 void
5879 OP_5_10 (void)
5880 {
5881 trace_input ("ei", OP_VOID, OP_VOID, OP_VOID);
5882 SET_PSR_I (1);
5883 trace_output_void ();
5884 }
5885
5886 /* wait. */
5887 void
5888 OP_6_10 (void)
5889 {
5890 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
5891 State.exception = SIGTRAP;
5892 trace_output_void ();
5893 }
5894
5895 /* ewait. */
5896 void
5897 OP_7_10 (void)
5898 {
5899 trace_input ("ewait", OP_VOID, OP_VOID, OP_VOID);
5900 SET_PSR_I (1);
5901 trace_output_void ();
5902 }
5903
5904 /* xorb. */
5905 void
5906 OP_28_8 (void)
5907 {
5908 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
5909 trace_input ("xorb", OP_CONSTANT4, OP_REG, OP_VOID);
5910 tmp = a ^ b;
5911 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
5912 trace_output_16 (tmp);
5913 }
5914
5915 /* xorb. */
5916 void
5917 OP_28B_C (void)
5918 {
5919 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
5920 trace_input ("xorb", OP_CONSTANT16, OP_REG, OP_VOID);
5921 tmp = a ^ b;
5922 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
5923 trace_output_16 (tmp);
5924 }
5925
5926 /* xorb. */
5927 void
5928 OP_29_8 (void)
5929 {
5930 uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
5931 trace_input ("xorb", OP_REG, OP_REG, OP_VOID);
5932 tmp = a ^ b;
5933 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
5934 trace_output_16 (tmp);
5935 }
5936
5937 /* xorw. */
5938 void
5939 OP_2A_8 (void)
5940 {
5941 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
5942 trace_input ("xorw", OP_CONSTANT4, OP_REG, OP_VOID);
5943 tmp = a ^ b;
5944 SET_GPR (OP[1], tmp);
5945 trace_output_16 (tmp);
5946 }
5947
5948 /* xorw. */
5949 void
5950 OP_2AB_C (void)
5951 {
5952 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
5953 trace_input ("xorw", OP_CONSTANT16, OP_REG, OP_VOID);
5954 tmp = a ^ b;
5955 SET_GPR (OP[1], tmp);
5956 trace_output_16 (tmp);
5957 }
5958
5959 /* xorw. */
5960 void
5961 OP_2B_8 (void)
5962 {
5963 uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
5964 trace_input ("xorw", OP_REG, OP_REG, OP_VOID);
5965 tmp = a ^ b;
5966 SET_GPR (OP[1], tmp);
5967 trace_output_16 (tmp);
5968 }
5969
5970 /*REVISIT FOR LPR/SPR . */
5971
5972 /* lpr. */
5973 void
5974 OP_140_14 (void)
5975 {
5976 uint16 a = GPR (OP[0]);
5977 trace_input ("lpr", OP_REG, OP_REG, OP_VOID);
5978 SET_CREG (OP[1], a);
5979 trace_output_16 (a);
5980 }
5981
5982 /* lprd. */
5983 void
5984 OP_141_14 (void)
5985 {
5986 uint32 a = GPR32 (OP[0]);
5987 trace_input ("lprd", OP_REGP, OP_REG, OP_VOID);
5988 SET_CREG (OP[1], a);
5989 trace_output_flag ();
5990 }
5991
5992 /* spr. */
5993 void
5994 OP_142_14 (void)
5995 {
5996 uint16 a = CREG (OP[0]);
5997 trace_input ("spr", OP_REG, OP_REG, OP_VOID);
5998 SET_GPR (OP[1], a);
5999 trace_output_16 (a);
6000 }
6001
6002 /* sprd. */
6003 void
6004 OP_143_14 (void)
6005 {
6006 uint32 a = CREG (OP[0]);
6007 trace_input ("sprd", OP_REGP, OP_REGP, OP_VOID);
6008 SET_GPR32 (OP[1], a);
6009 trace_output_32 (a);
6010 }
6011
6012 /* null. */
6013 void
6014 OP_0_20 (void)
6015 {
6016 trace_input ("null", OP_VOID, OP_VOID, OP_VOID);
6017 State.exception = SIG_CR16_STOP;
6018 }