projects / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
sim: rl78: clean up various warnings
[binutils-gdb.git] / sim / cr16 / simops.c
1 /* Simulation code for the CR16 processor.
2 Copyright (C) 2008-2021 Free Software Foundation, Inc.
3 Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com>
4
5 This file is part of GDB, the GNU debugger.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20
21 #include "config.h"
22
23 #include <signal.h>
24 #include <errno.h>
25 #include <sys/types.h>
26 #include <sys/stat.h>
27 #ifdef HAVE_UNISTD_H
28 #include <unistd.h>
29 #endif
30 #include <string.h>
31 #include <time.h>
32 #include <sys/time.h>
33
34 #include "sim-main.h"
35 #include "simops.h"
36 #include "targ-vals.h"
37
38 #ifdef TARGET_SYS_utime
39 #include <utime.h>
40 #endif
41 #ifdef TARGET_SYS_wait
42 #include <sys/wait.h>
43 #endif
44
45 #define EXCEPTION(sig) sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, sig)
46
47 enum op_types {
48 OP_VOID,
49 OP_CONSTANT3,
50 OP_UCONSTANT3,
51 OP_CONSTANT4,
52 OP_CONSTANT4_1,
53 OP_CONSTANT5,
54 OP_CONSTANT6,
55 OP_CONSTANT16,
56 OP_UCONSTANT16,
57 OP_CONSTANT20,
58 OP_UCONSTANT20,
59 OP_CONSTANT32,
60 OP_UCONSTANT32,
61 OP_MEMREF,
62 OP_MEMREF2,
63 OP_MEMREF3,
64
65 OP_DISP5,
66 OP_DISP17,
67 OP_DISP25,
68 OP_DISPE9,
69 //OP_ABS20,
70 OP_ABS20_OUTPUT,
71 //OP_ABS24,
72 OP_ABS24_OUTPUT,
73
74 OP_R_BASE_DISPS16,
75 OP_R_BASE_DISP20,
76 OP_R_BASE_DISPS20,
77 OP_R_BASE_DISPE20,
78
79 OP_RP_BASE_DISPE0,
80 OP_RP_BASE_DISP4,
81 OP_RP_BASE_DISPE4,
82 OP_RP_BASE_DISP14,
83 OP_RP_BASE_DISP16,
84 OP_RP_BASE_DISP20,
85 OP_RP_BASE_DISPS20,
86 OP_RP_BASE_DISPE20,
87
88 OP_R_INDEX7_ABS20,
89 OP_R_INDEX8_ABS20,
90
91 OP_RP_INDEX_DISP0,
92 OP_RP_INDEX_DISP14,
93 OP_RP_INDEX_DISP20,
94 OP_RP_INDEX_DISPS20,
95
96 OP_REG,
97 OP_REGP,
98 OP_PROC_REG,
99 OP_PROC_REGP,
100 OP_COND,
101 OP_RA
102 };
103
104
105 enum {
106 PSR_MASK = (PSR_I_BIT
107 | PSR_P_BIT
108 | PSR_E_BIT
109 | PSR_N_BIT
110 | PSR_Z_BIT
111 | PSR_F_BIT
112 | PSR_U_BIT
113 | PSR_L_BIT
114 | PSR_T_BIT
115 | PSR_C_BIT),
116 /* The following bits in the PSR _can't_ be set by instructions such
117 as mvtc. */
118 PSR_HW_MASK = (PSR_MASK)
119 };
120
121 /* cond Code Condition True State
122 * EQ Equal Z flag is 1
123 * NE Not Equal Z flag is 0
124 * CS Carry Set C flag is 1
125 * CC Carry Clear C flag is 0
126 * HI Higher L flag is 1
127 * LS Lower or Same L flag is 0
128 * GT Greater Than N flag is 1
129 * LE Less Than or Equal To N flag is 0
130 * FS Flag Set F flag is 1
131 * FC Flag Clear F flag is 0
132 * LO Lower Z and L flags are 0
133 * HS Higher or Same Z or L flag is 1
134 * LT Less Than Z and N flags are 0
135 * GE Greater Than or Equal To Z or N flag is 1. */
136
137 static int cond_stat(int cc)
138 {
139 switch (cc)
140 {
141 case 0: return PSR_Z; break;
142 case 1: return !PSR_Z; break;
143 case 2: return PSR_C; break;
144 case 3: return !PSR_C; break;
145 case 4: return PSR_L; break;
146 case 5: return !PSR_L; break;
147 case 6: return PSR_N; break;
148 case 7: return !PSR_N; break;
149 case 8: return PSR_F; break;
150 case 9: return !PSR_F; break;
151 case 10: return !PSR_Z && !PSR_L; break;
152 case 11: return PSR_Z || PSR_L; break;
153 case 12: return !PSR_Z && !PSR_N; break;
154 case 13: return PSR_Z || PSR_N; break;
155 case 14: return 1; break; /*ALWAYS. */
156 default:
157 // case NEVER: return false; break;
158 //case NO_COND_CODE:
159 //panic("Shouldn't have NO_COND_CODE in an actual instruction!");
160 return 0; break;
161 }
162 return 0;
163 }
164
165
166 creg_t
167 move_to_cr (SIM_DESC sd, SIM_CPU *cpu, int cr, creg_t mask, creg_t val, int psw_hw_p)
168 {
169 /* A MASK bit is set when the corresponding bit in the CR should
170 be left alone. */
171 /* This assumes that (VAL & MASK) == 0. */
172 switch (cr)
173 {
174 case PSR_CR:
175 if (psw_hw_p)
176 val &= PSR_HW_MASK;
177 #if 0
178 else
179 val &= PSR_MASK;
180 sim_io_printf
181 (sd,
182 "ERROR at PC 0x%x: ST can only be set when FX is set.\n", PC);
183 EXCEPTION (SIM_SIGILL);
184 #endif
185 /* keep an up-to-date psw around for tracing. */
186 State.trace.psw = (State.trace.psw & mask) | val;
187 break;
188 default:
189 break;
190 }
191 /* only issue an update if the register is being changed. */
192 if ((State.cregs[cr] & ~mask) != val)
193 SLOT_PEND_MASK (State.cregs[cr], mask, val);
194
195 return val;
196 }
197
198 #ifdef DEBUG
199 static void trace_input_func (SIM_DESC sd,
200 const char *name,
201 enum op_types in1,
202 enum op_types in2,
203 enum op_types in3);
204
205 #define trace_input(name, in1, in2, in3) do { if (cr16_debug) trace_input_func (sd, name, in1, in2, in3); } while (0)
206
207 #ifndef SIZE_INSTRUCTION
208 #define SIZE_INSTRUCTION 8
209 #endif
210
211 #ifndef SIZE_OPERANDS
212 #define SIZE_OPERANDS 18
213 #endif
214
215 #ifndef SIZE_VALUES
216 #define SIZE_VALUES 13
217 #endif
218
219 #ifndef SIZE_LOCATION
220 #define SIZE_LOCATION 20
221 #endif
222
223 #ifndef SIZE_PC
224 #define SIZE_PC 4
225 #endif
226
227 #ifndef SIZE_LINE_NUMBER
228 #define SIZE_LINE_NUMBER 2
229 #endif
230
231 static void
232 trace_input_func (SIM_DESC sd, const char *name, enum op_types in1, enum op_types in2, enum op_types in3)
233 {
234 char *comma;
235 enum op_types in[3];
236 int i;
237 char buf[1024];
238 char *p;
239 long tmp;
240 char *type;
241 const char *filename;
242 const char *functionname;
243 unsigned int linenumber;
244 bfd_vma byte_pc;
245
246 if ((cr16_debug & DEBUG_TRACE) == 0)
247 return;
248
249 switch (State.ins_type)
250 {
251 default:
252 case INS_UNKNOWN: type = " ?"; break;
253 }
254
255 if ((cr16_debug & DEBUG_LINE_NUMBER) == 0)
256 sim_io_printf (sd,
257 "0x%.*x %s: %-*s ",
258 SIZE_PC, (unsigned)PC,
259 type,
260 SIZE_INSTRUCTION, name);
261
262 else
263 {
264 buf[0] = '\0';
265 byte_pc = PC;
266 if (STATE_TEXT_SECTION (sd)
267 && byte_pc >= STATE_TEXT_START (sd)
268 && byte_pc < STATE_TEXT_END (sd))
269 {
270 filename = (const char *)0;
271 functionname = (const char *)0;
272 linenumber = 0;
273 if (bfd_find_nearest_line (STATE_PROG_BFD (sd),
274 STATE_TEXT_SECTION (sd),
275 (struct bfd_symbol **)0,
276 byte_pc - STATE_TEXT_START (sd),
277 &filename, &functionname, &linenumber))
278 {
279 p = buf;
280 if (linenumber)
281 {
282 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber);
283 p += strlen (p);
284 }
285 else
286 {
287 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---");
288 p += SIZE_LINE_NUMBER+2;
289 }
290
291 if (functionname)
292 {
293 sprintf (p, "%s ", functionname);
294 p += strlen (p);
295 }
296 else if (filename)
297 {
298 char *q = strrchr (filename, '/');
299 sprintf (p, "%s ", (q) ? q+1 : filename);
300 p += strlen (p);
301 }
302
303 if (*p == ' ')
304 *p = '\0';
305 }
306 }
307
308 sim_io_printf (sd,
309 "0x%.*x %s: %-*.*s %-*s ",
310 SIZE_PC, (unsigned)PC,
311 type,
312 SIZE_LOCATION, SIZE_LOCATION, buf,
313 SIZE_INSTRUCTION, name);
314 }
315
316 in[0] = in1;
317 in[1] = in2;
318 in[2] = in3;
319 comma = "";
320 p = buf;
321 for (i = 0; i < 3; i++)
322 {
323 switch (in[i])
324 {
325 case OP_VOID:
326 break;
327
328 case OP_REG:
329 case OP_REGP:
330 sprintf (p, "%sr%d", comma, OP[i]);
331 p += strlen (p);
332 comma = ",";
333 break;
334
335 case OP_PROC_REG:
336 sprintf (p, "%scr%d", comma, OP[i]);
337 p += strlen (p);
338 comma = ",";
339 break;
340
341 case OP_CONSTANT16:
342 sprintf (p, "%s%d", comma, OP[i]);
343 p += strlen (p);
344 comma = ",";
345 break;
346
347 case OP_CONSTANT4:
348 sprintf (p, "%s%d", comma, SEXT4(OP[i]));
349 p += strlen (p);
350 comma = ",";
351 break;
352
353 case OP_CONSTANT3:
354 sprintf (p, "%s%d", comma, SEXT3(OP[i]));
355 p += strlen (p);
356 comma = ",";
357 break;
358
359 case OP_MEMREF:
360 sprintf (p, "%s@r%d", comma, OP[i]);
361 p += strlen (p);
362 comma = ",";
363 break;
364
365 case OP_MEMREF2:
366 sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]);
367 p += strlen (p);
368 comma = ",";
369 break;
370
371 case OP_MEMREF3:
372 sprintf (p, "%s@%d", comma, OP[i]);
373 p += strlen (p);
374 comma = ",";
375 break;
376 }
377 }
378
379 if ((cr16_debug & DEBUG_VALUES) == 0)
380 {
381 *p++ = '\n';
382 *p = '\0';
383 sim_io_printf (sd, "%s", buf);
384 }
385 else
386 {
387 *p = '\0';
388 sim_io_printf (sd, "%-*s", SIZE_OPERANDS, buf);
389
390 p = buf;
391 for (i = 0; i < 3; i++)
392 {
393 buf[0] = '\0';
394 switch (in[i])
395 {
396 case OP_VOID:
397 sim_io_printf (sd, "%*s", SIZE_VALUES, "");
398 break;
399
400 case OP_REG:
401 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
402 (uint16) GPR (OP[i]));
403 break;
404
405 case OP_REGP:
406 tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
407 sim_io_printf (sd, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
408 break;
409
410 case OP_PROC_REG:
411 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
412 (uint16) CREG (OP[i]));
413 break;
414
415 case OP_CONSTANT16:
416 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
417 (uint16)OP[i]);
418 break;
419
420 case OP_CONSTANT4:
421 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
422 (uint16)SEXT4(OP[i]));
423 break;
424
425 case OP_CONSTANT3:
426 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
427 (uint16)SEXT3(OP[i]));
428 break;
429
430 case OP_MEMREF2:
431 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
432 (uint16)OP[i]);
433 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
434 (uint16)GPR (OP[i + 1]));
435 i++;
436 break;
437 }
438 }
439 }
440
441 sim_io_flush_stdout (sd);
442 }
443
444 static void
445 do_trace_output_flush (SIM_DESC sd)
446 {
447 sim_io_flush_stdout (sd);
448 }
449
450 static void
451 do_trace_output_finish (SIM_DESC sd)
452 {
453 sim_io_printf (sd,
454 " F0=%d F1=%d C=%d\n",
455 (State.trace.psw & PSR_F_BIT) != 0,
456 (State.trace.psw & PSR_F_BIT) != 0,
457 (State.trace.psw & PSR_C_BIT) != 0);
458 sim_io_flush_stdout (sd);
459 }
460
461 #if 0
462 static void
463 trace_output_40 (SIM_DESC sd, uint64 val)
464 {
465 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
466 {
467 sim_io_printf (sd,
468 " :: %*s0x%.2x%.8lx",
469 SIZE_VALUES - 12,
470 "",
471 ((int)(val >> 32) & 0xff),
472 ((unsigned long) val) & 0xffffffff);
473 do_trace_output_finish ();
474 }
475 }
476 #endif
477
478 static void
479 trace_output_32 (SIM_DESC sd, uint32 val)
480 {
481 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
482 {
483 sim_io_printf (sd,
484 " :: %*s0x%.8x",
485 SIZE_VALUES - 10,
486 "",
487 (int) val);
488 do_trace_output_finish (sd);
489 }
490 }
491
492 static void
493 trace_output_16 (SIM_DESC sd, uint16 val)
494 {
495 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
496 {
497 sim_io_printf (sd,
498 " :: %*s0x%.4x",
499 SIZE_VALUES - 6,
500 "",
501 (int) val);
502 do_trace_output_finish (sd);
503 }
504 }
505
506 static void
507 trace_output_void (SIM_DESC sd)
508 {
509 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
510 {
511 sim_io_printf (sd, "\n");
512 do_trace_output_flush (sd);
513 }
514 }
515
516 static void
517 trace_output_flag (SIM_DESC sd)
518 {
519 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
520 {
521 sim_io_printf (sd,
522 " :: %*s",
523 SIZE_VALUES,
524 "");
525 do_trace_output_finish (sd);
526 }
527 }
528
529
530
531
532 #else
533 #define trace_input(NAME, IN1, IN2, IN3)
534 #define trace_output(RESULT)
535 #endif
536
537 /* addub. */
538 void
539 OP_2C_8 (SIM_DESC sd, SIM_CPU *cpu)
540 {
541 uint8 tmp;
542 uint8 a = OP[0] & 0xff;
543 uint16 b = (GPR (OP[1])) & 0xff;
544 trace_input ("addub", OP_CONSTANT4_1, OP_REG, OP_VOID);
545 tmp = (a + b) & 0xff;
546 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
547 trace_output_16 (sd, tmp);
548 }
549
550 /* addub. */
551 void
552 OP_2CB_C (SIM_DESC sd, SIM_CPU *cpu)
553 {
554 uint16 tmp;
555 uint8 a = ((OP[0]) & 0xff), b = (GPR (OP[1])) & 0xff;
556 trace_input ("addub", OP_CONSTANT16, OP_REG, OP_VOID);
557 tmp = (a + b) & 0xff;
558 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
559 trace_output_16 (sd, tmp);
560 }
561
562 /* addub. */
563 void
564 OP_2D_8 (SIM_DESC sd, SIM_CPU *cpu)
565 {
566 uint8 a = (GPR (OP[0])) & 0xff;
567 uint8 b = (GPR (OP[1])) & 0xff;
568 uint16 tmp = (a + b) & 0xff;
569 trace_input ("addub", OP_REG, OP_REG, OP_VOID);
570 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
571 trace_output_16 (sd, tmp);
572 }
573
574 /* adduw. */
575 void
576 OP_2E_8 (SIM_DESC sd, SIM_CPU *cpu)
577 {
578 uint16 a = OP[0];
579 uint16 b = GPR (OP[1]);
580 uint16 tmp = (a + b);
581 trace_input ("adduw", OP_CONSTANT4_1, OP_REG, OP_VOID);
582 SET_GPR (OP[1], tmp);
583 trace_output_16 (sd, tmp);
584 }
585
586 /* adduw. */
587 void
588 OP_2EB_C (SIM_DESC sd, SIM_CPU *cpu)
589 {
590 uint16 a = OP[0];
591 uint16 b = GPR (OP[1]);
592 uint16 tmp = (a + b);
593 trace_input ("adduw", OP_CONSTANT16, OP_REG, OP_VOID);
594 SET_GPR (OP[1], tmp);
595 trace_output_16 (sd, tmp);
596 }
597
598 /* adduw. */
599 void
600 OP_2F_8 (SIM_DESC sd, SIM_CPU *cpu)
601 {
602 uint16 a = GPR (OP[0]);
603 uint16 b = GPR (OP[1]);
604 uint16 tmp = (a + b);
605 trace_input ("adduw", OP_REG, OP_REG, OP_VOID);
606 SET_GPR (OP[1], tmp);
607 trace_output_16 (sd, tmp);
608 }
609
610 /* addb. */
611 void
612 OP_30_8 (SIM_DESC sd, SIM_CPU *cpu)
613 {
614 uint8 a = OP[0];
615 uint8 b = (GPR (OP[1]) & 0xff);
616 uint16 tmp = (a + b) & 0xff;
617 trace_input ("addb", OP_CONSTANT4_1, OP_REG, OP_VOID);
618 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
619 SET_PSR_C (tmp > 0xFF);
620 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
621 trace_output_16 (sd, tmp);
622 }
623
624 /* addb. */
625 void
626 OP_30B_C (SIM_DESC sd, SIM_CPU *cpu)
627 {
628 uint8 a = (OP[0]) & 0xff;
629 uint8 b = (GPR (OP[1]) & 0xff);
630 uint16 tmp = (a + b) & 0xff;
631 trace_input ("addb", OP_CONSTANT16, OP_REG, OP_VOID);
632 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
633 SET_PSR_C (tmp > 0xFF);
634 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
635 trace_output_16 (sd, tmp);
636 }
637
638 /* addb. */
639 void
640 OP_31_8 (SIM_DESC sd, SIM_CPU *cpu)
641 {
642 uint8 a = (GPR (OP[0]) & 0xff);
643 uint8 b = (GPR (OP[1]) & 0xff);
644 uint16 tmp = (a + b) & 0xff;
645 trace_input ("addb", OP_REG, OP_REG, OP_VOID);
646 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
647 SET_PSR_C (tmp > 0xFF);
648 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
649 trace_output_16 (sd, tmp);
650 }
651
652 /* addw. */
653 void
654 OP_32_8 (SIM_DESC sd, SIM_CPU *cpu)
655 {
656 int16 a = OP[0];
657 uint16 tmp, b = GPR (OP[1]);
658 tmp = (a + b);
659 trace_input ("addw", OP_CONSTANT4_1, OP_REG, OP_VOID);
660 SET_GPR (OP[1], tmp);
661 SET_PSR_C (tmp > 0xFFFF);
662 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
663 trace_output_16 (sd, tmp);
664 }
665
666 /* addw. */
667 void
668 OP_32B_C (SIM_DESC sd, SIM_CPU *cpu)
669 {
670 int16 a = OP[0];
671 uint16 tmp, b = GPR (OP[1]);
672 tmp = (a + b);
673 trace_input ("addw", OP_CONSTANT16, OP_REG, OP_VOID);
674 SET_GPR (OP[1], tmp);
675 SET_PSR_C (tmp > 0xFFFF);
676 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
677 trace_output_16 (sd, tmp);
678 }
679
680 /* addw. */
681 void
682 OP_33_8 (SIM_DESC sd, SIM_CPU *cpu)
683 {
684 uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
685 trace_input ("addw", OP_REG, OP_REG, OP_VOID);
686 tmp = (a + b);
687 SET_GPR (OP[1], tmp);
688 SET_PSR_C (tmp > 0xFFFF);
689 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
690 trace_output_16 (sd, tmp);
691 }
692
693 /* addcb. */
694 void
695 OP_34_8 (SIM_DESC sd, SIM_CPU *cpu)
696 {
697 uint8 tmp, a = OP[0] & 0xff, b = (GPR (OP[1])) & 0xff;
698 trace_input ("addcb", OP_CONSTANT4_1, OP_REG, OP_REG);
699 tmp = (a + b + PSR_C) & 0xff;
700 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
701 SET_PSR_C (tmp > 0xFF);
702 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
703 trace_output_16 (sd, tmp);
704 }
705
706 /* addcb. */
707 void
708 OP_34B_C (SIM_DESC sd, SIM_CPU *cpu)
709 {
710 int8 a = OP[0] & 0xff;
711 uint8 b = (GPR (OP[1])) & 0xff;
712 uint8 tmp = (a + b + PSR_C) & 0xff;
713 trace_input ("addcb", OP_CONSTANT16, OP_REG, OP_VOID);
714 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
715 SET_PSR_C (tmp > 0xFF);
716 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
717 trace_output_16 (sd, tmp);
718 }
719
720 /* addcb. */
721 void
722 OP_35_8 (SIM_DESC sd, SIM_CPU *cpu)
723 {
724 uint8 a = (GPR (OP[0])) & 0xff;
725 uint8 b = (GPR (OP[1])) & 0xff;
726 uint8 tmp = (a + b + PSR_C) & 0xff;
727 trace_input ("addcb", OP_REG, OP_REG, OP_VOID);
728 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
729 SET_PSR_C (tmp > 0xFF);
730 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
731 trace_output_16 (sd, tmp);
732 }
733
734 /* addcw. */
735 void
736 OP_36_8 (SIM_DESC sd, SIM_CPU *cpu)
737 {
738 uint16 a = OP[0];
739 uint16 b = GPR (OP[1]);
740 uint16 tmp = (a + b + PSR_C);
741 trace_input ("addcw", OP_CONSTANT4_1, OP_REG, OP_VOID);
742 SET_GPR (OP[1], tmp);
743 SET_PSR_C (tmp > 0xFFFF);
744 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
745 trace_output_16 (sd, tmp);
746 }
747
748 /* addcw. */
749 void
750 OP_36B_C (SIM_DESC sd, SIM_CPU *cpu)
751 {
752 int16 a = OP[0];
753 uint16 b = GPR (OP[1]);
754 uint16 tmp = (a + b + PSR_C);
755 trace_input ("addcw", OP_CONSTANT16, OP_REG, OP_VOID);
756 SET_GPR (OP[1], tmp);
757 SET_PSR_C (tmp > 0xFFFF);
758 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
759 trace_output_16 (sd, tmp);
760 }
761
762 /* addcw. */
763 void
764 OP_37_8 (SIM_DESC sd, SIM_CPU *cpu)
765 {
766 uint16 a = GPR (OP[1]);
767 uint16 b = GPR (OP[1]);
768 uint16 tmp = (a + b + PSR_C);
769 trace_input ("addcw", OP_REG, OP_REG, OP_VOID);
770 SET_GPR (OP[1], tmp);
771 SET_PSR_C (tmp > 0xFFFF);
772 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
773 trace_output_16 (sd, tmp);
774 }
775
776 /* addd. */
777 void
778 OP_60_8 (SIM_DESC sd, SIM_CPU *cpu)
779 {
780 int16 a = (OP[0]);
781 uint32 b = GPR32 (OP[1]);
782 uint32 tmp = (a + b);
783 trace_input ("addd", OP_CONSTANT4_1, OP_REGP, OP_VOID);
784 SET_GPR32 (OP[1], tmp);
785 SET_PSR_C (tmp > 0xFFFFFFFF);
786 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
787 trace_output_32 (sd, tmp);
788 }
789
790 /* addd. */
791 void
792 OP_60B_C (SIM_DESC sd, SIM_CPU *cpu)
793 {
794 int32 a = (SEXT16(OP[0]));
795 uint32 b = GPR32 (OP[1]);
796 uint32 tmp = (a + b);
797 trace_input ("addd", OP_CONSTANT16, OP_REGP, OP_VOID);
798 SET_GPR32 (OP[1], tmp);
799 SET_PSR_C (tmp > 0xFFFFFFFF);
800 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
801 trace_output_32 (sd, tmp);
802 }
803
804 /* addd. */
805 void
806 OP_61_8 (SIM_DESC sd, SIM_CPU *cpu)
807 {
808 uint32 a = GPR32 (OP[0]);
809 uint32 b = GPR32 (OP[1]);
810 uint32 tmp = (a + b);
811 trace_input ("addd", OP_REGP, OP_REGP, OP_VOID);
812 SET_GPR32 (OP[1], tmp);
813 trace_output_32 (sd, tmp);
814 SET_PSR_C (tmp > 0xFFFFFFFF);
815 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
816 }
817
818 /* addd. */
819 void
820 OP_4_8 (SIM_DESC sd, SIM_CPU *cpu)
821 {
822 uint32 a = OP[0];
823 uint32 b = GPR32 (OP[1]);
824 uint32 tmp;
825 trace_input ("addd", OP_CONSTANT20, OP_REGP, OP_VOID);
826 tmp = (a + b);
827 SET_GPR32 (OP[1], tmp);
828 SET_PSR_C (tmp > 0xFFFFFFFF);
829 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
830 trace_output_32 (sd, tmp);
831 }
832
833 /* addd. */
834 void
835 OP_2_C (SIM_DESC sd, SIM_CPU *cpu)
836 {
837 int32 a = OP[0];
838 uint32 b = GPR32 (OP[1]);
839 uint32 tmp;
840 trace_input ("addd", OP_CONSTANT32, OP_REGP, OP_VOID);
841 tmp = (a + b);
842 SET_GPR32 (OP[1], tmp);
843 SET_PSR_C (tmp > 0xFFFFFFFF);
844 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000)));
845 trace_output_32 (sd, tmp);
846 }
847
848 /* andb. */
849 void
850 OP_20_8 (SIM_DESC sd, SIM_CPU *cpu)
851 {
852 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
853 trace_input ("andb", OP_CONSTANT4, OP_REG, OP_VOID);
854 tmp = a & b;
855 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
856 trace_output_16 (sd, tmp);
857 }
858
859 /* andb. */
860 void
861 OP_20B_C (SIM_DESC sd, SIM_CPU *cpu)
862 {
863 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
864 trace_input ("andb", OP_CONSTANT16, OP_REG, OP_VOID);
865 tmp = a & b;
866 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
867 trace_output_16 (sd, tmp);
868 }
869
870 /* andb. */
871 void
872 OP_21_8 (SIM_DESC sd, SIM_CPU *cpu)
873 {
874 uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
875 trace_input ("andb", OP_REG, OP_REG, OP_VOID);
876 tmp = a & b;
877 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
878 trace_output_16 (sd, tmp);
879 }
880
881 /* andw. */
882 void
883 OP_22_8 (SIM_DESC sd, SIM_CPU *cpu)
884 {
885 uint16 tmp, a = OP[0], b = GPR (OP[1]);
886 trace_input ("andw", OP_CONSTANT4, OP_REG, OP_VOID);
887 tmp = a & b;
888 SET_GPR (OP[1], tmp);
889 trace_output_16 (sd, tmp);
890 }
891
892 /* andw. */
893 void
894 OP_22B_C (SIM_DESC sd, SIM_CPU *cpu)
895 {
896 uint16 tmp, a = OP[0], b = GPR (OP[1]);
897 trace_input ("andw", OP_CONSTANT16, OP_REG, OP_VOID);
898 tmp = a & b;
899 SET_GPR (OP[1], tmp);
900 trace_output_16 (sd, tmp);
901 }
902
903 /* andw. */
904 void
905 OP_23_8 (SIM_DESC sd, SIM_CPU *cpu)
906 {
907 uint16 tmp, a = GPR (OP[0]), b = GPR (OP[1]);
908 trace_input ("andw", OP_REG, OP_REG, OP_VOID);
909 tmp = a & b;
910 SET_GPR (OP[1], tmp);
911 trace_output_16 (sd, tmp);
912 }
913
914 /* andd. */
915 void
916 OP_4_C (SIM_DESC sd, SIM_CPU *cpu)
917 {
918 uint32 tmp, a = OP[0], b = GPR32 (OP[1]);
919 trace_input ("andd", OP_CONSTANT32, OP_REGP, OP_VOID);
920 tmp = a & b;
921 SET_GPR32 (OP[1], tmp);
922 trace_output_32 (sd, tmp);
923 }
924
925 /* andd. */
926 void
927 OP_14B_14 (SIM_DESC sd, SIM_CPU *cpu)
928 {
929 uint32 tmp, a = (GPR32 (OP[0])), b = (GPR32 (OP[1]));
930 trace_input ("andd", OP_REGP, OP_REGP, OP_VOID);
931 tmp = a & b;
932 SET_GPR32 (OP[1], tmp);
933 trace_output_32 (sd, tmp);
934 }
935
936 /* ord. */
937 void
938 OP_5_C (SIM_DESC sd, SIM_CPU *cpu)
939 {
940 uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]);
941 trace_input ("ord", OP_CONSTANT32, OP_REG, OP_VOID);
942 tmp = a | b;
943 SET_GPR32 (OP[1], tmp);
944 trace_output_32 (sd, tmp);
945 }
946
947 /* ord. */
948 void
949 OP_149_14 (SIM_DESC sd, SIM_CPU *cpu)
950 {
951 uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
952 trace_input ("ord", OP_REGP, OP_REGP, OP_VOID);
953 tmp = a | b;
954 SET_GPR32 (OP[1], tmp);
955 trace_output_32 (sd, tmp);
956 }
957
958 /* xord. */
959 void
960 OP_6_C (SIM_DESC sd, SIM_CPU *cpu)
961 {
962 uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]);
963 trace_input ("xord", OP_CONSTANT32, OP_REG, OP_VOID);
964 tmp = a ^ b;
965 SET_GPR32 (OP[1], tmp);
966 trace_output_32 (sd, tmp);
967 }
968
969 /* xord. */
970 void
971 OP_14A_14 (SIM_DESC sd, SIM_CPU *cpu)
972 {
973 uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]);
974 trace_input ("xord", OP_REGP, OP_REGP, OP_VOID);
975 tmp = a ^ b;
976 SET_GPR32 (OP[1], tmp);
977 trace_output_32 (sd, tmp);
978 }
979
980
981 /* b. */
982 void
983 OP_1_4 (SIM_DESC sd, SIM_CPU *cpu)
984 {
985 uint32 tmp = 0, cc = cond_stat (OP[0]);
986 trace_input ("b", OP_CONSTANT4, OP_DISPE9, OP_VOID);
987 if (cc)
988 {
989 if (sign_flag)
990 tmp = (PC - (OP[1]));
991 else
992 tmp = (PC + (OP[1]));
993 /* If the resulting PC value is less than 0x00_0000 or greater
994 than 0xFF_FFFF, this instruction causes an IAD trap.*/
995
996 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
997 {
998 trace_output_void (sd);
999 EXCEPTION (SIM_SIGBUS);
1000 }
1001 else
1002 JMP (tmp);
1003 }
1004 sign_flag = 0; /* Reset sign_flag. */
1005 trace_output_32 (sd, tmp);
1006 }
1007
1008 /* b. */
1009 void
1010 OP_18_8 (SIM_DESC sd, SIM_CPU *cpu)
1011 {
1012 uint32 tmp = 0, cc = cond_stat (OP[0]);
1013 trace_input ("b", OP_CONSTANT4, OP_DISP17, OP_VOID);
1014 if (cc)
1015 {
1016 if (sign_flag)
1017 tmp = (PC - OP[1]);
1018 else
1019 tmp = (PC + OP[1]);
1020 /* If the resulting PC value is less than 0x00_0000 or greater
1021 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1022
1023 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1024 {
1025 trace_output_void (sd);
1026 EXCEPTION (SIM_SIGBUS);
1027 }
1028 else
1029 JMP (tmp);
1030 }
1031 sign_flag = 0; /* Reset sign_flag. */
1032 trace_output_32 (sd, tmp);
1033 }
1034
1035 /* b. */
1036 void
1037 OP_10_10 (SIM_DESC sd, SIM_CPU *cpu)
1038 {
1039 uint32 tmp = 0, cc = cond_stat (OP[0]);
1040 trace_input ("b", OP_CONSTANT4, OP_DISP25, OP_VOID);
1041 if (cc)
1042 {
1043 if (sign_flag)
1044 tmp = (PC - (OP[1]));
1045 else
1046 tmp = (PC + (OP[1]));
1047 /* If the resulting PC value is less than 0x00_0000 or greater
1048 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1049
1050 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1051 {
1052 trace_output_void (sd);
1053 EXCEPTION (SIM_SIGBUS);
1054 }
1055 else
1056 JMP (tmp);
1057 }
1058 sign_flag = 0; /* Reset sign_flag. */
1059 trace_output_32 (sd, tmp);
1060 }
1061
1062 /* bal. */
1063 void
1064 OP_C0_8 (SIM_DESC sd, SIM_CPU *cpu)
1065 {
1066 uint32 tmp;
1067 trace_input ("bal", OP_REG, OP_DISP17, OP_VOID);
1068 tmp = ((PC + 4) >> 1); /* Store PC in RA register. */
1069 SET_GPR32 (14, tmp);
1070 if (sign_flag)
1071 tmp = (PC - (OP[1]));
1072 else
1073 tmp = (PC + (OP[1]));
1074
1075 /* If the resulting PC value is less than 0x00_0000 or greater
1076 than 0xFF_FFFF, this instruction causes an IAD trap. */
1077
1078 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1079 {
1080 trace_output_void (sd);
1081 EXCEPTION (SIM_SIGBUS);
1082 }
1083 else
1084 JMP (tmp);
1085 sign_flag = 0; /* Reset sign_flag. */
1086 trace_output_32 (sd, tmp);
1087 }
1088
1089
1090 /* bal. */
1091 void
1092 OP_102_14 (SIM_DESC sd, SIM_CPU *cpu)
1093 {
1094 uint32 tmp;
1095 trace_input ("bal", OP_REGP, OP_DISP25, OP_VOID);
1096 tmp = (((PC) + 4) >> 1); /* Store PC in reg pair. */
1097 SET_GPR32 (OP[0], tmp);
1098 if (sign_flag)
1099 tmp = ((PC) - (OP[1]));
1100 else
1101 tmp = ((PC) + (OP[1]));
1102 /* If the resulting PC value is less than 0x00_0000 or greater
1103 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1104
1105 if ((tmp < 0x000000) || (tmp > 0xFFFFFF))
1106 {
1107 trace_output_void (sd);
1108 EXCEPTION (SIM_SIGBUS);
1109 }
1110 else
1111 JMP (tmp);
1112 sign_flag = 0; /* Reset sign_flag. */
1113 trace_output_32 (sd, tmp);
1114 }
1115
1116 /* jal. */
1117 void
1118 OP_148_14 (SIM_DESC sd, SIM_CPU *cpu)
1119 {
1120 uint32 tmp;
1121 trace_input ("jal", OP_REGP, OP_REGP, OP_VOID);
1122 SET_GPR32 (OP[0], (((PC) + 4) >> 1)); /* Store next PC in RA */
1123 tmp = GPR32 (OP[1]);
1124 tmp = SEXT24(tmp << 1);
1125 /* If the resulting PC value is less than 0x00_0000 or greater
1126 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1127
1128 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
1129 {
1130 trace_output_void (sd);
1131 EXCEPTION (SIM_SIGBUS);
1132 }
1133 else
1134 JMP (tmp);
1135
1136 trace_output_32 (sd, tmp);
1137 }
1138
1139
1140 /* jal. */
1141 void
1142 OP_D_C (SIM_DESC sd, SIM_CPU *cpu)
1143 {
1144 uint32 tmp;
1145 trace_input ("jal", OP_REGP, OP_VOID, OP_VOID);
1146 SET_GPR32 (14, (((PC) + 2) >> 1)); /* Store next PC in RA */
1147 tmp = GPR32 (OP[0]);
1148 tmp = SEXT24(tmp << 1);
1149 /* If the resulting PC value is less than 0x00_0000 or greater
1150 than 0xFF_FFFF, this instruction causes an IAD trap.*/
1151
1152 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
1153 {
1154 trace_output_void (sd);
1155 EXCEPTION (SIM_SIGBUS);
1156 }
1157 else
1158 JMP (tmp);
1159
1160 trace_output_32 (sd, tmp);
1161 }
1162
1163
1164 /* beq0b. */
1165 void
1166 OP_C_8 (SIM_DESC sd, SIM_CPU *cpu)
1167 {
1168 uint32 addr;
1169 uint8 a = (GPR (OP[0]) & 0xFF);
1170 trace_input ("beq0b", OP_REG, OP_DISP5, OP_VOID);
1171 addr = OP[1];
1172 if (a == 0)
1173 {
1174 if (sign_flag)
1175 addr = (PC - OP[1]);
1176 else
1177 addr = (PC + OP[1]);
1178
1179 JMP (addr);
1180 }
1181 sign_flag = 0; /* Reset sign_flag. */
1182 trace_output_void (sd);
1183 }
1184
1185 /* bne0b. */
1186 void
1187 OP_D_8 (SIM_DESC sd, SIM_CPU *cpu)
1188 {
1189 uint32 addr;
1190 uint8 a = (GPR (OP[0]) & 0xFF);
1191 trace_input ("bne0b", OP_REG, OP_DISP5, OP_VOID);
1192 addr = OP[1];
1193 if (a != 0)
1194 {
1195 if (sign_flag)
1196 addr = (PC - OP[1]);
1197 else
1198 addr = (PC + OP[1]);
1199
1200 JMP (addr);
1201 }
1202 sign_flag = 0; /* Reset sign_flag. */
1203 trace_output_void (sd);
1204 }
1205
1206 /* beq0w. */
1207 void
1208 OP_E_8 (SIM_DESC sd, SIM_CPU *cpu)
1209 {
1210 uint32 addr;
1211 uint16 a = GPR (OP[0]);
1212 trace_input ("beq0w", OP_REG, OP_DISP5, OP_VOID);
1213 addr = OP[1];
1214 if (a == 0)
1215 {
1216 if (sign_flag)
1217 addr = (PC - OP[1]);
1218 else
1219 addr = (PC + OP[1]);
1220
1221 JMP (addr);
1222 }
1223 sign_flag = 0; /* Reset sign_flag. */
1224 trace_output_void (sd);
1225 }
1226
1227 /* bne0w. */
1228 void
1229 OP_F_8 (SIM_DESC sd, SIM_CPU *cpu)
1230 {
1231 uint32 addr;
1232 uint16 a = GPR (OP[0]);
1233 trace_input ("bne0w", OP_REG, OP_DISP5, OP_VOID);
1234 addr = OP[1];
1235 if (a != 0)
1236 {
1237 if (sign_flag)
1238 addr = (PC - OP[1]);
1239 else
1240 addr = (PC + OP[1]);
1241
1242 JMP (addr);
1243 }
1244 sign_flag = 0; /* Reset sign_flag. */
1245 trace_output_void (sd);
1246 }
1247
1248
1249 /* jeq. */
1250 void
1251 OP_A0_C (SIM_DESC sd, SIM_CPU *cpu)
1252 {
1253 uint32 tmp = 0;
1254 trace_input ("jeq", OP_REGP, OP_VOID, OP_VOID);
1255 if ((PSR_Z) == 1)
1256 {
1257 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */
1258 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */
1259 }
1260 trace_output_32 (sd, tmp);
1261 }
1262
1263 /* jne. */
1264 void
1265 OP_A1_C (SIM_DESC sd, SIM_CPU *cpu)
1266 {
1267 uint32 tmp = 0;
1268 trace_input ("jne", OP_REGP, OP_VOID, OP_VOID);
1269 if ((PSR_Z) == 0)
1270 {
1271 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */
1272 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */
1273 }
1274 trace_output_32 (sd, tmp);
1275 }
1276
1277 /* jcs. */
1278 void
1279 OP_A2_C (SIM_DESC sd, SIM_CPU *cpu)
1280 {
1281 uint32 tmp = 0;
1282 trace_input ("jcs", OP_REGP, OP_VOID, OP_VOID);
1283 if ((PSR_C) == 1)
1284 {
1285 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1286 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1287 }
1288 trace_output_32 (sd, tmp);
1289 }
1290
1291 /* jcc. */
1292 void
1293 OP_A3_C (SIM_DESC sd, SIM_CPU *cpu)
1294 {
1295 uint32 tmp = 0;
1296 trace_input ("jcc", OP_REGP, OP_VOID, OP_VOID);
1297 if ((PSR_C) == 0)
1298 {
1299 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1300 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1301 }
1302 trace_output_32 (sd, tmp);
1303 }
1304
1305 /* jhi. */
1306 void
1307 OP_A4_C (SIM_DESC sd, SIM_CPU *cpu)
1308 {
1309 uint32 tmp = 0;
1310 trace_input ("jhi", OP_REGP, OP_VOID, OP_VOID);
1311 if ((PSR_L) == 1)
1312 {
1313 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1314 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1315 }
1316 trace_output_32 (sd, tmp);
1317 }
1318
1319 /* jls. */
1320 void
1321 OP_A5_C (SIM_DESC sd, SIM_CPU *cpu)
1322 {
1323 uint32 tmp = 0;
1324 trace_input ("jls", OP_REGP, OP_VOID, OP_VOID);
1325 if ((PSR_L) == 0)
1326 {
1327 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1328 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1329 }
1330 trace_output_32 (sd, tmp);
1331 }
1332
1333 /* jgt. */
1334 void
1335 OP_A6_C (SIM_DESC sd, SIM_CPU *cpu)
1336 {
1337 uint32 tmp = 0;
1338 trace_input ("jgt", OP_REGP, OP_VOID, OP_VOID);
1339 if ((PSR_N) == 1)
1340 {
1341 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1342 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1343 }
1344 trace_output_32 (sd, tmp);
1345 }
1346
1347 /* jle. */
1348 void
1349 OP_A7_C (SIM_DESC sd, SIM_CPU *cpu)
1350 {
1351 uint32 tmp = 0;
1352 trace_input ("jle", OP_REGP, OP_VOID, OP_VOID);
1353 if ((PSR_N) == 0)
1354 {
1355 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1356 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1357 }
1358 trace_output_32 (sd, tmp);
1359 }
1360
1361
1362 /* jfs. */
1363 void
1364 OP_A8_C (SIM_DESC sd, SIM_CPU *cpu)
1365 {
1366 uint32 tmp = 0;
1367 trace_input ("jfs", OP_REGP, OP_VOID, OP_VOID);
1368 if ((PSR_F) == 1)
1369 {
1370 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1371 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1372 }
1373 trace_output_32 (sd, tmp);
1374 }
1375
1376 /* jfc. */
1377 void
1378 OP_A9_C (SIM_DESC sd, SIM_CPU *cpu)
1379 {
1380 uint32 tmp = 0;
1381 trace_input ("jfc", OP_REGP, OP_VOID, OP_VOID);
1382 if ((PSR_F) == 0)
1383 {
1384 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1385 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1386 }
1387 trace_output_32 (sd, tmp);
1388 }
1389
1390 /* jlo. */
1391 void
1392 OP_AA_C (SIM_DESC sd, SIM_CPU *cpu)
1393 {
1394 uint32 tmp = 0;
1395 trace_input ("jlo", OP_REGP, OP_VOID, OP_VOID);
1396 if (((PSR_Z) == 0) & ((PSR_L) == 0))
1397 {
1398 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1399 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1400 }
1401 trace_output_32 (sd, tmp);
1402 }
1403
1404 /* jhs. */
1405 void
1406 OP_AB_C (SIM_DESC sd, SIM_CPU *cpu)
1407 {
1408 uint32 tmp = 0;
1409 trace_input ("jhs", OP_REGP, OP_VOID, OP_VOID);
1410 if (((PSR_Z) == 1) | ((PSR_L) == 1))
1411 {
1412 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1413 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1414 }
1415 trace_output_32 (sd, tmp);
1416 }
1417
1418 /* jlt. */
1419 void
1420 OP_AC_C (SIM_DESC sd, SIM_CPU *cpu)
1421 {
1422 uint32 tmp = 0;
1423 trace_input ("jlt", OP_REGP, OP_VOID, OP_VOID);
1424 if (((PSR_Z) == 0) & ((PSR_N) == 0))
1425 {
1426 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1427 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1428 }
1429 trace_output_32 (sd, tmp);
1430 }
1431
1432 /* jge. */
1433 void
1434 OP_AD_C (SIM_DESC sd, SIM_CPU *cpu)
1435 {
1436 uint32 tmp = 0;
1437 trace_input ("jge", OP_REGP, OP_VOID, OP_VOID);
1438 if (((PSR_Z) == 1) | ((PSR_N) == 1))
1439 {
1440 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1441 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1442 }
1443 trace_output_32 (sd, tmp);
1444 }
1445
1446 /* jump. */
1447 void
1448 OP_AE_C (SIM_DESC sd, SIM_CPU *cpu)
1449 {
1450 uint32 tmp;
1451 trace_input ("jump", OP_REGP, OP_VOID, OP_VOID);
1452 tmp = GPR32 (OP[0]) /*& 0x3fffff*/; /* Use only 0 - 22 bits */
1453 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1454 trace_output_32 (sd, tmp);
1455 }
1456
1457 /* jusr. */
1458 void
1459 OP_AF_C (SIM_DESC sd, SIM_CPU *cpu)
1460 {
1461 uint32 tmp;
1462 trace_input ("jusr", OP_REGP, OP_VOID, OP_VOID);
1463 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */
1464 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/
1465 SET_PSR_U(1);
1466 trace_output_32 (sd, tmp);
1467 }
1468
1469 /* seq. */
1470 void
1471 OP_80_C (SIM_DESC sd, SIM_CPU *cpu)
1472 {
1473 trace_input ("seq", OP_REG, OP_VOID, OP_VOID);
1474 if ((PSR_Z) == 1)
1475 SET_GPR (OP[0], 1);
1476 else
1477 SET_GPR (OP[0], 0);
1478 trace_output_void (sd);
1479 }
1480 /* sne. */
1481 void
1482 OP_81_C (SIM_DESC sd, SIM_CPU *cpu)
1483 {
1484 trace_input ("sne", OP_REG, OP_VOID, OP_VOID);
1485 if ((PSR_Z) == 0)
1486 SET_GPR (OP[0], 1);
1487 else
1488 SET_GPR (OP[0], 0);
1489 trace_output_void (sd);
1490 }
1491
1492 /* scs. */
1493 void
1494 OP_82_C (SIM_DESC sd, SIM_CPU *cpu)
1495 {
1496 trace_input ("scs", OP_REG, OP_VOID, OP_VOID);
1497 if ((PSR_C) == 1)
1498 SET_GPR (OP[0], 1);
1499 else
1500 SET_GPR (OP[0], 0);
1501 trace_output_void (sd);
1502 }
1503
1504 /* scc. */
1505 void
1506 OP_83_C (SIM_DESC sd, SIM_CPU *cpu)
1507 {
1508 trace_input ("scc", OP_REG, OP_VOID, OP_VOID);
1509 if ((PSR_C) == 0)
1510 SET_GPR (OP[0], 1);
1511 else
1512 SET_GPR (OP[0], 0);
1513 trace_output_void (sd);
1514 }
1515
1516 /* shi. */
1517 void
1518 OP_84_C (SIM_DESC sd, SIM_CPU *cpu)
1519 {
1520 trace_input ("shi", OP_REG, OP_VOID, OP_VOID);
1521 if ((PSR_L) == 1)
1522 SET_GPR (OP[0], 1);
1523 else
1524 SET_GPR (OP[0], 0);
1525 trace_output_void (sd);
1526 }
1527
1528 /* sls. */
1529 void
1530 OP_85_C (SIM_DESC sd, SIM_CPU *cpu)
1531 {
1532 trace_input ("sls", OP_REG, OP_VOID, OP_VOID);
1533 if ((PSR_L) == 0)
1534 SET_GPR (OP[0], 1);
1535 else
1536 SET_GPR (OP[0], 0);
1537 trace_output_void (sd);
1538 }
1539
1540 /* sgt. */
1541 void
1542 OP_86_C (SIM_DESC sd, SIM_CPU *cpu)
1543 {
1544 trace_input ("sgt", OP_REG, OP_VOID, OP_VOID);
1545 if ((PSR_N) == 1)
1546 SET_GPR (OP[0], 1);
1547 else
1548 SET_GPR (OP[0], 0);
1549 trace_output_void (sd);
1550 }
1551
1552 /* sle. */
1553 void
1554 OP_87_C (SIM_DESC sd, SIM_CPU *cpu)
1555 {
1556 trace_input ("sle", OP_REG, OP_VOID, OP_VOID);
1557 if ((PSR_N) == 0)
1558 SET_GPR (OP[0], 1);
1559 else
1560 SET_GPR (OP[0], 0);
1561 trace_output_void (sd);
1562 }
1563
1564 /* sfs. */
1565 void
1566 OP_88_C (SIM_DESC sd, SIM_CPU *cpu)
1567 {
1568 trace_input ("sfs", OP_REG, OP_VOID, OP_VOID);
1569 if ((PSR_F) == 1)
1570 SET_GPR (OP[0], 1);
1571 else
1572 SET_GPR (OP[0], 0);
1573 trace_output_void (sd);
1574 }
1575
1576 /* sfc. */
1577 void
1578 OP_89_C (SIM_DESC sd, SIM_CPU *cpu)
1579 {
1580 trace_input ("sfc", OP_REG, OP_VOID, OP_VOID);
1581 if ((PSR_F) == 0)
1582 SET_GPR (OP[0], 1);
1583 else
1584 SET_GPR (OP[0], 0);
1585 trace_output_void (sd);
1586 }
1587
1588
1589 /* slo. */
1590 void
1591 OP_8A_C (SIM_DESC sd, SIM_CPU *cpu)
1592 {
1593 trace_input ("slo", OP_REG, OP_VOID, OP_VOID);
1594 if (((PSR_Z) == 0) & ((PSR_L) == 0))
1595 SET_GPR (OP[0], 1);
1596 else
1597 SET_GPR (OP[0], 0);
1598 trace_output_void (sd);
1599 }
1600
1601 /* shs. */
1602 void
1603 OP_8B_C (SIM_DESC sd, SIM_CPU *cpu)
1604 {
1605 trace_input ("shs", OP_REG, OP_VOID, OP_VOID);
1606 if ( ((PSR_Z) == 1) | ((PSR_L) == 1))
1607 SET_GPR (OP[0], 1);
1608 else
1609 SET_GPR (OP[0], 0);
1610 trace_output_void (sd);
1611 }
1612
1613 /* slt. */
1614 void
1615 OP_8C_C (SIM_DESC sd, SIM_CPU *cpu)
1616 {
1617 trace_input ("slt", OP_REG, OP_VOID, OP_VOID);
1618 if (((PSR_Z) == 0) & ((PSR_N) == 0))
1619 SET_GPR (OP[0], 1);
1620 else
1621 SET_GPR (OP[0], 0);
1622 trace_output_void (sd);
1623 }
1624
1625 /* sge. */
1626 void
1627 OP_8D_C (SIM_DESC sd, SIM_CPU *cpu)
1628 {
1629 trace_input ("sge", OP_REG, OP_VOID, OP_VOID);
1630 if (((PSR_Z) == 1) | ((PSR_N) == 1))
1631 SET_GPR (OP[0], 1);
1632 else
1633 SET_GPR (OP[0], 0);
1634 trace_output_void (sd);
1635 }
1636
1637 /* cbitb. */
1638 void
1639 OP_D7_9 (SIM_DESC sd, SIM_CPU *cpu)
1640 {
1641 uint8 a = OP[0] & 0xff;
1642 uint32 addr = OP[1], tmp;
1643 trace_input ("cbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1644 tmp = RB (addr);
1645 SET_PSR_F (tmp & (1 << a));
1646 tmp = tmp & ~(1 << a);
1647 SB (addr, tmp);
1648 trace_output_32 (sd, tmp);
1649 }
1650
1651 /* cbitb. */
1652 void
1653 OP_107_14 (SIM_DESC sd, SIM_CPU *cpu)
1654 {
1655 uint8 a = OP[0] & 0xff;
1656 uint32 addr = OP[1], tmp;
1657 trace_input ("cbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1658 tmp = RB (addr);
1659 SET_PSR_F (tmp & (1 << a));
1660 tmp = tmp & ~(1 << a);
1661 SB (addr, tmp);
1662 trace_output_32 (sd, tmp);
1663 }
1664
1665 /* cbitb. */
1666 void
1667 OP_68_8 (SIM_DESC sd, SIM_CPU *cpu)
1668 {
1669 uint8 a = (OP[0]) & 0xff;
1670 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1671 trace_input ("cbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
1672 tmp = RB (addr);
1673 SET_PSR_F (tmp & (1 << a));
1674 tmp = tmp & ~(1 << a);
1675 SB (addr, tmp);
1676 trace_output_32 (sd, addr);
1677 }
1678
1679 /* cbitb. */
1680 void
1681 OP_1AA_A (SIM_DESC sd, SIM_CPU *cpu)
1682 {
1683 uint8 a = (OP[0]) & 0xff;
1684 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1685 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1686 tmp = RB (addr);
1687 SET_PSR_F (tmp & (1 << a));
1688 tmp = tmp & ~(1 << a);
1689 SB (addr, tmp);
1690 trace_output_32 (sd, addr);
1691 }
1692
1693 /* cbitb. */
1694 void
1695 OP_104_14 (SIM_DESC sd, SIM_CPU *cpu)
1696 {
1697 uint8 a = (OP[0]) & 0xff;
1698 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1699 trace_input ("cbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1700 tmp = RB (addr);
1701 SET_PSR_F (tmp & (1 << a));
1702 tmp = tmp & ~(1 << a);
1703 SB (addr, tmp);
1704 trace_output_32 (sd, addr);
1705 }
1706
1707 /* cbitb. */
1708 void
1709 OP_D4_9 (SIM_DESC sd, SIM_CPU *cpu)
1710 {
1711 uint8 a = (OP[0]) & 0xff;
1712 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1713 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1714 tmp = RB (addr);
1715 SET_PSR_F (tmp & (1 << a));
1716 tmp = tmp & ~(1 << a);
1717 SB (addr, tmp);
1718 trace_output_32 (sd, addr);
1719 }
1720
1721 /* cbitb. */
1722 void
1723 OP_D6_9 (SIM_DESC sd, SIM_CPU *cpu)
1724 {
1725 uint8 a = (OP[0]) & 0xff;
1726 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1727 trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
1728 tmp = RB (addr);
1729 SET_PSR_F (tmp & (1 << a));
1730 tmp = tmp & ~(1 << a);
1731 SB (addr, tmp);
1732 trace_output_32 (sd, addr);
1733
1734 }
1735
1736 /* cbitb. */
1737 void
1738 OP_105_14 (SIM_DESC sd, SIM_CPU *cpu)
1739 {
1740 uint8 a = (OP[0]) & 0xff;
1741 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1742 trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
1743 tmp = RB (addr);
1744 SET_PSR_F (tmp & (1 << a));
1745 tmp = tmp & ~(1 << a);
1746 SB (addr, tmp);
1747 trace_output_32 (sd, addr);
1748 }
1749
1750 /* cbitb. */
1751 void
1752 OP_106_14 (SIM_DESC sd, SIM_CPU *cpu)
1753 {
1754 uint8 a = (OP[0]) & 0xff;
1755 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1756 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
1757 tmp = RB (addr);
1758 SET_PSR_F (tmp & (1 << a));
1759 tmp = tmp & ~(1 << a);
1760 SB (addr, tmp);
1761 trace_output_32 (sd, addr);
1762 }
1763
1764
1765 /* cbitw. */
1766 void
1767 OP_6F_8 (SIM_DESC sd, SIM_CPU *cpu)
1768 {
1769 uint16 a = OP[0];
1770 uint32 addr = OP[1], tmp;
1771 trace_input ("cbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1772 tmp = RW (addr);
1773 SET_PSR_F (tmp & (1 << a));
1774 tmp = tmp & ~(1 << a);
1775 SW (addr, tmp);
1776 trace_output_32 (sd, tmp);
1777 }
1778
1779 /* cbitw. */
1780 void
1781 OP_117_14 (SIM_DESC sd, SIM_CPU *cpu)
1782 {
1783 uint16 a = OP[0];
1784 uint32 addr = OP[1], tmp;
1785 trace_input ("cbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1786 tmp = RW (addr);
1787 SET_PSR_F (tmp & (1 << a));
1788 tmp = tmp & ~(1 << a);
1789 SW (addr, tmp);
1790 trace_output_32 (sd, tmp);
1791 }
1792
1793 /* cbitw. */
1794 void
1795 OP_36_7 (SIM_DESC sd, SIM_CPU *cpu)
1796 {
1797 uint32 addr;
1798 uint16 a = (OP[0]), tmp;
1799 trace_input ("cbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
1800
1801 if (OP[1] == 0)
1802 addr = (GPR32 (12)) + OP[2];
1803 else
1804 addr = (GPR32 (13)) + OP[2];
1805
1806 tmp = RW (addr);
1807 SET_PSR_F (tmp & (1 << a));
1808 tmp = tmp & ~(1 << a);
1809 SW (addr, tmp);
1810 trace_output_32 (sd, addr);
1811
1812 }
1813
1814 /* cbitw. */
1815 void
1816 OP_1AB_A (SIM_DESC sd, SIM_CPU *cpu)
1817 {
1818 uint16 a = (OP[0]);
1819 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1820 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1821 tmp = RW (addr);
1822 SET_PSR_F (tmp & (1 << a));
1823 tmp = tmp & ~(1 << a);
1824 SW (addr, tmp);
1825 trace_output_32 (sd, addr);
1826 }
1827
1828 /* cbitw. */
1829 void
1830 OP_114_14 (SIM_DESC sd, SIM_CPU *cpu)
1831 {
1832 uint16 a = (OP[0]);
1833 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1834 trace_input ("cbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1835 tmp = RW (addr);
1836 SET_PSR_F (tmp & (1 << a));
1837 tmp = tmp & ~(1 << a);
1838 SW (addr, tmp);
1839 trace_output_32 (sd, addr);
1840 }
1841
1842
1843 /* cbitw. */
1844 void
1845 OP_6E_8 (SIM_DESC sd, SIM_CPU *cpu)
1846 {
1847 uint16 a = (OP[0]);
1848 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1849 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1850 tmp = RW (addr);
1851 SET_PSR_F (tmp & (1 << a));
1852 tmp = tmp & ~(1 << a);
1853 SW (addr, tmp);
1854 trace_output_32 (sd, addr);
1855 }
1856
1857 /* cbitw. */
1858 void
1859 OP_69_8 (SIM_DESC sd, SIM_CPU *cpu)
1860 {
1861 uint16 a = (OP[0]);
1862 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1863 trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
1864 tmp = RW (addr);
1865 SET_PSR_F (tmp & (1 << a));
1866 tmp = tmp & ~(1 << a);
1867 SW (addr, tmp);
1868 trace_output_32 (sd, addr);
1869 }
1870
1871
1872 /* cbitw. */
1873 void
1874 OP_115_14 (SIM_DESC sd, SIM_CPU *cpu)
1875 {
1876 uint16 a = (OP[0]);
1877 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1878 trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
1879 tmp = RW (addr);
1880 SET_PSR_F (tmp & (1 << a));
1881 tmp = tmp & ~(1 << a);
1882 SW (addr, tmp);
1883 trace_output_32 (sd, addr);
1884 }
1885
1886 /* cbitw. */
1887 void
1888 OP_116_14 (SIM_DESC sd, SIM_CPU *cpu)
1889 {
1890 uint16 a = (OP[0]);
1891 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1892 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
1893 tmp = RW (addr);
1894 SET_PSR_F (tmp & (1 << a));
1895 tmp = tmp & ~(1 << a);
1896 SW (addr, tmp);
1897 trace_output_32 (sd, addr);
1898 }
1899
1900 /* sbitb. */
1901 void
1902 OP_E7_9 (SIM_DESC sd, SIM_CPU *cpu)
1903 {
1904 uint8 a = OP[0] & 0xff;
1905 uint32 addr = OP[1], tmp;
1906 trace_input ("sbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
1907 tmp = RB (addr);
1908 SET_PSR_F (tmp & (1 << a));
1909 tmp = tmp | (1 << a);
1910 SB (addr, tmp);
1911 trace_output_32 (sd, tmp);
1912 }
1913
1914 /* sbitb. */
1915 void
1916 OP_10B_14 (SIM_DESC sd, SIM_CPU *cpu)
1917 {
1918 uint8 a = OP[0] & 0xff;
1919 uint32 addr = OP[1], tmp;
1920 trace_input ("sbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
1921 tmp = RB (addr);
1922 SET_PSR_F (tmp & (1 << a));
1923 tmp = tmp | (1 << a);
1924 SB (addr, tmp);
1925 trace_output_32 (sd, tmp);
1926 }
1927
1928 /* sbitb. */
1929 void
1930 OP_70_8 (SIM_DESC sd, SIM_CPU *cpu)
1931 {
1932 uint8 a = OP[0] & 0xff;
1933 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1934 trace_input ("sbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
1935 tmp = RB (addr);
1936 SET_PSR_F (tmp & (1 << a));
1937 tmp = tmp | (1 << a);
1938 SB (addr, tmp);
1939 trace_output_32 (sd, tmp);
1940 }
1941
1942 /* sbitb. */
1943 void
1944 OP_1CA_A (SIM_DESC sd, SIM_CPU *cpu)
1945 {
1946 uint8 a = OP[0] & 0xff;
1947 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1948 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
1949 tmp = RB (addr);
1950 SET_PSR_F (tmp & (1 << a));
1951 tmp = tmp | (1 << a);
1952 SB (addr, tmp);
1953 trace_output_32 (sd, tmp);
1954 }
1955
1956 /* sbitb. */
1957 void
1958 OP_108_14 (SIM_DESC sd, SIM_CPU *cpu)
1959 {
1960 uint8 a = OP[0] & 0xff;
1961 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
1962 trace_input ("sbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
1963 tmp = RB (addr);
1964 SET_PSR_F (tmp & (1 << a));
1965 tmp = tmp | (1 << a);
1966 SB (addr, tmp);
1967 trace_output_32 (sd, tmp);
1968 }
1969
1970
1971 /* sbitb. */
1972 void
1973 OP_E4_9 (SIM_DESC sd, SIM_CPU *cpu)
1974 {
1975 uint8 a = OP[0] & 0xff;
1976 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1977 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
1978 tmp = RB (addr);
1979 SET_PSR_F (tmp & (1 << a));
1980 tmp = tmp | (1 << a);
1981 SB (addr, tmp);
1982 trace_output_32 (sd, tmp);
1983 }
1984
1985 /* sbitb. */
1986 void
1987 OP_E6_9 (SIM_DESC sd, SIM_CPU *cpu)
1988 {
1989 uint8 a = OP[0] & 0xff;
1990 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
1991 trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
1992 tmp = RB (addr);
1993 SET_PSR_F (tmp & (1 << a));
1994 tmp = tmp | (1 << a);
1995 SB (addr, tmp);
1996 trace_output_32 (sd, tmp);
1997 }
1998
1999
2000 /* sbitb. */
2001 void
2002 OP_109_14 (SIM_DESC sd, SIM_CPU *cpu)
2003 {
2004 uint8 a = OP[0] & 0xff;
2005 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2006 trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2007 tmp = RB (addr);
2008 SET_PSR_F (tmp & (1 << a));
2009 tmp = tmp | (1 << a);
2010 SB (addr, tmp);
2011 trace_output_32 (sd, tmp);
2012 }
2013
2014
2015 /* sbitb. */
2016 void
2017 OP_10A_14 (SIM_DESC sd, SIM_CPU *cpu)
2018 {
2019 uint8 a = OP[0] & 0xff;
2020 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2021 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2022 tmp = RB (addr);
2023 SET_PSR_F (tmp & (1 << a));
2024 tmp = tmp | (1 << a);
2025 SB (addr, tmp);
2026 trace_output_32 (sd, tmp);
2027 }
2028
2029
2030 /* sbitw. */
2031 void
2032 OP_77_8 (SIM_DESC sd, SIM_CPU *cpu)
2033 {
2034 uint16 a = OP[0];
2035 uint32 addr = OP[1], tmp;
2036 trace_input ("sbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2037 tmp = RW (addr);
2038 SET_PSR_F (tmp & (1 << a));
2039 tmp = tmp | (1 << a);
2040 SW (addr, tmp);
2041 trace_output_32 (sd, tmp);
2042 }
2043
2044 /* sbitw. */
2045 void
2046 OP_11B_14 (SIM_DESC sd, SIM_CPU *cpu)
2047 {
2048 uint16 a = OP[0];
2049 uint32 addr = OP[1], tmp;
2050 trace_input ("sbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2051 tmp = RW (addr);
2052 SET_PSR_F (tmp & (1 << a));
2053 tmp = tmp | (1 << a);
2054 SW (addr, tmp);
2055 trace_output_32 (sd, tmp);
2056 }
2057
2058 /* sbitw. */
2059 void
2060 OP_3A_7 (SIM_DESC sd, SIM_CPU *cpu)
2061 {
2062 uint32 addr;
2063 uint16 a = (OP[0]), tmp;
2064 trace_input ("sbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
2065
2066 if (OP[1] == 0)
2067 addr = (GPR32 (12)) + OP[2];
2068 else
2069 addr = (GPR32 (13)) + OP[2];
2070
2071 tmp = RW (addr);
2072 SET_PSR_F (tmp & (1 << a));
2073 tmp = tmp | (1 << a);
2074 SW (addr, tmp);
2075 trace_output_32 (sd, addr);
2076 }
2077
2078 /* sbitw. */
2079 void
2080 OP_1CB_A (SIM_DESC sd, SIM_CPU *cpu)
2081 {
2082 uint16 a = (OP[0]);
2083 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2084 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2085 tmp = RW (addr);
2086 SET_PSR_F (tmp & (1 << a));
2087 tmp = tmp | (1 << a);
2088 SW (addr, tmp);
2089 trace_output_32 (sd, addr);
2090 }
2091
2092 /* sbitw. */
2093 void
2094 OP_118_14 (SIM_DESC sd, SIM_CPU *cpu)
2095 {
2096 uint16 a = (OP[0]);
2097 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2098 trace_input ("sbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2099 tmp = RW (addr);
2100 SET_PSR_F (tmp & (1 << a));
2101 tmp = tmp | (1 << a);
2102 SW (addr, tmp);
2103 trace_output_32 (sd, addr);
2104 }
2105
2106 /* sbitw. */
2107 void
2108 OP_76_8 (SIM_DESC sd, SIM_CPU *cpu)
2109 {
2110 uint16 a = (OP[0]);
2111 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2112 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2113 tmp = RW (addr);
2114 SET_PSR_F (tmp & (1 << a));
2115 tmp = tmp | (1 << a);
2116 SW (addr, tmp);
2117 trace_output_32 (sd, addr);
2118 }
2119
2120 /* sbitw. */
2121 void
2122 OP_71_8 (SIM_DESC sd, SIM_CPU *cpu)
2123 {
2124 uint16 a = (OP[0]);
2125 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2126 trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2127 tmp = RW (addr);
2128 SET_PSR_F (tmp & (1 << a));
2129 tmp = tmp | (1 << a);
2130 SW (addr, tmp);
2131 trace_output_32 (sd, addr);
2132 }
2133
2134 /* sbitw. */
2135 void
2136 OP_119_14 (SIM_DESC sd, SIM_CPU *cpu)
2137 {
2138 uint16 a = (OP[0]);
2139 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2140 trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2141 tmp = RW (addr);
2142 SET_PSR_F (tmp & (1 << a));
2143 tmp = tmp | (1 << a);
2144 SW (addr, tmp);
2145 trace_output_32 (sd, addr);
2146 }
2147
2148 /* sbitw. */
2149 void
2150 OP_11A_14 (SIM_DESC sd, SIM_CPU *cpu)
2151 {
2152 uint16 a = (OP[0]);
2153 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2154 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2155 tmp = RW (addr);
2156 SET_PSR_F (tmp & (1 << a));
2157 tmp = tmp | (1 << a);
2158 SW (addr, tmp);
2159 trace_output_32 (sd, addr);
2160 }
2161
2162
2163 /* tbitb. */
2164 void
2165 OP_F7_9 (SIM_DESC sd, SIM_CPU *cpu)
2166 {
2167 uint8 a = OP[0] & 0xff;
2168 uint32 addr = OP[1], tmp;
2169 trace_input ("tbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2170 tmp = RB (addr);
2171 SET_PSR_F (tmp & (1 << a));
2172 trace_output_32 (sd, tmp);
2173 }
2174
2175 /* tbitb. */
2176 void
2177 OP_10F_14 (SIM_DESC sd, SIM_CPU *cpu)
2178 {
2179 uint8 a = OP[0] & 0xff;
2180 uint32 addr = OP[1], tmp;
2181 trace_input ("tbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2182 tmp = RB (addr);
2183 SET_PSR_F (tmp & (1 << a));
2184 trace_output_32 (sd, tmp);
2185 }
2186
2187 /* tbitb. */
2188 void
2189 OP_78_8 (SIM_DESC sd, SIM_CPU *cpu)
2190 {
2191 uint8 a = (OP[0]) & 0xff;
2192 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2193 trace_input ("tbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID);
2194 tmp = RB (addr);
2195 SET_PSR_F (tmp & (1 << a));
2196 trace_output_32 (sd, addr);
2197 }
2198
2199 /* tbitb. */
2200 void
2201 OP_1EA_A (SIM_DESC sd, SIM_CPU *cpu)
2202 {
2203 uint8 a = (OP[0]) & 0xff;
2204 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2205 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2206 tmp = RB (addr);
2207 SET_PSR_F (tmp & (1 << a));
2208 trace_output_32 (sd, addr);
2209 }
2210
2211 /* tbitb. */
2212 void
2213 OP_10C_14 (SIM_DESC sd, SIM_CPU *cpu)
2214 {
2215 uint8 a = (OP[0]) & 0xff;
2216 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2217 trace_input ("tbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2218 tmp = RB (addr);
2219 SET_PSR_F (tmp & (1 << a));
2220 trace_output_32 (sd, addr);
2221 }
2222
2223 /* tbitb. */
2224 void
2225 OP_F4_9 (SIM_DESC sd, SIM_CPU *cpu)
2226 {
2227 uint8 a = (OP[0]) & 0xff;
2228 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2229 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2230 tmp = RB (addr);
2231 SET_PSR_F (tmp & (1 << a));
2232 trace_output_32 (sd, addr);
2233 }
2234
2235 /* tbitb. */
2236 void
2237 OP_F6_9 (SIM_DESC sd, SIM_CPU *cpu)
2238 {
2239 uint8 a = (OP[0]) & 0xff;
2240 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2241 trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2242 tmp = RB (addr);
2243 SET_PSR_F (tmp & (1 << a));
2244 trace_output_32 (sd, addr);
2245 }
2246
2247 /* tbitb. */
2248 void
2249 OP_10D_14 (SIM_DESC sd, SIM_CPU *cpu)
2250 {
2251 uint8 a = (OP[0]) & 0xff;
2252 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2253 trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2254 tmp = RB (addr);
2255 SET_PSR_F (tmp & (1 << a));
2256 trace_output_32 (sd, addr);
2257 }
2258
2259 /* tbitb. */
2260 void
2261 OP_10E_14 (SIM_DESC sd, SIM_CPU *cpu)
2262 {
2263 uint8 a = (OP[0]) & 0xff;
2264 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2265 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2266 tmp = RB (addr);
2267 SET_PSR_F (tmp & (1 << a));
2268 trace_output_32 (sd, addr);
2269 }
2270
2271
2272 /* tbitw. */
2273 void
2274 OP_7F_8 (SIM_DESC sd, SIM_CPU *cpu)
2275 {
2276 uint16 a = OP[0];
2277 uint32 addr = OP[1], tmp;
2278 trace_input ("tbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
2279 tmp = RW (addr);
2280 SET_PSR_F (tmp & (1 << a));
2281 trace_output_32 (sd, tmp);
2282 }
2283
2284 /* tbitw. */
2285 void
2286 OP_11F_14 (SIM_DESC sd, SIM_CPU *cpu)
2287 {
2288 uint16 a = OP[0];
2289 uint32 addr = OP[1], tmp;
2290 trace_input ("tbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
2291 tmp = RW (addr);
2292 SET_PSR_F (tmp & (1 << a));
2293 trace_output_32 (sd, tmp);
2294 }
2295
2296
2297 /* tbitw. */
2298 void
2299 OP_3E_7 (SIM_DESC sd, SIM_CPU *cpu)
2300 {
2301 uint32 addr;
2302 uint16 a = (OP[0]), tmp;
2303 trace_input ("tbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
2304
2305 if (OP[1] == 0)
2306 addr = (GPR32 (12)) + OP[2];
2307 else
2308 addr = (GPR32 (13)) + OP[2];
2309
2310 tmp = RW (addr);
2311 SET_PSR_F (tmp & (1 << a));
2312 trace_output_32 (sd, addr);
2313 }
2314
2315 /* tbitw. */
2316 void
2317 OP_1EB_A (SIM_DESC sd, SIM_CPU *cpu)
2318 {
2319 uint16 a = (OP[0]);
2320 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2321 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID);
2322 tmp = RW (addr);
2323 SET_PSR_F (tmp & (1 << a));
2324 trace_output_32 (sd, addr);
2325 }
2326
2327 /* tbitw. */
2328 void
2329 OP_11C_14 (SIM_DESC sd, SIM_CPU *cpu)
2330 {
2331 uint16 a = (OP[0]);
2332 uint32 addr = (GPR (OP[2])) + OP[1], tmp;
2333 trace_input ("tbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
2334 tmp = RW (addr);
2335 SET_PSR_F (tmp & (1 << a));
2336 trace_output_32 (sd, addr);
2337 }
2338
2339 /* tbitw. */
2340 void
2341 OP_7E_8 (SIM_DESC sd, SIM_CPU *cpu)
2342 {
2343 uint16 a = (OP[0]);
2344 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2345 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
2346 tmp = RW (addr);
2347 SET_PSR_F (tmp & (1 << a));
2348 trace_output_32 (sd, addr);
2349 }
2350
2351 /* tbitw. */
2352 void
2353 OP_79_8 (SIM_DESC sd, SIM_CPU *cpu)
2354 {
2355 uint16 a = (OP[0]);
2356 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2357 trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
2358 tmp = RW (addr);
2359 SET_PSR_F (tmp & (1 << a));
2360 trace_output_32 (sd, addr);
2361 }
2362
2363 /* tbitw. */
2364 void
2365 OP_11D_14 (SIM_DESC sd, SIM_CPU *cpu)
2366 {
2367 uint16 a = (OP[0]);
2368 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2369 trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
2370 tmp = RW (addr);
2371 SET_PSR_F (tmp & (1 << a));
2372 trace_output_32 (sd, addr);
2373 }
2374
2375
2376 /* tbitw. */
2377 void
2378 OP_11E_14 (SIM_DESC sd, SIM_CPU *cpu)
2379 {
2380 uint16 a = (OP[0]);
2381 uint32 addr = (GPR32 (OP[2])) + OP[1], tmp;
2382 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
2383 tmp = RW (addr);
2384 SET_PSR_F (tmp & (1 << a));
2385 trace_output_32 (sd, addr);
2386 }
2387
2388
2389 /* tbit. */
2390 void
2391 OP_6_8 (SIM_DESC sd, SIM_CPU *cpu)
2392 {
2393 uint16 a = OP[0];
2394 uint16 b = (GPR (OP[1]));
2395 trace_input ("tbit", OP_CONSTANT4, OP_REG, OP_VOID);
2396 SET_PSR_F (b & (1 << a));
2397 trace_output_16 (sd, b);
2398 }
2399
2400 /* tbit. */
2401 void
2402 OP_7_8 (SIM_DESC sd, SIM_CPU *cpu)
2403 {
2404 uint16 a = GPR (OP[0]);
2405 uint16 b = (GPR (OP[1]));
2406 trace_input ("tbit", OP_REG, OP_REG, OP_VOID);
2407 SET_PSR_F (b & (1 << a));
2408 trace_output_16 (sd, b);
2409 }
2410
2411
2412 /* cmpb. */
2413 void
2414 OP_50_8 (SIM_DESC sd, SIM_CPU *cpu)
2415 {
2416 uint8 a = (OP[0]) & 0xFF;
2417 uint8 b = (GPR (OP[1])) & 0xFF;
2418 trace_input ("cmpb", OP_CONSTANT4, OP_REG, OP_VOID);
2419 SET_PSR_Z (a == b);
2420 SET_PSR_N ((int8)a > (int8)b);
2421 SET_PSR_L (a > b);
2422 trace_output_flag (sd);
2423 }
2424
2425 /* cmpb. */
2426 void
2427 OP_50B_C (SIM_DESC sd, SIM_CPU *cpu)
2428 {
2429 uint8 a = (OP[0]) & 0xFF;
2430 uint8 b = (GPR (OP[1])) & 0xFF;
2431 trace_input ("cmpb", OP_CONSTANT16, OP_REG, OP_VOID);
2432 SET_PSR_Z (a == b);
2433 SET_PSR_N ((int8)a > (int8)b);
2434 SET_PSR_L (a > b);
2435 trace_output_flag (sd);
2436 }
2437
2438 /* cmpb. */
2439 void
2440 OP_51_8 (SIM_DESC sd, SIM_CPU *cpu)
2441 {
2442 uint8 a = (GPR (OP[0])) & 0xFF;
2443 uint8 b = (GPR (OP[1])) & 0xFF;
2444 trace_input ("cmpb", OP_REG, OP_REG, OP_VOID);
2445 SET_PSR_Z (a == b);
2446 SET_PSR_N ((int8)a > (int8)b);
2447 SET_PSR_L (a > b);
2448 trace_output_flag (sd);
2449 }
2450
2451 /* cmpw. */
2452 void
2453 OP_52_8 (SIM_DESC sd, SIM_CPU *cpu)
2454 {
2455 uint16 a = (OP[0]);
2456 uint16 b = GPR (OP[1]);
2457 trace_input ("cmpw", OP_CONSTANT4, OP_REG, OP_VOID);
2458 SET_PSR_Z (a == b);
2459 SET_PSR_N ((int16)a > (int16)b);
2460 SET_PSR_L (a > b);
2461 trace_output_flag (sd);
2462 }
2463
2464 /* cmpw. */
2465 void
2466 OP_52B_C (SIM_DESC sd, SIM_CPU *cpu)
2467 {
2468 uint16 a = (OP[0]);
2469 uint16 b = GPR (OP[1]);
2470 trace_input ("cmpw", OP_CONSTANT16, OP_REG, OP_VOID);
2471 SET_PSR_Z (a == b);
2472 SET_PSR_N ((int16)a > (int16)b);
2473 SET_PSR_L (a > b);
2474 trace_output_flag (sd);
2475 }
2476
2477 /* cmpw. */
2478 void
2479 OP_53_8 (SIM_DESC sd, SIM_CPU *cpu)
2480 {
2481 uint16 a = GPR (OP[0]) ;
2482 uint16 b = GPR (OP[1]) ;
2483 trace_input ("cmpw", OP_REG, OP_REG, OP_VOID);
2484 SET_PSR_Z (a == b);
2485 SET_PSR_N ((int16)a > (int16)b);
2486 SET_PSR_L (a > b);
2487 trace_output_flag (sd);
2488 }
2489
2490 /* cmpd. */
2491 void
2492 OP_56_8 (SIM_DESC sd, SIM_CPU *cpu)
2493 {
2494 uint32 a = (OP[0]);
2495 uint32 b = GPR32 (OP[1]);
2496 trace_input ("cmpd", OP_CONSTANT4, OP_REGP, OP_VOID);
2497 SET_PSR_Z (a == b);
2498 SET_PSR_N ((int32)a > (int32)b);
2499 SET_PSR_L (a > b);
2500 trace_output_flag (sd);
2501 }
2502
2503 /* cmpd. */
2504 void
2505 OP_56B_C (SIM_DESC sd, SIM_CPU *cpu)
2506 {
2507 uint32 a = (SEXT16(OP[0]));
2508 uint32 b = GPR32 (OP[1]);
2509 trace_input ("cmpd", OP_CONSTANT16, OP_REGP, OP_VOID);
2510 SET_PSR_Z (a == b);
2511 SET_PSR_N ((int32)a > (int32)b);
2512 SET_PSR_L (a > b);
2513 trace_output_flag (sd);
2514 }
2515
2516 /* cmpd. */
2517 void
2518 OP_57_8 (SIM_DESC sd, SIM_CPU *cpu)
2519 {
2520 uint32 a = GPR32 (OP[0]) ;
2521 uint32 b = GPR32 (OP[1]) ;
2522 trace_input ("cmpd", OP_REGP, OP_REGP, OP_VOID);
2523 SET_PSR_Z (a == b);
2524 SET_PSR_N ((int32)a > (int32)b);
2525 SET_PSR_L (a > b);
2526 trace_output_flag (sd);
2527 }
2528
2529 /* cmpd. */
2530 void
2531 OP_9_C (SIM_DESC sd, SIM_CPU *cpu)
2532 {
2533 uint32 a = (OP[0]);
2534 uint32 b = GPR32 (OP[1]);
2535 trace_input ("cmpd", OP_CONSTANT32, OP_REGP, OP_VOID);
2536 SET_PSR_Z (a == b);
2537 SET_PSR_N ((int32)a > (int32)b);
2538 SET_PSR_L (a > b);
2539 trace_output_flag (sd);
2540 }
2541
2542
2543 /* movb. */
2544 void
2545 OP_58_8 (SIM_DESC sd, SIM_CPU *cpu)
2546 {
2547 uint8 tmp = OP[0] & 0xFF;
2548 uint16 a = (GPR (OP[1])) & 0xFF00;
2549 trace_input ("movb", OP_CONSTANT4, OP_REG, OP_VOID);
2550 SET_GPR (OP[1], (a | tmp));
2551 trace_output_16 (sd, tmp);
2552 }
2553
2554 /* movb. */
2555 void
2556 OP_58B_C (SIM_DESC sd, SIM_CPU *cpu)
2557 {
2558 uint8 tmp = OP[0] & 0xFF;
2559 uint16 a = (GPR (OP[1])) & 0xFF00;
2560 trace_input ("movb", OP_CONSTANT16, OP_REG, OP_VOID);
2561 SET_GPR (OP[1], (a | tmp));
2562 trace_output_16 (sd, tmp);
2563 }
2564
2565 /* movb. */
2566 void
2567 OP_59_8 (SIM_DESC sd, SIM_CPU *cpu)
2568 {
2569 uint8 tmp = (GPR (OP[0])) & 0xFF;
2570 uint16 a = (GPR (OP[1])) & 0xFF00;
2571 trace_input ("movb", OP_REG, OP_REG, OP_VOID);
2572 SET_GPR (OP[1], (a | tmp));
2573 trace_output_16 (sd, tmp);
2574 }
2575
2576 /* movw. */
2577 void
2578 OP_5A_8 (SIM_DESC sd, SIM_CPU *cpu)
2579 {
2580 uint16 tmp = OP[0];
2581 trace_input ("movw", OP_CONSTANT4_1, OP_REG, OP_VOID);
2582 SET_GPR (OP[1], (tmp & 0xffff));
2583 trace_output_16 (sd, tmp);
2584 }
2585
2586 /* movw. */
2587 void
2588 OP_5AB_C (SIM_DESC sd, SIM_CPU *cpu)
2589 {
2590 int16 tmp = OP[0];
2591 trace_input ("movw", OP_CONSTANT16, OP_REG, OP_VOID);
2592 SET_GPR (OP[1], (tmp & 0xffff));
2593 trace_output_16 (sd, tmp);
2594 }
2595
2596 /* movw. */
2597 void
2598 OP_5B_8 (SIM_DESC sd, SIM_CPU *cpu)
2599 {
2600 uint16 tmp = GPR (OP[0]);
2601 uint32 a = GPR32 (OP[1]);
2602 trace_input ("movw", OP_REG, OP_REGP, OP_VOID);
2603 a = (a & 0xffff0000) | tmp;
2604 SET_GPR32 (OP[1], a);
2605 trace_output_16 (sd, tmp);
2606 }
2607
2608 /* movxb. */
2609 void
2610 OP_5C_8 (SIM_DESC sd, SIM_CPU *cpu)
2611 {
2612 uint8 tmp = (GPR (OP[0])) & 0xFF;
2613 trace_input ("movxb", OP_REG, OP_REG, OP_VOID);
2614 SET_GPR (OP[1], ((SEXT8(tmp)) & 0xffff));
2615 trace_output_16 (sd, tmp);
2616 }
2617
2618 /* movzb. */
2619 void
2620 OP_5D_8 (SIM_DESC sd, SIM_CPU *cpu)
2621 {
2622 uint8 tmp = (GPR (OP[0])) & 0xFF;
2623 trace_input ("movzb", OP_REG, OP_REG, OP_VOID);
2624 SET_GPR (OP[1], tmp);
2625 trace_output_16 (sd, tmp);
2626 }
2627
2628 /* movxw. */
2629 void
2630 OP_5E_8 (SIM_DESC sd, SIM_CPU *cpu)
2631 {
2632 uint16 tmp = GPR (OP[0]);
2633 trace_input ("movxw", OP_REG, OP_REGP, OP_VOID);
2634 SET_GPR32 (OP[1], SEXT16(tmp));
2635 trace_output_16 (sd, tmp);
2636 }
2637
2638 /* movzw. */
2639 void
2640 OP_5F_8 (SIM_DESC sd, SIM_CPU *cpu)
2641 {
2642 uint16 tmp = GPR (OP[0]);
2643 trace_input ("movzw", OP_REG, OP_REGP, OP_VOID);
2644 SET_GPR32 (OP[1], (tmp & 0x0000FFFF));
2645 trace_output_16 (sd, tmp);
2646 }
2647
2648 /* movd. */
2649 void
2650 OP_54_8 (SIM_DESC sd, SIM_CPU *cpu)
2651 {
2652 int32 tmp = OP[0];
2653 trace_input ("movd", OP_CONSTANT4, OP_REGP, OP_VOID);
2654 SET_GPR32 (OP[1], tmp);
2655 trace_output_32 (sd, tmp);
2656 }
2657
2658 /* movd. */
2659 void
2660 OP_54B_C (SIM_DESC sd, SIM_CPU *cpu)
2661 {
2662 int32 tmp = SEXT16(OP[0]);
2663 trace_input ("movd", OP_CONSTANT16, OP_REGP, OP_VOID);
2664 SET_GPR32 (OP[1], tmp);
2665 trace_output_32 (sd, tmp);
2666 }
2667
2668 /* movd. */
2669 void
2670 OP_55_8 (SIM_DESC sd, SIM_CPU *cpu)
2671 {
2672 uint32 tmp = GPR32 (OP[0]);
2673 trace_input ("movd", OP_REGP, OP_REGP, OP_VOID);
2674 SET_GPR32 (OP[1], tmp);
2675 trace_output_32 (sd, tmp);
2676 }
2677
2678 /* movd. */
2679 void
2680 OP_5_8 (SIM_DESC sd, SIM_CPU *cpu)
2681 {
2682 uint32 tmp = OP[0];
2683 trace_input ("movd", OP_CONSTANT20, OP_REGP, OP_VOID);
2684 SET_GPR32 (OP[1], tmp);
2685 trace_output_32 (sd, tmp);
2686 }
2687
2688 /* movd. */
2689 void
2690 OP_7_C (SIM_DESC sd, SIM_CPU *cpu)
2691 {
2692 int32 tmp = OP[0];
2693 trace_input ("movd", OP_CONSTANT32, OP_REGP, OP_VOID);
2694 SET_GPR32 (OP[1], tmp);
2695 trace_output_32 (sd, tmp);
2696 }
2697
2698 /* loadm. */
2699 void
2700 OP_14_D (SIM_DESC sd, SIM_CPU *cpu)
2701 {
2702 uint32 addr = GPR (0);
2703 uint16 count = OP[0], reg = 2, tmp;
2704 trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID);
2705 if ((addr & 1))
2706 {
2707 trace_output_void (sd);
2708 EXCEPTION (SIM_SIGBUS);
2709 }
2710
2711 while (count)
2712 {
2713 tmp = RW (addr);
2714 SET_GPR (reg, tmp);
2715 addr +=2;
2716 --count;
2717 reg++;
2718 if (reg == 6) reg = 8;
2719 };
2720
2721 SET_GPR (0, addr);
2722 trace_output_void (sd);
2723 }
2724
2725
2726 /* loadmp. */
2727 void
2728 OP_15_D (SIM_DESC sd, SIM_CPU *cpu)
2729 {
2730 uint32 addr = GPR32 (0);
2731 uint16 count = OP[0], reg = 2, tmp;
2732 trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID);
2733 if ((addr & 1))
2734 {
2735 trace_output_void (sd);
2736 EXCEPTION (SIM_SIGBUS);
2737 }
2738
2739 while (count)
2740 {
2741 tmp = RW (addr);
2742 SET_GPR (reg, tmp);
2743 addr +=2;
2744 --count;
2745 reg++;
2746 if (reg == 6) reg = 8;
2747 };
2748
2749 SET_GPR32 (0, addr);
2750 trace_output_void (sd);
2751 }
2752
2753
2754 /* loadb. */
2755 void
2756 OP_88_8 (SIM_DESC sd, SIM_CPU *cpu)
2757 {
2758 /* loadb ABS20, REG
2759 * ADDR = zext24(abs20) | remap (ie 0xF00000)
2760 * REG = [ADDR]
2761 * NOTE: remap is
2762 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
2763 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
2764 * by the core to 16M-64k to 16M. */
2765
2766 uint16 tmp, a = (GPR (OP[1])) & 0xFF00;
2767 uint32 addr = OP[0];
2768 trace_input ("loadb", OP_ABS20, OP_REG, OP_VOID);
2769 if (addr > 0xEFFFF) addr |= 0xF00000;
2770 tmp = (RB (addr));
2771 SET_GPR (OP[1], (a | tmp));
2772 trace_output_16 (sd, tmp);
2773 }
2774
2775 /* loadb. */
2776 void
2777 OP_127_14 (SIM_DESC sd, SIM_CPU *cpu)
2778 {
2779 /* loadb ABS24, REG
2780 * ADDR = abs24
2781 * REGR = [ADDR]. */
2782
2783 uint16 tmp, a = (GPR (OP[1])) & 0xFF00;
2784 uint32 addr = OP[0];
2785 trace_input ("loadb", OP_ABS24, OP_REG, OP_VOID);
2786 tmp = (RB (addr));
2787 SET_GPR (OP[1], (a | tmp));
2788 trace_output_16 (sd, tmp);
2789 }
2790
2791 /* loadb. */
2792 void
2793 OP_45_7 (SIM_DESC sd, SIM_CPU *cpu)
2794 {
2795 /* loadb [Rindex]ABS20 REG
2796 * ADDR = Rindex + zext24(disp20)
2797 * REGR = [ADDR]. */
2798
2799 uint32 addr;
2800 uint16 tmp, a = (GPR (OP[2])) & 0xFF00;
2801 trace_input ("loadb", OP_R_INDEX8_ABS20, OP_REG, OP_VOID);
2802
2803 if (OP[0] == 0)
2804 addr = (GPR32 (12)) + OP[1];
2805 else
2806 addr = (GPR32 (13)) + OP[1];
2807
2808 tmp = (RB (addr));
2809 SET_GPR (OP[2], (a | tmp));
2810 trace_output_16 (sd, tmp);
2811 }
2812
2813
2814 /* loadb. */
2815 void
2816 OP_B_4 (SIM_DESC sd, SIM_CPU *cpu)
2817 {
2818 /* loadb DIPS4(REGP) REG
2819 * ADDR = RPBASE + zext24(DISP4)
2820 * REG = [ADDR]. */
2821 uint16 tmp, a = (GPR (OP[2])) & 0xFF00;
2822 uint32 addr = (GPR32 (OP[1])) + OP[0];
2823 trace_input ("loadb", OP_RP_BASE_DISP4, OP_REG, OP_VOID);
2824 tmp = (RB (addr));
2825 SET_GPR (OP[2], (a | tmp));
2826 trace_output_16 (sd, tmp);
2827 }
2828
2829 /* loadb. */
2830 void
2831 OP_BE_8 (SIM_DESC sd, SIM_CPU *cpu)
2832 {
2833 /* loadb [Rindex]disp0(RPbasex) REG
2834 * ADDR = Rpbasex + Rindex
2835 * REGR = [ADDR] */
2836
2837 uint32 addr;
2838 uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
2839 trace_input ("loadb", OP_RP_INDEX_DISP0, OP_REG, OP_VOID);
2840
2841 addr = (GPR32 (OP[2])) + OP[1];
2842
2843 if (OP[0] == 0)
2844 addr = (GPR32 (12)) + addr;
2845 else
2846 addr = (GPR32 (13)) + addr;
2847
2848 tmp = (RB (addr));
2849 SET_GPR (OP[3], (a | tmp));
2850 trace_output_16 (sd, tmp);
2851 }
2852
2853 /* loadb. */
2854 void
2855 OP_219_A (SIM_DESC sd, SIM_CPU *cpu)
2856 {
2857 /* loadb [Rindex]disp14(RPbasex) REG
2858 * ADDR = Rpbasex + Rindex + zext24(disp14)
2859 * REGR = [ADDR] */
2860
2861 uint32 addr;
2862 uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
2863
2864 addr = (GPR32 (OP[2])) + OP[1];
2865
2866 if (OP[0] == 0)
2867 addr = (GPR32 (12)) + addr;
2868 else
2869 addr = (GPR32 (13)) + addr;
2870
2871 trace_input ("loadb", OP_RP_INDEX_DISP14, OP_REG, OP_VOID);
2872 tmp = (RB (addr));
2873 SET_GPR (OP[3], (a | tmp));
2874 trace_output_16 (sd, tmp);
2875 }
2876
2877
2878 /* loadb. */
2879 void
2880 OP_184_14 (SIM_DESC sd, SIM_CPU *cpu)
2881 {
2882 /* loadb DISPE20(REG) REG
2883 * zext24(Rbase) + zext24(dispe20)
2884 * REG = [ADDR] */
2885
2886 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2887 uint32 addr = OP[0] + (GPR (OP[1]));
2888 trace_input ("loadb", OP_R_BASE_DISPE20, OP_REG, OP_VOID);
2889 tmp = (RB (addr));
2890 SET_GPR (OP[2], (a | tmp));
2891 trace_output_16 (sd, tmp);
2892 }
2893
2894 /* loadb. */
2895 void
2896 OP_124_14 (SIM_DESC sd, SIM_CPU *cpu)
2897 {
2898 /* loadb DISP20(REG) REG
2899 * ADDR = zext24(Rbase) + zext24(disp20)
2900 * REG = [ADDR] */
2901
2902 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2903 uint32 addr = OP[0] + (GPR (OP[1]));
2904 trace_input ("loadb", OP_R_BASE_DISP20, OP_REG, OP_VOID);
2905 tmp = (RB (addr));
2906 SET_GPR (OP[2], (a | tmp));
2907 trace_output_16 (sd, tmp);
2908 }
2909
2910 /* loadb. */
2911 void
2912 OP_BF_8 (SIM_DESC sd, SIM_CPU *cpu)
2913 {
2914 /* loadb disp16(REGP) REG
2915 * ADDR = RPbase + zext24(disp16)
2916 * REGR = [ADDR] */
2917
2918 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2919 uint32 addr = (GPR32 (OP[1])) + OP[0];
2920 trace_input ("loadb", OP_RP_BASE_DISP16, OP_REG, OP_VOID);
2921 tmp = (RB (addr));
2922 SET_GPR (OP[2], (a | tmp));
2923 trace_output_16 (sd, tmp);
2924 }
2925
2926 /* loadb. */
2927 void
2928 OP_125_14 (SIM_DESC sd, SIM_CPU *cpu)
2929 {
2930 /* loadb disp20(REGP) REG
2931 * ADDR = RPbase + zext24(disp20)
2932 * REGR = [ADDR] */
2933 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2934 uint32 addr = (GPR32 (OP[1])) + OP[0];
2935 trace_input ("loadb", OP_RP_BASE_DISP20, OP_REG, OP_VOID);
2936 tmp = (RB (addr));
2937 SET_GPR (OP[2], (a | tmp));
2938 trace_output_16 (sd, tmp);
2939 }
2940
2941
2942 /* loadb. */
2943 void
2944 OP_185_14 (SIM_DESC sd, SIM_CPU *cpu)
2945 {
2946 /* loadb -disp20(REGP) REG
2947 * ADDR = RPbase + zext24(-disp20)
2948 * REGR = [ADDR] */
2949 uint16 tmp,a = (GPR (OP[2])) & 0xFF00;
2950 uint32 addr = (GPR32 (OP[1])) + OP[1];
2951 trace_input ("loadb", OP_RP_BASE_DISPE20, OP_REG, OP_VOID);
2952 tmp = (RB (addr));
2953 SET_GPR (OP[2], (a | tmp));
2954 trace_output_16 (sd, tmp);
2955 }
2956
2957 /* loadb. */
2958 void
2959 OP_126_14 (SIM_DESC sd, SIM_CPU *cpu)
2960 {
2961 /* loadb [Rindex]disp20(RPbasexb) REG
2962 * ADDR = RPbasex + Rindex + zext24(disp20)
2963 * REGR = [ADDR] */
2964
2965 uint32 addr;
2966 uint16 tmp, a = (GPR (OP[3])) & 0xFF00;
2967 trace_input ("loadb", OP_RP_INDEX_DISP20, OP_REG, OP_VOID);
2968
2969 addr = (GPR32 (OP[2])) + OP[1];
2970
2971 if (OP[0] == 0)
2972 addr = (GPR32 (12)) + addr;
2973 else
2974 addr = (GPR32 (13)) + addr;
2975
2976 tmp = (RB (addr));
2977 SET_GPR (OP[3], (a | tmp));
2978 trace_output_16 (sd, tmp);
2979 }
2980
2981
2982 /* loadw. */
2983 void
2984 OP_89_8 (SIM_DESC sd, SIM_CPU *cpu)
2985 {
2986 /* loadw ABS20, REG
2987 * ADDR = zext24(abs20) | remap
2988 * REGR = [ADDR]
2989 * NOTE: remap is
2990 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
2991 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
2992 * by the core to 16M-64k to 16M. */
2993
2994 uint16 tmp;
2995 uint32 addr = OP[0];
2996 trace_input ("loadw", OP_ABS20, OP_REG, OP_VOID);
2997 if (addr > 0xEFFFF) addr |= 0xF00000;
2998 tmp = (RW (addr));
2999 SET_GPR (OP[1], tmp);
3000 trace_output_16 (sd, tmp);
3001 }
3002
3003
3004 /* loadw. */
3005 void
3006 OP_12F_14 (SIM_DESC sd, SIM_CPU *cpu)
3007 {
3008 /* loadw ABS24, REG
3009 * ADDR = abs24
3010 * REGR = [ADDR] */
3011 uint16 tmp;
3012 uint32 addr = OP[0];
3013 trace_input ("loadw", OP_ABS24, OP_REG, OP_VOID);
3014 tmp = (RW (addr));
3015 SET_GPR (OP[1], tmp);
3016 trace_output_16 (sd, tmp);
3017 }
3018
3019 /* loadw. */
3020 void
3021 OP_47_7 (SIM_DESC sd, SIM_CPU *cpu)
3022 {
3023 /* loadw [Rindex]ABS20 REG
3024 * ADDR = Rindex + zext24(disp20)
3025 * REGR = [ADDR] */
3026
3027 uint32 addr;
3028 uint16 tmp;
3029 trace_input ("loadw", OP_R_INDEX8_ABS20, OP_REG, OP_VOID);
3030
3031 if (OP[0] == 0)
3032 addr = (GPR32 (12)) + OP[1];
3033 else
3034 addr = (GPR32 (13)) + OP[1];
3035
3036 tmp = (RW (addr));
3037 SET_GPR (OP[2], tmp);
3038 trace_output_16 (sd, tmp);
3039 }
3040
3041
3042 /* loadw. */
3043 void
3044 OP_9_4 (SIM_DESC sd, SIM_CPU *cpu)
3045 {
3046 /* loadw DIPS4(REGP) REGP
3047 * ADDR = RPBASE + zext24(DISP4)
3048 * REGP = [ADDR]. */
3049 uint16 tmp;
3050 uint32 addr, a;
3051 trace_input ("loadw", OP_RP_BASE_DISP4, OP_REG, OP_VOID);
3052 addr = (GPR32 (OP[1])) + OP[0];
3053 tmp = (RW (addr));
3054 if (OP[2] > 11)
3055 {
3056 a = (GPR32 (OP[2])) & 0xffff0000;
3057 SET_GPR32 (OP[2], (a | tmp));
3058 }
3059 else
3060 SET_GPR (OP[2], tmp);
3061
3062 trace_output_16 (sd, tmp);
3063 }
3064
3065
3066 /* loadw. */
3067 void
3068 OP_9E_8 (SIM_DESC sd, SIM_CPU *cpu)
3069 {
3070 /* loadw [Rindex]disp0(RPbasex) REG
3071 * ADDR = Rpbasex + Rindex
3072 * REGR = [ADDR] */
3073
3074 uint32 addr;
3075 uint16 tmp;
3076 trace_input ("loadw", OP_RP_INDEX_DISP0, OP_REG, OP_VOID);
3077
3078 addr = (GPR32 (OP[2])) + OP[1];
3079
3080 if (OP[0] == 0)
3081 addr = (GPR32 (12)) + addr;
3082 else
3083 addr = (GPR32 (13)) + addr;
3084
3085 tmp = RW (addr);
3086 SET_GPR (OP[3], tmp);
3087 trace_output_16 (sd, tmp);
3088 }
3089
3090
3091 /* loadw. */
3092 void
3093 OP_21B_A (SIM_DESC sd, SIM_CPU *cpu)
3094 {
3095 /* loadw [Rindex]disp14(RPbasex) REG
3096 * ADDR = Rpbasex + Rindex + zext24(disp14)
3097 * REGR = [ADDR] */
3098
3099 uint32 addr;
3100 uint16 tmp;
3101 trace_input ("loadw", OP_RP_INDEX_DISP14, OP_REG, OP_VOID);
3102 addr = (GPR32 (OP[2])) + OP[1];
3103
3104 if (OP[0] == 0)
3105 addr = (GPR32 (12)) + addr;
3106 else
3107 addr = (GPR32 (13)) + addr;
3108
3109 tmp = (RW (addr));
3110 SET_GPR (OP[3], tmp);
3111 trace_output_16 (sd, tmp);
3112 }
3113
3114 /* loadw. */
3115 void
3116 OP_18C_14 (SIM_DESC sd, SIM_CPU *cpu)
3117 {
3118 /* loadw dispe20(REG) REGP
3119 * REGP = [DISPE20+[REG]] */
3120
3121 uint16 tmp;
3122 uint32 addr, a;
3123 trace_input ("loadw", OP_R_BASE_DISPE20, OP_REGP, OP_VOID);
3124 addr = OP[0] + (GPR (OP[1]));
3125 tmp = (RW (addr));
3126 if (OP[2] > 11)
3127 {
3128 a = (GPR32 (OP[2])) & 0xffff0000;
3129 SET_GPR32 (OP[2], (a | tmp));
3130 }
3131 else
3132 SET_GPR (OP[2], tmp);
3133
3134 trace_output_16 (sd, tmp);
3135 }
3136
3137
3138 /* loadw. */
3139 void
3140 OP_12C_14 (SIM_DESC sd, SIM_CPU *cpu)
3141 {
3142 /* loadw DISP20(REG) REGP
3143 * ADDR = zext24(Rbase) + zext24(disp20)
3144 * REGP = [ADDR] */
3145
3146 uint16 tmp;
3147 uint32 addr, a;
3148 trace_input ("loadw", OP_R_BASE_DISP20, OP_REGP, OP_VOID);
3149 addr = OP[0] + (GPR (OP[1]));
3150 tmp = (RW (addr));
3151 if (OP[2] > 11)
3152 {
3153 a = (GPR32 (OP[2])) & 0xffff0000;
3154 SET_GPR32 (OP[2], (a | tmp));
3155 }
3156 else
3157 SET_GPR (OP[2], tmp);
3158
3159 trace_output_16 (sd, tmp);
3160 }
3161
3162 /* loadw. */
3163 void
3164 OP_9F_8 (SIM_DESC sd, SIM_CPU *cpu)
3165 {
3166 /* loadw disp16(REGP) REGP
3167 * ADDR = RPbase + zext24(disp16)
3168 * REGP = [ADDR] */
3169 uint16 tmp;
3170 uint32 addr, a;
3171 trace_input ("loadw", OP_RP_BASE_DISP16, OP_REGP, OP_VOID);
3172 addr = (GPR32 (OP[1])) + OP[0];
3173 tmp = (RW (addr));
3174 if (OP[2] > 11)
3175 {
3176 a = (GPR32 (OP[2])) & 0xffff0000;
3177 SET_GPR32 (OP[2], (a | tmp));
3178 }
3179 else
3180 SET_GPR (OP[2], tmp);
3181
3182 trace_output_16 (sd, tmp);
3183 }
3184
3185 /* loadw. */
3186 void
3187 OP_12D_14 (SIM_DESC sd, SIM_CPU *cpu)
3188 {
3189 /* loadw disp20(REGP) REGP
3190 * ADDR = RPbase + zext24(disp20)
3191 * REGP = [ADDR] */
3192 uint16 tmp;
3193 uint32 addr, a;
3194 trace_input ("loadw", OP_RP_BASE_DISP20, OP_REG, OP_VOID);
3195 addr = (GPR32 (OP[1])) + OP[0];
3196 tmp = (RW (addr));
3197 if (OP[2] > 11)
3198 {
3199 a = (GPR32 (OP[2])) & 0xffff0000;
3200 SET_GPR32 (OP[2], (a | tmp));
3201 }
3202 else
3203 SET_GPR (OP[2], tmp);
3204
3205 trace_output_16 (sd, tmp);
3206 }
3207
3208 /* loadw. */
3209 void
3210 OP_18D_14 (SIM_DESC sd, SIM_CPU *cpu)
3211 {
3212 /* loadw -disp20(REGP) REG
3213 * ADDR = RPbase + zext24(-disp20)
3214 * REGR = [ADDR] */
3215
3216 uint16 tmp;
3217 uint32 addr, a;
3218 trace_input ("loadw", OP_RP_BASE_DISPE20, OP_REG, OP_VOID);
3219 addr = (GPR32 (OP[1])) + OP[0];
3220 tmp = (RB (addr));
3221 if (OP[2] > 11)
3222 {
3223 a = (GPR32 (OP[2])) & 0xffff0000;
3224 SET_GPR32 (OP[2], (a | tmp));
3225 }
3226 else
3227 SET_GPR (OP[2], tmp);
3228
3229 trace_output_16 (sd, tmp);
3230 }
3231
3232
3233 /* loadw. */
3234 void
3235 OP_12E_14 (SIM_DESC sd, SIM_CPU *cpu)
3236 {
3237 /* loadw [Rindex]disp20(RPbasexb) REG
3238 * ADDR = RPbasex + Rindex + zext24(disp20)
3239 * REGR = [ADDR] */
3240
3241 uint32 addr;
3242 uint16 tmp;
3243 trace_input ("loadw", OP_RP_INDEX_DISP20, OP_REG, OP_VOID);
3244
3245 if (OP[0] == 0)
3246 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3247 else
3248 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3249
3250 tmp = (RW (addr));
3251 SET_GPR (OP[3], tmp);
3252 trace_output_16 (sd, tmp);
3253 }
3254
3255
3256 /* loadd. */
3257 void
3258 OP_87_8 (SIM_DESC sd, SIM_CPU *cpu)
3259 {
3260 /* loadd ABS20, REGP
3261 * ADDR = zext24(abs20) | remap
3262 * REGP = [ADDR]
3263 * NOTE: remap is
3264 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3265 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3266 * by the core to 16M-64k to 16M. */
3267
3268 uint32 addr, tmp;
3269 addr = OP[0];
3270 trace_input ("loadd", OP_ABS20, OP_REGP, OP_VOID);
3271 if (addr > 0xEFFFF) addr |= 0xF00000;
3272 tmp = RLW (addr);
3273 tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff);
3274 SET_GPR32 (OP[1], tmp);
3275 trace_output_32 (sd, tmp);
3276 }
3277
3278 /* loadd. */
3279 void
3280 OP_12B_14 (SIM_DESC sd, SIM_CPU *cpu)
3281 {
3282 /* loadd ABS24, REGP
3283 * ADDR = abs24
3284 * REGP = [ADDR] */
3285
3286 uint32 addr = OP[0];
3287 uint32 tmp;
3288 trace_input ("loadd", OP_ABS24, OP_REGP, OP_VOID);
3289 tmp = RLW (addr);
3290 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3291 SET_GPR32 (OP[1],tmp);
3292 trace_output_32 (sd, tmp);
3293 }
3294
3295
3296 /* loadd. */
3297 void
3298 OP_46_7 (SIM_DESC sd, SIM_CPU *cpu)
3299 {
3300 /* loadd [Rindex]ABS20 REGP
3301 * ADDR = Rindex + zext24(disp20)
3302 * REGP = [ADDR] */
3303
3304 uint32 addr, tmp;
3305 trace_input ("loadd", OP_R_INDEX8_ABS20, OP_REGP, OP_VOID);
3306
3307 if (OP[0] == 0)
3308 addr = (GPR32 (12)) + OP[1];
3309 else
3310 addr = (GPR32 (13)) + OP[1];
3311
3312 tmp = RLW (addr);
3313 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3314 SET_GPR32 (OP[2], tmp);
3315 trace_output_32 (sd, tmp);
3316 }
3317
3318
3319 /* loadd. */
3320 void
3321 OP_A_4 (SIM_DESC sd, SIM_CPU *cpu)
3322 {
3323 /* loadd dips4(regp) REGP
3324 * ADDR = Rpbase + zext24(disp4)
3325 * REGP = [ADDR] */
3326
3327 uint32 tmp, addr = (GPR32 (OP[1])) + OP[0];
3328 trace_input ("loadd", OP_RP_BASE_DISP4, OP_REGP, OP_VOID);
3329 tmp = RLW (addr);
3330 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3331 SET_GPR32 (OP[2], tmp);
3332 trace_output_32 (sd, tmp);
3333 }
3334
3335
3336 /* loadd. */
3337 void
3338 OP_AE_8 (SIM_DESC sd, SIM_CPU *cpu)
3339 {
3340 /* loadd [Rindex]disp0(RPbasex) REGP
3341 * ADDR = Rpbasex + Rindex
3342 * REGP = [ADDR] */
3343
3344 uint32 addr, tmp;
3345 trace_input ("loadd", OP_RP_INDEX_DISP0, OP_REGP, OP_VOID);
3346
3347 if (OP[0] == 0)
3348 addr = (GPR32 (12)) + (GPR32 (OP[2])) + OP[1];
3349 else
3350 addr = (GPR32 (13)) + (GPR32 (OP[2])) + OP[1];
3351
3352 tmp = RLW (addr);
3353 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3354 SET_GPR32 (OP[3], tmp);
3355 trace_output_32 (sd, tmp);
3356 }
3357
3358
3359 /* loadd. */
3360 void
3361 OP_21A_A (SIM_DESC sd, SIM_CPU *cpu)
3362 {
3363 /* loadd [Rindex]disp14(RPbasex) REGP
3364 * ADDR = Rpbasex + Rindex + zext24(disp14)
3365 * REGR = [ADDR] */
3366
3367 uint32 addr, tmp;
3368 trace_input ("loadd", OP_RP_INDEX_DISP14, OP_REGP, OP_VOID);
3369
3370 if (OP[0] == 0)
3371 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3372 else
3373 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3374
3375 tmp = RLW (addr);
3376 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3377 SET_GPR (OP[3],tmp);
3378 trace_output_32 (sd, tmp);
3379 }
3380
3381
3382 /* loadd. */
3383 void
3384 OP_188_14 (SIM_DESC sd, SIM_CPU *cpu)
3385 {
3386 /* loadd dispe20(REG) REG
3387 * zext24(Rbase) + zext24(dispe20)
3388 * REG = [ADDR] */
3389
3390 uint32 tmp, addr = OP[0] + (GPR (OP[1]));
3391 trace_input ("loadd", OP_R_BASE_DISPE20, OP_REGP, OP_VOID);
3392 tmp = RLW (addr);
3393 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3394 SET_GPR32 (OP[2], tmp);
3395 trace_output_32 (sd, tmp);
3396 }
3397
3398
3399 /* loadd. */
3400 void
3401 OP_128_14 (SIM_DESC sd, SIM_CPU *cpu)
3402 {
3403 /* loadd DISP20(REG) REG
3404 * ADDR = zext24(Rbase) + zext24(disp20)
3405 * REG = [ADDR] */
3406
3407 uint32 tmp, addr = OP[0] + (GPR (OP[1]));
3408 trace_input ("loadd", OP_R_BASE_DISP20, OP_REGP, OP_VOID);
3409 tmp = RLW (addr);
3410 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3411 SET_GPR32 (OP[2], tmp);
3412 trace_output_32 (sd, tmp);
3413 }
3414
3415 /* loadd. */
3416 void
3417 OP_AF_8 (SIM_DESC sd, SIM_CPU *cpu)
3418 {
3419 /* loadd disp16(REGP) REGP
3420 * ADDR = RPbase + zext24(disp16)
3421 * REGR = [ADDR] */
3422 uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
3423 trace_input ("loadd", OP_RP_BASE_DISP16, OP_REGP, OP_VOID);
3424 tmp = RLW (addr);
3425 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3426 SET_GPR32 (OP[2], tmp);
3427 trace_output_32 (sd, tmp);
3428 }
3429
3430
3431 /* loadd. */
3432 void
3433 OP_129_14 (SIM_DESC sd, SIM_CPU *cpu)
3434 {
3435 /* loadd disp20(REGP) REGP
3436 * ADDR = RPbase + zext24(disp20)
3437 * REGP = [ADDR] */
3438 uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
3439 trace_input ("loadd", OP_RP_BASE_DISP20, OP_REGP, OP_VOID);
3440 tmp = RLW (addr);
3441 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3442 SET_GPR32 (OP[2], tmp);
3443 trace_output_32 (sd, tmp);
3444 }
3445
3446 /* loadd. */
3447 void
3448 OP_189_14 (SIM_DESC sd, SIM_CPU *cpu)
3449 {
3450 /* loadd -disp20(REGP) REGP
3451 * ADDR = RPbase + zext24(-disp20)
3452 * REGP = [ADDR] */
3453
3454 uint32 tmp, addr = OP[0] + (GPR32 (OP[1]));
3455 trace_input ("loadd", OP_RP_BASE_DISPE20, OP_REGP, OP_VOID);
3456 tmp = RLW (addr);
3457 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff);
3458 SET_GPR32 (OP[2], tmp);
3459 trace_output_32 (sd, tmp);
3460 }
3461
3462 /* loadd. */
3463 void
3464 OP_12A_14 (SIM_DESC sd, SIM_CPU *cpu)
3465 {
3466 /* loadd [Rindex]disp20(RPbasexb) REGP
3467 * ADDR = RPbasex + Rindex + zext24(disp20)
3468 * REGP = [ADDR] */
3469
3470 uint32 addr, tmp;
3471 trace_input ("loadd", OP_RP_INDEX_DISP20, OP_REGP, OP_VOID);
3472
3473 if (OP[0] == 0)
3474 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2]));
3475 else
3476 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2]));
3477
3478 tmp = RLW (addr);
3479 tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff);
3480 SET_GPR32 (OP[3], tmp);
3481 trace_output_32 (sd, tmp);
3482 }
3483
3484
3485 /* storb. */
3486 void
3487 OP_C8_8 (SIM_DESC sd, SIM_CPU *cpu)
3488 {
3489 /* storb REG, ABS20
3490 * ADDR = zext24(abs20) | remap
3491 * [ADDR] = REGR
3492 * NOTE: remap is
3493 * If (abs20 > 0xEFFFF) the resulting address is logically ORed
3494 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped
3495 * by the core to 16M-64k to 16M. */
3496
3497 uint8 a = ((GPR (OP[0])) & 0xff);
3498 uint32 addr = OP[1];
3499 trace_input ("storb", OP_REG, OP_ABS20_OUTPUT, OP_VOID);
3500 SB (addr, a);
3501 trace_output_32 (sd, addr);
3502 }
3503
3504 /* storb. */
3505 void
3506 OP_137_14 (SIM_DESC sd, SIM_CPU *cpu)
3507 {
3508 /* storb REG, ABS24
3509 * ADDR = abs24
3510 * [ADDR] = REGR. */
3511
3512 uint8 a = ((GPR (OP[0])) & 0xff);
3513 uint32 addr = OP[1];
3514 trace_input ("storb", OP_REG, OP_ABS24_OUTPUT, OP_VOID);
3515 SB (addr, a);
3516 trace_output_32 (sd, addr);
3517 }
3518
3519 /* storb. */
3520 void
3521 OP_65_7 (SIM_DESC sd, SIM_CPU *cpu)
3522 {
3523 /* storb REG, [Rindex]ABS20
3524 * ADDR = Rindex + zext24(disp20)
3525 * [ADDR] = REGR */
3526
3527 uint32 addr;
3528 uint8 a = ((GPR (OP[0])) & 0xff);
3529 trace_input ("storb", OP_REG, OP_R_INDEX8_ABS20, OP_VOID);
3530
3531 if (OP[1] == 0)
3532 addr = (GPR32 (12)) + OP[2];
3533 else
3534 addr = (GPR32 (13)) + OP[2];
3535
3536 SB (addr, a);
3537 trace_output_32 (sd, addr);
3538 }
3539
3540 /* storb. */
3541 void
3542 OP_F_4 (SIM_DESC sd, SIM_CPU *cpu)
3543 {
3544 /* storb REG, DIPS4(REGP)
3545 * ADDR = RPBASE + zext24(DISP4)
3546 * [ADDR] = REG. */
3547
3548 uint16 a = ((GPR (OP[0])) & 0xff);
3549 uint32 addr = (GPR32 (OP[2])) + OP[1];
3550 trace_input ("storb", OP_REG, OP_RP_BASE_DISPE4, OP_VOID);
3551 SB (addr, a);
3552 trace_output_32 (sd, addr);
3553 }
3554
3555 /* storb. */
3556 void
3557 OP_FE_8 (SIM_DESC sd, SIM_CPU *cpu)
3558 {
3559 /* storb [Rindex]disp0(RPbasex) REG
3560 * ADDR = Rpbasex + Rindex
3561 * [ADDR] = REGR */
3562
3563 uint32 addr;
3564 uint8 a = ((GPR (OP[0])) & 0xff);
3565 trace_input ("storb", OP_REG, OP_RP_INDEX_DISP0, OP_VOID);
3566
3567 if (OP[1] == 0)
3568 addr = (GPR32 (12)) + (GPR32 (OP[3])) + OP[2];
3569 else
3570 addr = (GPR32 (13)) + (GPR32 (OP[3])) + OP[2];
3571
3572 SB (addr, a);
3573 trace_output_32 (sd, addr);
3574 }
3575
3576 /* storb. */
3577 void
3578 OP_319_A (SIM_DESC sd, SIM_CPU *cpu)
3579 {
3580 /* storb REG, [Rindex]disp14(RPbasex)
3581 * ADDR = Rpbasex + Rindex + zext24(disp14)
3582 * [ADDR] = REGR */
3583
3584 uint8 a = ((GPR (OP[0])) & 0xff);
3585 uint32 addr = (GPR32 (OP[2])) + OP[1];
3586 trace_input ("storb", OP_REG, OP_RP_INDEX_DISP14, OP_VOID);
3587 SB (addr, a);
3588 trace_output_32 (sd, addr);
3589 }
3590
3591 /* storb. */
3592 void
3593 OP_194_14 (SIM_DESC sd, SIM_CPU *cpu)
3594 {
3595 /* storb REG, DISPE20(REG)
3596 * zext24(Rbase) + zext24(dispe20)
3597 * [ADDR] = REG */
3598
3599 uint8 a = ((GPR (OP[0])) & 0xff);
3600 uint32 addr = OP[1] + (GPR (OP[2]));
3601 trace_input ("storb", OP_REG, OP_R_BASE_DISPE20, OP_VOID);
3602 SB (addr, a);
3603 trace_output_32 (sd, addr);
3604 }
3605
3606 /* storb. */
3607 void
3608 OP_134_14 (SIM_DESC sd, SIM_CPU *cpu)
3609 {
3610 /* storb REG, DISP20(REG)
3611 * ADDR = zext24(Rbase) + zext24(disp20)
3612 * [ADDR] = REG */
3613
3614 uint8 a = (GPR (OP[0]) & 0xff);
3615 uint32 addr = OP[1] + (GPR (OP[2]));
3616 trace_input ("storb", OP_REG, OP_R_BASE_DISPS20, OP_VOID);
3617 SB (addr, a);
3618 trace_output_32 (sd, addr);
3619 }
3620
3621 /* storb. */
3622 void
3623 OP_FF_8 (SIM_DESC sd, SIM_CPU *cpu)
3624 {
3625 /* storb REG, disp16(REGP)
3626 * ADDR = RPbase + zext24(disp16)
3627 * [ADDR] = REGP */
3628
3629 uint8 a = ((GPR (OP[0])) & 0xff);
3630 uint32 addr = (GPR32 (OP[2])) + OP[1];
3631 trace_input ("storb", OP_REG, OP_RP_BASE_DISP16, OP_VOID);
3632 SB (addr, a);
3633 trace_output_32 (sd, addr);
3634 }
3635
3636 /* storb. */
3637 void
3638 OP_135_14 (SIM_DESC sd, SIM_CPU *cpu)
3639 {
3640 /* storb REG, disp20(REGP)
3641 * ADDR = RPbase + zext24(disp20)
3642 * [ADDR] = REGP */
3643
3644 uint8 a = ((GPR (OP[0])) & 0xff);
3645 uint32 addr = (GPR32 (OP[2])) + OP[1];
3646 trace_input ("storb", OP_REG, OP_RP_BASE_DISPS20, OP_VOID);
3647 SB (addr, a);
3648 trace_output_32 (sd, addr);
3649 }
3650
3651 /* storb. */
3652 void
3653 OP_195_14 (SIM_DESC sd, SIM_CPU *cpu)
3654 {
3655 /* storb REG, -disp20(REGP)
3656 * ADDR = RPbase + zext24(-disp20)
3657 * [ADDR] = REGP */
3658
3659 uint8 a = (GPR (OP[0]) & 0xff);
3660 uint32 addr = (GPR32 (OP[2])) + OP[1];
3661 trace_input ("storb", OP_REG, OP_RP_BASE_DISPE20, OP_VOID);
3662 SB (addr, a);
3663 trace_output_32 (sd, addr);
3664 }
3665
3666 /* storb. */
3667 void
3668 OP_136_14 (SIM_DESC sd, SIM_CPU *cpu)
3669 {
3670 /* storb REG, [Rindex]disp20(RPbase)
3671 * ADDR = RPbasex + Rindex + zext24(disp20)
3672 * [ADDR] = REGP */
3673
3674 uint8 a = (GPR (OP[0])) & 0xff;
3675 uint32 addr = (GPR32 (OP[2])) + OP[1];
3676 trace_input ("storb", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID);
3677 SB (addr, a);
3678 trace_output_32 (sd, addr);
3679 }
3680
3681 /* STR_IMM instructions. */
3682 /* storb . */
3683 void
3684 OP_81_8 (SIM_DESC sd, SIM_CPU *cpu)
3685 {
3686 uint8 a = (OP[0]) & 0xff;
3687 uint32 addr = OP[1];
3688 trace_input ("storb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
3689 SB (addr, a);
3690 trace_output_32 (sd, addr);
3691 }
3692
3693 /* storb. */
3694 void
3695 OP_123_14 (SIM_DESC sd, SIM_CPU *cpu)
3696 {
3697 uint8 a = (OP[0]) & 0xff;
3698 uint32 addr = OP[1];
3699 trace_input ("storb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
3700 SB (addr, a);
3701 trace_output_32 (sd, addr);
3702 }
3703
3704 /* storb. */
3705 void
3706 OP_42_7 (SIM_DESC sd, SIM_CPU *cpu)
3707 {
3708 uint32 addr;
3709 uint8 a = (OP[0]) & 0xff;
3710 trace_input ("storb", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
3711
3712 if (OP[1] == 0)
3713 addr = (GPR32 (12)) + OP[2];
3714 else
3715 addr = (GPR32 (13)) + OP[2];
3716
3717 SB (addr, a);
3718 trace_output_32 (sd, addr);
3719 }
3720
3721 /* storb. */
3722 void
3723 OP_218_A (SIM_DESC sd, SIM_CPU *cpu)
3724 {
3725 uint8 a = (OP[0]) & 0xff;
3726 uint32 addr = (GPR32 (OP[2])) + OP[1];
3727 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID);
3728 SB (addr, a);
3729 trace_output_32 (sd, addr);
3730 }
3731
3732 /* storb. */
3733 void
3734 OP_82_8 (SIM_DESC sd, SIM_CPU *cpu)
3735 {
3736 uint8 a = (OP[0]) & 0xff;
3737 uint32 addr = (GPR32 (OP[2])) + OP[1];
3738 trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
3739 SB (addr, a);
3740 trace_output_32 (sd, addr);
3741 }
3742
3743 /* storb. */
3744 void
3745 OP_120_14 (SIM_DESC sd, SIM_CPU *cpu)
3746 {
3747 uint8 a = (OP[0]) & 0xff;
3748 uint32 addr = (GPR (OP[2])) + OP[1];
3749 trace_input ("storb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
3750 SB (addr, a);
3751 trace_output_32 (sd, addr);
3752 }
3753
3754 /* storb. */
3755 void
3756 OP_83_8 (SIM_DESC sd, SIM_CPU *cpu)
3757 {
3758 uint8 a = (OP[0]) & 0xff;
3759 uint32 addr = (GPR32 (OP[2])) + OP[1];
3760 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
3761 SB (addr, a);
3762 trace_output_32 (sd, addr);
3763 }
3764
3765 /* storb. */
3766 void
3767 OP_121_14 (SIM_DESC sd, SIM_CPU *cpu)
3768 {
3769 uint8 a = (OP[0]) & 0xff;
3770 uint32 addr = (GPR32 (OP[2])) + OP[1];
3771 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
3772 SB (addr, a);
3773 trace_output_32 (sd, addr);
3774 }
3775
3776 /* storb. */
3777 void
3778 OP_122_14 (SIM_DESC sd, SIM_CPU *cpu)
3779 {
3780 uint8 a = (OP[0]) & 0xff;
3781 uint32 addr = (GPR32 (OP[2])) + OP[1];
3782 trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
3783 SB (addr, a);
3784 trace_output_32 (sd, addr);
3785 }
3786 /* endif for STR_IMM. */
3787
3788 /* storw . */
3789 void
3790 OP_C9_8 (SIM_DESC sd, SIM_CPU *cpu)
3791 {
3792 uint16 a = GPR (OP[0]);
3793 uint32 addr = OP[1];
3794 trace_input ("storw", OP_REG, OP_ABS20_OUTPUT, OP_VOID);
3795 SW (addr, a);
3796 trace_output_32 (sd, addr);
3797 }
3798
3799 /* storw. */
3800 void
3801 OP_13F_14 (SIM_DESC sd, SIM_CPU *cpu)
3802 {
3803 uint16 a = GPR (OP[0]);
3804 uint32 addr = OP[1];
3805 trace_input ("storw", OP_REG, OP_ABS24_OUTPUT, OP_VOID);
3806 SW (addr, a);
3807 trace_output_32 (sd, addr);
3808 }
3809
3810 /* storw. */
3811 void
3812 OP_67_7 (SIM_DESC sd, SIM_CPU *cpu)
3813 {
3814 uint32 addr;
3815 uint16 a = GPR (OP[0]);
3816 trace_input ("storw", OP_REG, OP_R_INDEX8_ABS20, OP_VOID);
3817
3818 if (OP[1] == 0)
3819 addr = (GPR32 (12)) + OP[2];
3820 else
3821 addr = (GPR32 (13)) + OP[2];
3822
3823 SW (addr, a);
3824 trace_output_32 (sd, addr);
3825 }
3826
3827
3828 /* storw. */
3829 void
3830 OP_D_4 (SIM_DESC sd, SIM_CPU *cpu)
3831 {
3832 uint16 a = (GPR (OP[0]));
3833 uint32 addr = (GPR32 (OP[2])) + OP[1];
3834 trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID);
3835 SW (addr, a);
3836 trace_output_32 (sd, addr);
3837 }
3838
3839 /* storw. */
3840 void
3841 OP_DE_8 (SIM_DESC sd, SIM_CPU *cpu)
3842 {
3843 uint16 a = GPR (OP[0]);
3844 uint32 addr = (GPR32 (OP[2])) + OP[1];
3845 trace_input ("storw", OP_REG, OP_RP_INDEX_DISP0, OP_VOID);
3846 SW (addr, a);
3847 trace_output_32 (sd, addr);
3848 }
3849
3850 /* storw. */
3851 void
3852 OP_31B_A (SIM_DESC sd, SIM_CPU *cpu)
3853 {
3854 uint16 a = GPR (OP[0]);
3855 uint32 addr = (GPR32 (OP[2])) + OP[1];
3856 trace_input ("storw", OP_REG, OP_RP_INDEX_DISP14, OP_VOID);
3857 SW (addr, a);
3858 trace_output_32 (sd, addr);
3859 }
3860
3861 /* storw. */
3862 void
3863 OP_19C_14 (SIM_DESC sd, SIM_CPU *cpu)
3864 {
3865 uint16 a = (GPR (OP[0]));
3866 uint32 addr = (GPR32 (OP[2])) + OP[1];
3867 trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID);
3868 SW (addr, a);
3869 trace_output_32 (sd, addr);
3870 }
3871
3872 /* storw. */
3873 void
3874 OP_13C_14 (SIM_DESC sd, SIM_CPU *cpu)
3875 {
3876 uint16 a = (GPR (OP[0]));
3877 uint32 addr = (GPR (OP[2])) + OP[1];
3878 trace_input ("storw", OP_REG, OP_R_BASE_DISPS20, OP_VOID);
3879 SW (addr, a);
3880 trace_output_32 (sd, addr);
3881 }
3882
3883 /* storw. */
3884 void
3885 OP_DF_8 (SIM_DESC sd, SIM_CPU *cpu)
3886 {
3887 uint16 a = (GPR (OP[0]));
3888 uint32 addr = (GPR32 (OP[2])) + OP[1];
3889 trace_input ("storw", OP_REG, OP_RP_BASE_DISP16, OP_VOID);
3890 SW (addr, a);
3891 trace_output_32 (sd, addr);
3892 }
3893
3894 /* storw. */
3895 void
3896 OP_13D_14 (SIM_DESC sd, SIM_CPU *cpu)
3897 {
3898 uint16 a = (GPR (OP[0]));
3899 uint32 addr = (GPR32 (OP[2])) + OP[1];
3900 trace_input ("storw", OP_REG, OP_RP_BASE_DISPS20, OP_VOID);
3901 SW (addr, a);
3902 trace_output_32 (sd, addr);
3903 }
3904
3905 /* storw. */
3906 void
3907 OP_19D_14 (SIM_DESC sd, SIM_CPU *cpu)
3908 {
3909 uint16 a = (GPR (OP[0]));
3910 uint32 addr = (GPR32 (OP[2])) + OP[1];
3911 trace_input ("storw", OP_REG, OP_RP_BASE_DISPE20, OP_VOID);
3912 SW (addr, a);
3913 trace_output_32 (sd, addr);
3914 }
3915
3916 /* storw. */
3917 void
3918 OP_13E_14 (SIM_DESC sd, SIM_CPU *cpu)
3919 {
3920 uint16 a = (GPR (OP[0]));
3921 uint32 addr = (GPR32 (OP[2])) + OP[1];
3922 trace_input ("storw", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID);
3923 SW (addr, a);
3924 trace_output_32 (sd, addr);
3925 }
3926
3927 /* STORE-w IMM instruction *****/
3928 /* storw . */
3929 void
3930 OP_C1_8 (SIM_DESC sd, SIM_CPU *cpu)
3931 {
3932 uint16 a = OP[0];
3933 uint32 addr = OP[1];
3934 trace_input ("storw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID);
3935 SW (addr, a);
3936 trace_output_32 (sd, addr);
3937 }
3938
3939 /* storw. */
3940 void
3941 OP_133_14 (SIM_DESC sd, SIM_CPU *cpu)
3942 {
3943 uint16 a = OP[0];
3944 uint32 addr = OP[1];
3945 trace_input ("storw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID);
3946 SW (addr, a);
3947 trace_output_32 (sd, addr);
3948 }
3949
3950 /* storw. */
3951 void
3952 OP_62_7 (SIM_DESC sd, SIM_CPU *cpu)
3953 {
3954 uint32 addr;
3955 uint16 a = OP[0];
3956 trace_input ("storw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID);
3957
3958 if (OP[1] == 0)
3959 addr = (GPR32 (12)) + OP[2];
3960 else
3961 addr = (GPR32 (13)) + OP[2];
3962
3963 SW (addr, a);
3964 trace_output_32 (sd, addr);
3965 }
3966
3967 /* storw. */
3968 void
3969 OP_318_A (SIM_DESC sd, SIM_CPU *cpu)
3970 {
3971 uint16 a = OP[0];
3972 uint32 addr = (GPR32 (OP[2])) + OP[1];
3973 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID);
3974 SW (addr, a);
3975 trace_output_32 (sd, addr);
3976 }
3977
3978 /* storw. */
3979 void
3980 OP_C2_8 (SIM_DESC sd, SIM_CPU *cpu)
3981 {
3982 uint16 a = OP[0];
3983 uint32 addr = (GPR32 (OP[2])) + OP[1];
3984 trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID);
3985 SW (addr, a);
3986 trace_output_32 (sd, addr);
3987 }
3988
3989 /* storw. */
3990 void
3991 OP_130_14 (SIM_DESC sd, SIM_CPU *cpu)
3992 {
3993 uint16 a = OP[0];
3994 uint32 addr = (GPR32 (OP[2])) + OP[1];
3995 trace_input ("storw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID);
3996 SW (addr, a);
3997 trace_output_32 (sd, addr);
3998 }
3999
4000 /* storw. */
4001 void
4002 OP_C3_8 (SIM_DESC sd, SIM_CPU *cpu)
4003 {
4004 uint16 a = OP[0];
4005 uint32 addr = (GPR32 (OP[2])) + OP[1];
4006 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID);
4007 SW (addr, a);
4008 trace_output_32 (sd, addr);
4009 }
4010
4011
4012 /* storw. */
4013 void
4014 OP_131_14 (SIM_DESC sd, SIM_CPU *cpu)
4015 {
4016 uint16 a = OP[0];
4017 uint32 addr = (GPR32 (OP[2])) + OP[1];
4018 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID);
4019 SW (addr, a);
4020 trace_output_32 (sd, addr);
4021 }
4022
4023 /* storw. */
4024 void
4025 OP_132_14 (SIM_DESC sd, SIM_CPU *cpu)
4026 {
4027 uint16 a = OP[0];
4028 uint32 addr = (GPR32 (OP[2])) + OP[1];
4029 trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID);
4030 SW (addr, a);
4031 trace_output_32 (sd, addr);
4032 }
4033
4034
4035 /* stord. */
4036 void
4037 OP_C7_8 (SIM_DESC sd, SIM_CPU *cpu)
4038 {
4039 uint32 a = GPR32 (OP[0]);
4040 uint32 addr = OP[1];
4041 trace_input ("stord", OP_REGP, OP_ABS20_OUTPUT, OP_VOID);
4042 SLW (addr, a);
4043 trace_output_32 (sd, addr);
4044 }
4045
4046 /* stord. */
4047 void
4048 OP_13B_14 (SIM_DESC sd, SIM_CPU *cpu)
4049 {
4050 uint32 a = GPR32 (OP[0]);
4051 uint32 addr = OP[1];
4052 trace_input ("stord", OP_REGP, OP_ABS24_OUTPUT, OP_VOID);
4053 SLW (addr, a);
4054 trace_output_32 (sd, addr);
4055 }
4056
4057 /* stord. */
4058 void
4059 OP_66_7 (SIM_DESC sd, SIM_CPU *cpu)
4060 {
4061 uint32 addr, a = GPR32 (OP[0]);
4062 trace_input ("stord", OP_REGP, OP_R_INDEX8_ABS20, OP_VOID);
4063
4064 if (OP[1] == 0)
4065 addr = (GPR32 (12)) + OP[2];
4066 else
4067 addr = (GPR32 (13)) + OP[2];
4068
4069 SLW (addr, a);
4070 trace_output_32 (sd, addr);
4071 }
4072
4073 /* stord. */
4074 void
4075 OP_E_4 (SIM_DESC sd, SIM_CPU *cpu)
4076 {
4077 uint32 a = GPR32 (OP[0]);
4078 uint32 addr = (GPR32 (OP[2])) + OP[1];
4079 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID);
4080 SLW (addr, a);
4081 trace_output_32 (sd, addr);
4082 }
4083
4084 /* stord. */
4085 void
4086 OP_EE_8 (SIM_DESC sd, SIM_CPU *cpu)
4087 {
4088 uint32 a = GPR32 (OP[0]);
4089 uint32 addr = (GPR32 (OP[2])) + OP[1];
4090 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP0, OP_VOID);
4091 SLW (addr, a);
4092 trace_output_32 (sd, addr);
4093 }
4094
4095 /* stord. */
4096 void
4097 OP_31A_A (SIM_DESC sd, SIM_CPU *cpu)
4098 {
4099 uint32 a = GPR32 (OP[0]);
4100 uint32 addr = (GPR32 (OP[2])) + OP[1];
4101 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP14, OP_VOID);
4102 SLW (addr, a);
4103 trace_output_32 (sd, addr);
4104 }
4105
4106 /* stord. */
4107 void
4108 OP_198_14 (SIM_DESC sd, SIM_CPU *cpu)
4109 {
4110 uint32 a = GPR32 (OP[0]);
4111 uint32 addr = (GPR32 (OP[2])) + OP[1];
4112 trace_input ("stord", OP_REGP, OP_R_BASE_DISPE20, OP_VOID);
4113 SLW (addr, a);
4114 trace_output_32 (sd, addr);
4115 }
4116
4117 /* stord. */
4118 void
4119 OP_138_14 (SIM_DESC sd, SIM_CPU *cpu)
4120 {
4121 uint32 a = GPR32 (OP[0]);
4122 uint32 addr = (GPR32 (OP[2])) + OP[1];
4123 trace_input ("stord", OP_REGP, OP_R_BASE_DISPS20, OP_VOID);
4124 SLW (addr, a);
4125 trace_output_32 (sd, addr);
4126 }
4127
4128 /* stord. */
4129 void
4130 OP_EF_8 (SIM_DESC sd, SIM_CPU *cpu)
4131 {
4132 uint32 a = GPR32 (OP[0]);
4133 uint32 addr = (GPR32 (OP[2])) + OP[1];
4134 trace_input ("stord", OP_REGP, OP_RP_BASE_DISP16, OP_VOID);
4135 SLW (addr, a);
4136 trace_output_32 (sd, addr);
4137 }
4138
4139 /* stord. */
4140 void
4141 OP_139_14 (SIM_DESC sd, SIM_CPU *cpu)
4142 {
4143 uint32 a = GPR32 (OP[0]);
4144 uint32 addr = (GPR32 (OP[2])) + OP[1];
4145 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPS20, OP_VOID);
4146 SLW (addr, a);
4147 trace_output_32 (sd, addr);
4148 }
4149
4150 /* stord. */
4151 void
4152 OP_199_14 (SIM_DESC sd, SIM_CPU *cpu)
4153 {
4154 uint32 a = GPR32 (OP[0]);
4155 uint32 addr = (GPR32 (OP[2])) + OP[1];
4156 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID);
4157 SLW (addr, a);
4158 trace_output_32 (sd, addr);
4159 }
4160
4161 /* stord. */
4162 void
4163 OP_13A_14 (SIM_DESC sd, SIM_CPU *cpu)
4164 {
4165 uint32 a = GPR32 (OP[0]);
4166 uint32 addr = (GPR32 (OP[2])) + OP[1];
4167 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISPS20, OP_VOID);
4168 SLW (addr, a);
4169 trace_output_32 (sd, addr);
4170 }
4171
4172 /* macqu. */
4173 void
4174 OP_14D_14 (SIM_DESC sd, SIM_CPU *cpu)
4175 {
4176 int32 tmp;
4177 int16 src1, src2;
4178 trace_input ("macuw", OP_REG, OP_REG, OP_REGP);
4179 src1 = GPR (OP[0]);
4180 src2 = GPR (OP[1]);
4181 tmp = src1 * src2;
4182 /*REVISIT FOR SATURATION and Q FORMAT. */
4183 SET_GPR32 (OP[2], tmp);
4184 trace_output_32 (sd, tmp);
4185 }
4186
4187 /* macuw. */
4188 void
4189 OP_14E_14 (SIM_DESC sd, SIM_CPU *cpu)
4190 {
4191 uint32 tmp;
4192 uint16 src1, src2;
4193 trace_input ("macuw", OP_REG, OP_REG, OP_REGP);
4194 src1 = GPR (OP[0]);
4195 src2 = GPR (OP[1]);
4196 tmp = src1 * src2;
4197 /*REVISIT FOR SATURATION. */
4198 SET_GPR32 (OP[2], tmp);
4199 trace_output_32 (sd, tmp);
4200 }
4201
4202 /* macsw. */
4203 void
4204 OP_14F_14 (SIM_DESC sd, SIM_CPU *cpu)
4205 {
4206 int32 tmp;
4207 int16 src1, src2;
4208 trace_input ("macsw", OP_REG, OP_REG, OP_REGP);
4209 src1 = GPR (OP[0]);
4210 src2 = GPR (OP[1]);
4211 tmp = src1 * src2;
4212 /*REVISIT FOR SATURATION. */
4213 SET_GPR32 (OP[2], tmp);
4214 trace_output_32 (sd, tmp);
4215 }
4216
4217
4218 /* mulb. */
4219 void
4220 OP_64_8 (SIM_DESC sd, SIM_CPU *cpu)
4221 {
4222 int16 tmp;
4223 int8 a = (OP[0]) & 0xff;
4224 int8 b = (GPR (OP[1])) & 0xff;
4225 trace_input ("mulb", OP_CONSTANT4_1, OP_REG, OP_VOID);
4226 tmp = (a * b) & 0xff;
4227 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4228 trace_output_16 (sd, tmp);
4229 }
4230
4231 /* mulb. */
4232 void
4233 OP_64B_C (SIM_DESC sd, SIM_CPU *cpu)
4234 {
4235 int16 tmp;
4236 int8 a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
4237 trace_input ("mulb", OP_CONSTANT4, OP_REG, OP_VOID);
4238 tmp = (a * b) & 0xff;
4239 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4240 trace_output_16 (sd, tmp);
4241 }
4242
4243
4244 /* mulb. */
4245 void
4246 OP_65_8 (SIM_DESC sd, SIM_CPU *cpu)
4247 {
4248 int16 tmp;
4249 int8 a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
4250 trace_input ("mulb", OP_REG, OP_REG, OP_VOID);
4251 tmp = (a * b) & 0xff;
4252 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4253 trace_output_16 (sd, tmp);
4254 }
4255
4256
4257 /* mulw. */
4258 void
4259 OP_66_8 (SIM_DESC sd, SIM_CPU *cpu)
4260 {
4261 int32 tmp;
4262 uint16 a = OP[0];
4263 int16 b = (GPR (OP[1]));
4264 trace_input ("mulw", OP_CONSTANT4_1, OP_REG, OP_VOID);
4265 tmp = (a * b) & 0xffff;
4266 SET_GPR (OP[1], tmp);
4267 trace_output_32 (sd, tmp);
4268 }
4269
4270 /* mulw. */
4271 void
4272 OP_66B_C (SIM_DESC sd, SIM_CPU *cpu)
4273 {
4274 int32 tmp;
4275 int16 a = OP[0], b = (GPR (OP[1]));
4276 trace_input ("mulw", OP_CONSTANT4, OP_REG, OP_VOID);
4277 tmp = (a * b) & 0xffff;
4278 SET_GPR (OP[1], tmp);
4279 trace_output_32 (sd, tmp);
4280 }
4281
4282
4283 /* mulw. */
4284 void
4285 OP_67_8 (SIM_DESC sd, SIM_CPU *cpu)
4286 {
4287 int32 tmp;
4288 int16 a = (GPR (OP[0])), b = (GPR (OP[1]));
4289 trace_input ("mulw", OP_REG, OP_REG, OP_VOID);
4290 tmp = (a * b) & 0xffff;
4291 SET_GPR (OP[1], tmp);
4292 trace_output_32 (sd, tmp);
4293 }
4294
4295
4296 /* mulsb. */
4297 void
4298 OP_B_8 (SIM_DESC sd, SIM_CPU *cpu)
4299 {
4300 int16 tmp;
4301 int8 a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
4302 trace_input ("mulsb", OP_REG, OP_REG, OP_VOID);
4303 tmp = a * b;
4304 SET_GPR (OP[1], tmp);
4305 trace_output_32 (sd, tmp);
4306 }
4307
4308 /* mulsw. */
4309 void
4310 OP_62_8 (SIM_DESC sd, SIM_CPU *cpu)
4311 {
4312 int32 tmp;
4313 int16 a = (GPR (OP[0])), b = (GPR (OP[1]));
4314 trace_input ("mulsw", OP_REG, OP_REGP, OP_VOID);
4315 tmp = a * b;
4316 SET_GPR32 (OP[1], tmp);
4317 trace_output_32 (sd, tmp);
4318 }
4319
4320 /* muluw. */
4321 void
4322 OP_63_8 (SIM_DESC sd, SIM_CPU *cpu)
4323 {
4324 uint32 tmp;
4325 uint16 a = (GPR (OP[0])), b = (GPR (OP[1]));
4326 trace_input ("muluw", OP_REG, OP_REGP, OP_VOID);
4327 tmp = a * b;
4328 SET_GPR32 (OP[1], tmp);
4329 trace_output_32 (sd, tmp);
4330 }
4331
4332
4333 /* nop. */
4334 void
4335 OP_2C00_10 (SIM_DESC sd, SIM_CPU *cpu)
4336 {
4337 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
4338
4339 #if 0
4340 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */
4341 switch (State.ins_type)
4342 {
4343 default:
4344 ins_type_counters[ (int)INS_UNKNOWN ]++;
4345 break;
4346
4347 }
4348 EXCEPTION (SIM_SIGTRAP);
4349 #endif
4350 trace_output_void (sd);
4351 }
4352
4353
4354 /* orb. */
4355 void
4356 OP_24_8 (SIM_DESC sd, SIM_CPU *cpu)
4357 {
4358 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
4359 trace_input ("orb", OP_CONSTANT4, OP_REG, OP_VOID);
4360 tmp = a | b;
4361 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
4362 trace_output_16 (sd, tmp);
4363 }
4364
4365 /* orb. */
4366 void
4367 OP_24B_C (SIM_DESC sd, SIM_CPU *cpu)
4368 {
4369 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
4370 trace_input ("orb", OP_CONSTANT16, OP_REG, OP_VOID);
4371 tmp = a | b;
4372 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
4373 trace_output_16 (sd, tmp);
4374 }
4375
4376 /* orb. */
4377 void
4378 OP_25_8 (SIM_DESC sd, SIM_CPU *cpu)
4379 {
4380 uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
4381 trace_input ("orb", OP_REG, OP_REG, OP_VOID);
4382 tmp = a | b;
4383 SET_GPR (OP[1], ((GPR (OP[1]) | tmp)));
4384 trace_output_16 (sd, tmp);
4385 }
4386
4387 /* orw. */
4388 void
4389 OP_26_8 (SIM_DESC sd, SIM_CPU *cpu)
4390 {
4391 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
4392 trace_input ("orw", OP_CONSTANT4, OP_REG, OP_VOID);
4393 tmp = a | b;
4394 SET_GPR (OP[1], tmp);
4395 trace_output_16 (sd, tmp);
4396 }
4397
4398
4399 /* orw. */
4400 void
4401 OP_26B_C (SIM_DESC sd, SIM_CPU *cpu)
4402 {
4403 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
4404 trace_input ("orw", OP_CONSTANT16, OP_REG, OP_VOID);
4405 tmp = a | b;
4406 SET_GPR (OP[1], tmp);
4407 trace_output_16 (sd, tmp);
4408 }
4409
4410 /* orw. */
4411 void
4412 OP_27_8 (SIM_DESC sd, SIM_CPU *cpu)
4413 {
4414 uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
4415 trace_input ("orw", OP_REG, OP_REG, OP_VOID);
4416 tmp = a | b;
4417 SET_GPR (OP[1], tmp);
4418 trace_output_16 (sd, tmp);
4419 }
4420
4421
4422 /* lshb. */
4423 void
4424 OP_13_9 (SIM_DESC sd, SIM_CPU *cpu)
4425 {
4426 uint16 a = OP[0];
4427 uint16 tmp, b = (GPR (OP[1])) & 0xFF;
4428 trace_input ("lshb", OP_CONSTANT4, OP_REG, OP_VOID);
4429 /* A positive count specifies a shift to the left;
4430 * A negative count specifies a shift to the right. */
4431 if (sign_flag)
4432 tmp = b >> a;
4433 else
4434 tmp = b << a;
4435
4436 sign_flag = 0; /* Reset sign_flag. */
4437
4438 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4439 trace_output_16 (sd, tmp);
4440 }
4441
4442 /* lshb. */
4443 void
4444 OP_44_8 (SIM_DESC sd, SIM_CPU *cpu)
4445 {
4446 uint16 a = (GPR (OP[0])) & 0xff;
4447 uint16 tmp, b = (GPR (OP[1])) & 0xFF;
4448 trace_input ("lshb", OP_REG, OP_REG, OP_VOID);
4449 if (a & ((long)1 << 3))
4450 {
4451 sign_flag = 1;
4452 a = ~(a) + 1;
4453 }
4454 a = (unsigned int) (a & 0x7);
4455
4456 /* A positive count specifies a shift to the left;
4457 * A negative count specifies a shift to the right. */
4458 if (sign_flag)
4459 tmp = b >> a;
4460 else
4461 tmp = b << a;
4462
4463 sign_flag = 0; /* Reset sign_flag. */
4464 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4465 trace_output_16 (sd, tmp);
4466 }
4467
4468 /* lshw. */
4469 void
4470 OP_46_8 (SIM_DESC sd, SIM_CPU *cpu)
4471 {
4472 uint16 tmp, b = GPR (OP[1]);
4473 int16 a = GPR (OP[0]);
4474 trace_input ("lshw", OP_REG, OP_REG, OP_VOID);
4475 if (a & ((long)1 << 4))
4476 {
4477 sign_flag = 1;
4478 a = ~(a) + 1;
4479 }
4480 a = (unsigned int) (a & 0xf);
4481
4482 /* A positive count specifies a shift to the left;
4483 * A negative count specifies a shift to the right. */
4484 if (sign_flag)
4485 tmp = b >> a;
4486 else
4487 tmp = b << a;
4488
4489 sign_flag = 0; /* Reset sign_flag. */
4490 SET_GPR (OP[1], (tmp & 0xffff));
4491 trace_output_16 (sd, tmp);
4492 }
4493
4494 /* lshw. */
4495 void
4496 OP_49_8 (SIM_DESC sd, SIM_CPU *cpu)
4497 {
4498 uint16 tmp, b = GPR (OP[1]);
4499 uint16 a = OP[0];
4500 trace_input ("lshw", OP_CONSTANT5, OP_REG, OP_VOID);
4501 /* A positive count specifies a shift to the left;
4502 * A negative count specifies a shift to the right. */
4503 if (sign_flag)
4504 tmp = b >> a;
4505 else
4506 tmp = b << a;
4507
4508 sign_flag = 0; /* Reset sign_flag. */
4509 SET_GPR (OP[1], (tmp & 0xffff));
4510 trace_output_16 (sd, tmp);
4511 }
4512
4513 /* lshd. */
4514 void
4515 OP_25_7 (SIM_DESC sd, SIM_CPU *cpu)
4516 {
4517 uint32 tmp, b = GPR32 (OP[1]);
4518 uint16 a = OP[0];
4519 trace_input ("lshd", OP_CONSTANT6, OP_REGP, OP_VOID);
4520 /* A positive count specifies a shift to the left;
4521 * A negative count specifies a shift to the right. */
4522 if (sign_flag)
4523 tmp = b >> a;
4524 else
4525 tmp = b << a;
4526
4527 sign_flag = 0; /* Reset sign flag. */
4528
4529 SET_GPR32 (OP[1], tmp);
4530 trace_output_32 (sd, tmp);
4531 }
4532
4533 /* lshd. */
4534 void
4535 OP_47_8 (SIM_DESC sd, SIM_CPU *cpu)
4536 {
4537 uint32 tmp, b = GPR32 (OP[1]);
4538 uint16 a = GPR (OP[0]);
4539 trace_input ("lshd", OP_REG, OP_REGP, OP_VOID);
4540 if (a & ((long)1 << 5))
4541 {
4542 sign_flag = 1;
4543 a = ~(a) + 1;
4544 }
4545 a = (unsigned int) (a & 0x1f);
4546 /* A positive count specifies a shift to the left;
4547 * A negative count specifies a shift to the right. */
4548 if (sign_flag)
4549 tmp = b >> a;
4550 else
4551 tmp = b << a;
4552
4553 sign_flag = 0; /* Reset sign flag. */
4554
4555 SET_GPR32 (OP[1], tmp);
4556 trace_output_32 (sd, tmp);
4557 }
4558
4559 /* ashub. */
4560 void
4561 OP_80_9 (SIM_DESC sd, SIM_CPU *cpu)
4562 {
4563 uint16 a = OP[0];
4564 int8 tmp, b = (GPR (OP[1])) & 0xFF;
4565 trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID);
4566 /* A positive count specifies a shift to the left;
4567 * A negative count specifies a shift to the right. */
4568 if (sign_flag)
4569 tmp = b >> a;
4570 else
4571 tmp = b << a;
4572
4573 sign_flag = 0; /* Reset sign flag. */
4574
4575 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xff00)));
4576 trace_output_16 (sd, tmp);
4577 }
4578
4579 /* ashub. */
4580 void
4581 OP_81_9 (SIM_DESC sd, SIM_CPU *cpu)
4582 {
4583 uint16 a = OP[0];
4584 int8 tmp, b = (GPR (OP[1])) & 0xFF;
4585 trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID);
4586 /* A positive count specifies a shift to the left;
4587 * A negative count specifies a shift to the right. */
4588 if (sign_flag)
4589 tmp = b >> a;
4590 else
4591 tmp = b << a;
4592
4593 sign_flag = 0; /* Reset sign flag. */
4594
4595 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4596 trace_output_16 (sd, tmp);
4597 }
4598
4599
4600 /* ashub. */
4601 void
4602 OP_41_8 (SIM_DESC sd, SIM_CPU *cpu)
4603 {
4604 int16 a = (GPR (OP[0]));
4605 int8 tmp, b = (GPR (OP[1])) & 0xFF;
4606 trace_input ("ashub", OP_REG, OP_REG, OP_VOID);
4607
4608 if (a & ((long)1 << 3))
4609 {
4610 sign_flag = 1;
4611 a = ~(a) + 1;
4612 }
4613 a = (unsigned int) (a & 0x7);
4614
4615 /* A positive count specifies a shift to the left;
4616 * A negative count specifies a shift to the right. */
4617 if (sign_flag)
4618 tmp = b >> a;
4619 else
4620 tmp = b << a;
4621
4622 sign_flag = 0; /* Reset sign flag. */
4623
4624 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00)));
4625 trace_output_16 (sd, tmp);
4626 }
4627
4628
4629 /* ashuw. */
4630 void
4631 OP_42_8 (SIM_DESC sd, SIM_CPU *cpu)
4632 {
4633 int16 tmp, b = GPR (OP[1]);
4634 uint16 a = OP[0];
4635 trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID);
4636 /* A positive count specifies a shift to the left;
4637 * A negative count specifies a shift to the right. */
4638 if (sign_flag)
4639 tmp = b >> a;
4640 else
4641 tmp = b << a;
4642
4643 sign_flag = 0; /* Reset sign flag. */
4644
4645 SET_GPR (OP[1], (tmp & 0xffff));
4646 trace_output_16 (sd, tmp);
4647 }
4648
4649 /* ashuw. */
4650 void
4651 OP_43_8 (SIM_DESC sd, SIM_CPU *cpu)
4652 {
4653 int16 tmp, b = GPR (OP[1]);
4654 uint16 a = OP[0];
4655 trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID);
4656 /* A positive count specifies a shift to the left;
4657 * A negative count specifies a shift to the right. */
4658 if (sign_flag)
4659 tmp = b >> a;
4660 else
4661 tmp = b << a;
4662
4663 sign_flag = 0; /* Reset sign flag. */
4664 SET_GPR (OP[1], (tmp & 0xffff));
4665 trace_output_16 (sd, tmp);
4666 }
4667
4668 /* ashuw. */
4669 void
4670 OP_45_8 (SIM_DESC sd, SIM_CPU *cpu)
4671 {
4672 int16 tmp;
4673 int16 a = GPR (OP[0]), b = GPR (OP[1]);
4674 trace_input ("ashuw", OP_REG, OP_REG, OP_VOID);
4675
4676 if (a & ((long)1 << 4))
4677 {
4678 sign_flag = 1;
4679 a = ~(a) + 1;
4680 }
4681 a = (unsigned int) (a & 0xf);
4682 /* A positive count specifies a shift to the left;
4683 * A negative count specifies a shift to the right. */
4684
4685 if (sign_flag)
4686 tmp = b >> a;
4687 else
4688 tmp = b << a;
4689
4690 sign_flag = 0; /* Reset sign flag. */
4691 SET_GPR (OP[1], (tmp & 0xffff));
4692 trace_output_16 (sd, tmp);
4693 }
4694
4695 /* ashud. */
4696 void
4697 OP_26_7 (SIM_DESC sd, SIM_CPU *cpu)
4698 {
4699 int32 tmp,b = GPR32 (OP[1]);
4700 uint32 a = OP[0];
4701 trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID);
4702 /* A positive count specifies a shift to the left;
4703 * A negative count specifies a shift to the right. */
4704 if (sign_flag)
4705 tmp = b >> a;
4706 else
4707 tmp = b << a;
4708
4709 sign_flag = 0; /* Reset sign flag. */
4710 SET_GPR32 (OP[1], tmp);
4711 trace_output_32 (sd, tmp);
4712 }
4713
4714 /* ashud. */
4715 void
4716 OP_27_7 (SIM_DESC sd, SIM_CPU *cpu)
4717 {
4718 int32 tmp;
4719 int32 a = OP[0], b = GPR32 (OP[1]);
4720 trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID);
4721 /* A positive count specifies a shift to the left;
4722 * A negative count specifies a shift to the right. */
4723 if (sign_flag)
4724 tmp = b >> a;
4725 else
4726 tmp = b << a;
4727
4728 sign_flag = 0; /* Reset sign flag. */
4729 SET_GPR32 (OP[1], tmp);
4730 trace_output_32 (sd, tmp);
4731 }
4732
4733 /* ashud. */
4734 void
4735 OP_48_8 (SIM_DESC sd, SIM_CPU *cpu)
4736 {
4737 int32 tmp;
4738 int32 a = GPR32 (OP[0]), b = GPR32 (OP[1]);
4739 trace_input ("ashud", OP_REGP, OP_REGP, OP_VOID);
4740
4741 if (a & ((long)1 << 5))
4742 {
4743 sign_flag = 1;
4744 a = ~(a) + 1;
4745 }
4746 a = (unsigned int) (a & 0x1f);
4747 /* A positive count specifies a shift to the left;
4748 * A negative count specifies a shift to the right. */
4749 if (sign_flag)
4750 tmp = b >> a;
4751 else
4752 tmp = b << a;
4753
4754 sign_flag = 0; /* Reset sign flag. */
4755 SET_GPR32 (OP[1], tmp);
4756 trace_output_32 (sd, tmp);
4757 }
4758
4759
4760 /* storm. */
4761 void
4762 OP_16_D (SIM_DESC sd, SIM_CPU *cpu)
4763 {
4764 uint32 addr = GPR (1);
4765 uint16 count = OP[0], reg = 2;
4766 trace_input ("storm", OP_CONSTANT4, OP_VOID, OP_VOID);
4767 if ((addr & 1))
4768 {
4769 trace_output_void (sd);
4770 EXCEPTION (SIM_SIGBUS);
4771 }
4772
4773 while (count)
4774 {
4775 SW (addr, (GPR (reg)));
4776 addr +=2;
4777 --count;
4778 reg++;
4779 if (reg == 6) reg = 8;
4780 };
4781
4782 SET_GPR (1, addr);
4783
4784 trace_output_void (sd);
4785 }
4786
4787
4788 /* stormp. */
4789 void
4790 OP_17_D (SIM_DESC sd, SIM_CPU *cpu)
4791 {
4792 uint32 addr = GPR32 (6);
4793 uint16 count = OP[0], reg = 2;
4794 trace_input ("stormp", OP_CONSTANT4, OP_VOID, OP_VOID);
4795 if ((addr & 1))
4796 {
4797 trace_output_void (sd);
4798 EXCEPTION (SIM_SIGBUS);
4799 }
4800
4801 while (count)
4802 {
4803 SW (addr, (GPR (reg)));
4804 addr +=2;
4805 --count;
4806 reg++;
4807 if (reg == 6) reg = 8;
4808 };
4809
4810 SET_GPR32 (6, addr);
4811 trace_output_void (sd);
4812 }
4813
4814 /* subb. */
4815 void
4816 OP_38_8 (SIM_DESC sd, SIM_CPU *cpu)
4817 {
4818 uint8 a = OP[0];
4819 uint8 b = (GPR (OP[1])) & 0xff;
4820 uint16 tmp = (~a + 1 + b) & 0xff;
4821 trace_input ("subb", OP_CONSTANT4, OP_REG, OP_VOID);
4822 /* see ../common/sim-alu.h for a more extensive discussion on how to
4823 compute the carry/overflow bits. */
4824 SET_PSR_C (tmp > 0xff);
4825 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4826 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4827 trace_output_16 (sd, tmp);
4828 }
4829
4830 /* subb. */
4831 void
4832 OP_38B_C (SIM_DESC sd, SIM_CPU *cpu)
4833 {
4834 uint8 a = OP[0] & 0xFF;
4835 uint8 b = (GPR (OP[1])) & 0xFF;
4836 uint16 tmp = (~a + 1 + b) & 0xFF;
4837 trace_input ("subb", OP_CONSTANT16, OP_REG, OP_VOID);
4838 /* see ../common/sim-alu.h for a more extensive discussion on how to
4839 compute the carry/overflow bits. */
4840 SET_PSR_C (tmp > 0xff);
4841 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4842 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4843 trace_output_16 (sd, tmp);
4844 }
4845
4846 /* subb. */
4847 void
4848 OP_39_8 (SIM_DESC sd, SIM_CPU *cpu)
4849 {
4850 uint8 a = (GPR (OP[0])) & 0xFF;
4851 uint8 b = (GPR (OP[1])) & 0xFF;
4852 uint16 tmp = (~a + 1 + b) & 0xff;
4853 trace_input ("subb", OP_REG, OP_REG, OP_VOID);
4854 /* see ../common/sim-alu.h for a more extensive discussion on how to
4855 compute the carry/overflow bits. */
4856 SET_PSR_C (tmp > 0xff);
4857 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4858 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
4859 trace_output_16 (sd, tmp);
4860 }
4861
4862 /* subw. */
4863 void
4864 OP_3A_8 (SIM_DESC sd, SIM_CPU *cpu)
4865 {
4866 uint16 a = OP[0];
4867 uint16 b = GPR (OP[1]);
4868 uint16 tmp = (~a + 1 + b);
4869 trace_input ("subw", OP_CONSTANT4, OP_REG, OP_VOID);
4870 /* see ../common/sim-alu.h for a more extensive discussion on how to
4871 compute the carry/overflow bits. */
4872 SET_PSR_C (tmp > 0xffff);
4873 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4874 SET_GPR (OP[1], tmp);
4875 trace_output_16 (sd, tmp);
4876 }
4877
4878 /* subw. */
4879 void
4880 OP_3AB_C (SIM_DESC sd, SIM_CPU *cpu)
4881 {
4882 uint16 a = OP[0];
4883 uint16 b = GPR (OP[1]);
4884 uint32 tmp = (~a + 1 + b);
4885 trace_input ("subw", OP_CONSTANT16, OP_REG, OP_VOID);
4886 /* see ../common/sim-alu.h for a more extensive discussion on how to
4887 compute the carry/overflow bits. */
4888 SET_PSR_C (tmp > 0xffff);
4889 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4890 SET_GPR (OP[1], tmp & 0xffff);
4891 trace_output_16 (sd, tmp);
4892 }
4893
4894 /* subw. */
4895 void
4896 OP_3B_8 (SIM_DESC sd, SIM_CPU *cpu)
4897 {
4898 uint16 a = GPR (OP[0]);
4899 uint16 b = GPR (OP[1]);
4900 uint32 tmp = (~a + 1 + b);
4901 trace_input ("subw", OP_REG, OP_REG, OP_VOID);
4902 /* see ../common/sim-alu.h for a more extensive discussion on how to
4903 compute the carry/overflow bits. */
4904 SET_PSR_C (tmp > 0xffff);
4905 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4906 SET_GPR (OP[1], tmp & 0xffff);
4907 trace_output_16 (sd, tmp);
4908 }
4909
4910 /* subcb. */
4911 void
4912 OP_3C_8 (SIM_DESC sd, SIM_CPU *cpu)
4913 {
4914 uint8 a = OP[0];
4915 uint8 b = (GPR (OP[1])) & 0xff;
4916 //uint16 tmp1 = a + 1;
4917 uint16 tmp1 = a + (PSR_C);
4918 uint16 tmp = (~tmp1 + 1 + b);
4919 trace_input ("subcb", OP_CONSTANT4, OP_REG, OP_VOID);
4920 /* see ../common/sim-alu.h for a more extensive discussion on how to
4921 compute the carry/overflow bits. */
4922 SET_PSR_C (tmp > 0xff);
4923 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4924 SET_GPR (OP[1], tmp);
4925 trace_output_16 (sd, tmp);
4926 }
4927
4928 /* subcb. */
4929 void
4930 OP_3CB_C (SIM_DESC sd, SIM_CPU *cpu)
4931 {
4932 uint16 a = OP[0];
4933 uint16 b = (GPR (OP[1])) & 0xff;
4934 //uint16 tmp1 = a + 1;
4935 uint16 tmp1 = a + (PSR_C);
4936 uint16 tmp = (~tmp1 + 1 + b);
4937 trace_input ("subcb", OP_CONSTANT16, OP_REG, OP_VOID);
4938 /* see ../common/sim-alu.h for a more extensive discussion on how to
4939 compute the carry/overflow bits. */
4940 SET_PSR_C (tmp > 0xff);
4941 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4942 SET_GPR (OP[1], tmp);
4943 trace_output_16 (sd, tmp);
4944 }
4945
4946 /* subcb. */
4947 void
4948 OP_3D_8 (SIM_DESC sd, SIM_CPU *cpu)
4949 {
4950 uint16 a = (GPR (OP[0])) & 0xff;
4951 uint16 b = (GPR (OP[1])) & 0xff;
4952 uint16 tmp1 = a + (PSR_C);
4953 uint16 tmp = (~tmp1 + 1 + b);
4954 trace_input ("subcb", OP_REG, OP_REG, OP_VOID);
4955 /* see ../common/sim-alu.h for a more extensive discussion on how to
4956 compute the carry/overflow bits. */
4957 SET_PSR_C (tmp > 0xff);
4958 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80)));
4959 SET_GPR (OP[1], tmp);
4960 trace_output_16 (sd, tmp);
4961 }
4962
4963 /* subcw. */
4964 void
4965 OP_3E_8 (SIM_DESC sd, SIM_CPU *cpu)
4966 {
4967 uint16 a = OP[0], b = (GPR (OP[1]));
4968 uint16 tmp1 = a + (PSR_C);
4969 uint16 tmp = (~tmp1 + 1 + b);
4970 trace_input ("subcw", OP_CONSTANT4, OP_REG, OP_VOID);
4971 /* see ../common/sim-alu.h for a more extensive discussion on how to
4972 compute the carry/overflow bits. */
4973 SET_PSR_C (tmp > 0xffff);
4974 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4975 SET_GPR (OP[1], tmp);
4976 trace_output_16 (sd, tmp);
4977 }
4978
4979 /* subcw. */
4980 void
4981 OP_3EB_C (SIM_DESC sd, SIM_CPU *cpu)
4982 {
4983 int16 a = OP[0];
4984 uint16 b = GPR (OP[1]);
4985 uint16 tmp1 = a + (PSR_C);
4986 uint16 tmp = (~tmp1 + 1 + b);
4987 trace_input ("subcw", OP_CONSTANT16, OP_REG, OP_VOID);
4988 /* see ../common/sim-alu.h for a more extensive discussion on how to
4989 compute the carry/overflow bits. */
4990 SET_PSR_C (tmp > 0xffff);
4991 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
4992 SET_GPR (OP[1], tmp);
4993 trace_output_16 (sd, tmp);
4994 }
4995
4996 /* subcw. */
4997 void
4998 OP_3F_8 (SIM_DESC sd, SIM_CPU *cpu)
4999 {
5000 uint16 a = (GPR (OP[0])), b = (GPR (OP[1]));
5001 uint16 tmp1 = a + (PSR_C);
5002 uint16 tmp = (~tmp1 + 1 + b);
5003 trace_input ("subcw", OP_REG, OP_REG, OP_VOID);
5004 /* see ../common/sim-alu.h for a more extensive discussion on how to
5005 compute the carry/overflow bits. */
5006 SET_PSR_C (tmp > 0xffff);
5007 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000)));
5008 SET_GPR (OP[1], tmp);
5009 trace_output_16 (sd, tmp);
5010 }
5011
5012 /* subd. */
5013 void
5014 OP_3_C (SIM_DESC sd, SIM_CPU *cpu)
5015 {
5016 int32 a = OP[0];
5017 uint32 b = GPR32 (OP[1]);
5018 uint32 tmp = (~a + 1 + b);
5019 trace_input ("subd", OP_CONSTANT32, OP_REGP, OP_VOID);
5020 /* see ../common/sim-alu.h for a more extensive discussion on how to
5021 compute the carry/overflow bits. */
5022 SET_PSR_C (tmp > 0xffffffff);
5023 SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) &&
5024 ((b & 0x80000000) != (tmp & 0x80000000)));
5025 SET_GPR32 (OP[1], tmp);
5026 trace_output_32 (sd, tmp);
5027 }
5028
5029 /* subd. */
5030 void
5031 OP_14C_14 (SIM_DESC sd, SIM_CPU *cpu)
5032 {
5033 uint32 a = GPR32 (OP[0]);
5034 uint32 b = GPR32 (OP[1]);
5035 uint32 tmp = (~a + 1 + b);
5036 trace_input ("subd", OP_REGP, OP_REGP, OP_VOID);
5037 /* see ../common/sim-alu.h for a more extensive discussion on how to
5038 compute the carry/overflow bits. */
5039 SET_PSR_C (tmp > 0xffffffff);
5040 SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) &&
5041 ((b & 0x80000000) != (tmp & 0x80000000)));
5042 SET_GPR32 (OP[1], tmp);
5043 trace_output_32 (sd, tmp);
5044 }
5045
5046 /* excp. */
5047 void
5048 OP_C_C (SIM_DESC sd, SIM_CPU *cpu)
5049 {
5050 host_callback *cb = STATE_CALLBACK (sd);
5051 uint32 tmp;
5052 uint16 a;
5053 trace_input ("excp", OP_CONSTANT4, OP_VOID, OP_VOID);
5054 switch (OP[0])
5055 {
5056 default:
5057 #if (DEBUG & DEBUG_TRAP) == 0
5058 {
5059 #if 0
5060 uint16 vec = OP[0] + TRAP_VECTOR_START;
5061 SET_BPC (PC + 1);
5062 SET_BPSR (PSR);
5063 SET_PSR (PSR & PSR_SM_BIT);
5064 JMP (vec);
5065 break;
5066 #endif
5067 }
5068 #else /* if debugging use trap to print registers */
5069 {
5070 int i;
5071 static int first_time = 1;
5072
5073 if (first_time)
5074 {
5075 first_time = 0;
5076 sim_io_printf (sd, "Trap # PC ");
5077 for (i = 0; i < 16; i++)
5078 sim_io_printf (sd, " %sr%d", (i > 9) ? "" : " ", i);
5079 sim_io_printf (sd, " a0 a1 f0 f1 c\n");
5080 }
5081
5082 sim_io_printf (sd, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
5083
5084 for (i = 0; i < 16; i++)
5085 sim_io_printf (sd, " %.4x", (int) GPR (i));
5086
5087 for (i = 0; i < 2; i++)
5088 sim_io_printf (sd, " %.2x%.8lx",
5089 ((int)(ACC (i) >> 32) & 0xff),
5090 ((unsigned long) ACC (i)) & 0xffffffff);
5091
5092 sim_io_printf (sd, " %d %d %d\n",
5093 PSR_F != 0, PSR_F != 0, PSR_C != 0);
5094 sim_io_flush_stdout (sd);
5095 break;
5096 }
5097 #endif
5098 case 8: /* new system call trap */
5099 /* Trap 8 is used for simulating low-level I/O */
5100 {
5101 unsigned32 result = 0;
5102 errno = 0;
5103
5104 /* Registers passed to trap 0. */
5105
5106 #define FUNC GPR (0) /* function number. */
5107 #define PARM1 GPR (2) /* optional parm 1. */
5108 #define PARM2 GPR (3) /* optional parm 2. */
5109 #define PARM3 GPR (4) /* optional parm 3. */
5110 #define PARM4 GPR (5) /* optional parm 4. */
5111
5112 /* Registers set by trap 0 */
5113
5114 #define RETVAL(X) do { result = (0xffff & (X));SET_GPR (0, result);} while (0)
5115 #define RETVAL32(X) do { result = (X); SET_GPR32 (0, result);} while (0)
5116 #define RETERR(X) SET_GPR (4, (X)) /* return error code. */
5117
5118 /* Turn a pointer in a register into a pointer into real memory. */
5119
5120 #define MEMPTR(x) sim_core_trans_addr (sd, cpu, read_map, x)
5121
5122 switch (FUNC)
5123 {
5124 #if !defined(__GO32__) && !defined(_WIN32)
5125 #ifdef TARGET_SYS_fork
5126 case TARGET_SYS_fork:
5127 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
5128 RETVAL (fork ());
5129 trace_output_16 (sd, result);
5130 break;
5131 #endif
5132
5133 #define getpid() 47
5134 case TARGET_SYS_getpid:
5135 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
5136 RETVAL (getpid ());
5137 trace_output_16 (sd, result);
5138 break;
5139
5140 case TARGET_SYS_kill:
5141 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
5142 if (PARM1 == getpid ())
5143 {
5144 trace_output_void (sd);
5145 EXCEPTION (PARM2);
5146 }
5147 else
5148 {
5149 int os_sig = -1;
5150 switch (PARM2)
5151 {
5152 #ifdef SIGHUP
5153 case 1: os_sig = SIGHUP; break;
5154 #endif
5155 #ifdef SIGINT
5156 case 2: os_sig = SIGINT; break;
5157 #endif
5158 #ifdef SIGQUIT
5159 case 3: os_sig = SIGQUIT; break;
5160 #endif
5161 #ifdef SIGILL
5162 case 4: os_sig = SIGILL; break;
5163 #endif
5164 #ifdef SIGTRAP
5165 case 5: os_sig = SIGTRAP; break;
5166 #endif
5167 #ifdef SIGABRT
5168 case 6: os_sig = SIGABRT; break;
5169 #elif defined(SIGIOT)
5170 case 6: os_sig = SIGIOT; break;
5171 #endif
5172 #ifdef SIGEMT
5173 case 7: os_sig = SIGEMT; break;
5174 #endif
5175 #ifdef SIGFPE
5176 case 8: os_sig = SIGFPE; break;
5177 #endif
5178 #ifdef SIGKILL
5179 case 9: os_sig = SIGKILL; break;
5180 #endif
5181 #ifdef SIGBUS
5182 case 10: os_sig = SIGBUS; break;
5183 #endif
5184 #ifdef SIGSEGV
5185 case 11: os_sig = SIGSEGV; break;
5186 #endif
5187 #ifdef SIGSYS
5188 case 12: os_sig = SIGSYS; break;
5189 #endif
5190 #ifdef SIGPIPE
5191 case 13: os_sig = SIGPIPE; break;
5192 #endif
5193 #ifdef SIGALRM
5194 case 14: os_sig = SIGALRM; break;
5195 #endif
5196 #ifdef SIGTERM
5197 case 15: os_sig = SIGTERM; break;
5198 #endif
5199 #ifdef SIGURG
5200 case 16: os_sig = SIGURG; break;
5201 #endif
5202 #ifdef SIGSTOP
5203 case 17: os_sig = SIGSTOP; break;
5204 #endif
5205 #ifdef SIGTSTP
5206 case 18: os_sig = SIGTSTP; break;
5207 #endif
5208 #ifdef SIGCONT
5209 case 19: os_sig = SIGCONT; break;
5210 #endif
5211 #ifdef SIGCHLD
5212 case 20: os_sig = SIGCHLD; break;
5213 #elif defined(SIGCLD)
5214 case 20: os_sig = SIGCLD; break;
5215 #endif
5216 #ifdef SIGTTIN
5217 case 21: os_sig = SIGTTIN; break;
5218 #endif
5219 #ifdef SIGTTOU
5220 case 22: os_sig = SIGTTOU; break;
5221 #endif
5222 #ifdef SIGIO
5223 case 23: os_sig = SIGIO; break;
5224 #elif defined (SIGPOLL)
5225 case 23: os_sig = SIGPOLL; break;
5226 #endif
5227 #ifdef SIGXCPU
5228 case 24: os_sig = SIGXCPU; break;
5229 #endif
5230 #ifdef SIGXFSZ
5231 case 25: os_sig = SIGXFSZ; break;
5232 #endif
5233 #ifdef SIGVTALRM
5234 case 26: os_sig = SIGVTALRM; break;
5235 #endif
5236 #ifdef SIGPROF
5237 case 27: os_sig = SIGPROF; break;
5238 #endif
5239 #ifdef SIGWINCH
5240 case 28: os_sig = SIGWINCH; break;
5241 #endif
5242 #ifdef SIGLOST
5243 case 29: os_sig = SIGLOST; break;
5244 #endif
5245 #ifdef SIGUSR1
5246 case 30: os_sig = SIGUSR1; break;
5247 #endif
5248 #ifdef SIGUSR2
5249 case 31: os_sig = SIGUSR2; break;
5250 #endif
5251 }
5252
5253 if (os_sig == -1)
5254 {
5255 trace_output_void (sd);
5256 sim_io_printf (sd, "Unknown signal %d\n", PARM2);
5257 sim_io_flush_stdout (sd);
5258 EXCEPTION (SIM_SIGILL);
5259 }
5260 else
5261 {
5262 RETVAL (kill (PARM1, PARM2));
5263 trace_output_16 (sd, result);
5264 }
5265 }
5266 break;
5267
5268 #ifdef TARGET_SYS_execve
5269 case TARGET_SYS_execve:
5270 trace_input ("<execve>", OP_VOID, OP_VOID, OP_VOID);
5271 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2<<16|PARM3),
5272 (char **)MEMPTR (PARM4)));
5273 trace_output_16 (sd, result);
5274 break;
5275 #endif
5276
5277 #ifdef TARGET_SYS_execv
5278 case TARGET_SYS_execv:
5279 trace_input ("<execv>", OP_VOID, OP_VOID, OP_VOID);
5280 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
5281 trace_output_16 (sd, result);
5282 break;
5283 #endif
5284
5285 #ifdef TARGET_SYS_pipe
5286 case TARGET_SYS_pipe:
5287 {
5288 reg_t buf;
5289 int host_fd[2];
5290
5291 trace_input ("<pipe>", OP_VOID, OP_VOID, OP_VOID);
5292 buf = PARM1;
5293 RETVAL (pipe (host_fd));
5294 SW (buf, host_fd[0]);
5295 buf += sizeof(uint16);
5296 SW (buf, host_fd[1]);
5297 trace_output_16 (sd, result);
5298 }
5299 break;
5300 #endif
5301
5302 #ifdef TARGET_SYS_wait
5303 case TARGET_SYS_wait:
5304 {
5305 int status;
5306 trace_input ("<wait>", OP_REG, OP_VOID, OP_VOID);
5307 RETVAL (wait (&status));
5308 if (PARM1)
5309 SW (PARM1, status);
5310 trace_output_16 (sd, result);
5311 }
5312 break;
5313 #endif
5314 #else
5315 case TARGET_SYS_getpid:
5316 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
5317 RETVAL (1);
5318 trace_output_16 (sd, result);
5319 break;
5320
5321 case TARGET_SYS_kill:
5322 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
5323 trace_output_void (sd);
5324 EXCEPTION (PARM2);
5325 break;
5326 #endif
5327
5328 case TARGET_SYS_read:
5329 trace_input ("<read>", OP_REG, OP_MEMREF, OP_REG);
5330 RETVAL (cb->read (cb, PARM1,
5331 MEMPTR (((unsigned long)PARM3 << 16)
5332 | ((unsigned long)PARM2)), PARM4));
5333 trace_output_16 (sd, result);
5334 break;
5335
5336 case TARGET_SYS_write:
5337 trace_input ("<write>", OP_REG, OP_MEMREF, OP_REG);
5338 RETVAL ((int)cb->write (cb, PARM1,
5339 MEMPTR (((unsigned long)PARM3 << 16)
5340 | PARM2), PARM4));
5341 trace_output_16 (sd, result);
5342 break;
5343
5344 case TARGET_SYS_lseek:
5345 trace_input ("<lseek>", OP_REG, OP_REGP, OP_REG);
5346 RETVAL32 (cb->lseek (cb, PARM1, ((((long) PARM3) << 16) | PARM2),
5347 PARM4));
5348 trace_output_32 (sd, result);
5349 break;
5350
5351 case TARGET_SYS_close:
5352 trace_input ("<close>", OP_REG, OP_VOID, OP_VOID);
5353 RETVAL (cb->close (cb, PARM1));
5354 trace_output_16 (sd, result);
5355 break;
5356
5357 case TARGET_SYS_open:
5358 trace_input ("<open>", OP_MEMREF, OP_REG, OP_VOID);
5359 RETVAL32 (cb->open (cb, MEMPTR ((((unsigned long)PARM2) << 16)
5360 | PARM1), PARM3));
5361 trace_output_32 (sd, result);
5362 break;
5363
5364 #ifdef TARGET_SYS_rename
5365 case TARGET_SYS_rename:
5366 trace_input ("<rename>", OP_MEMREF, OP_MEMREF, OP_VOID);
5367 RETVAL (cb->rename (cb, MEMPTR ((((unsigned long)PARM2) << 16) | PARM1),
5368 MEMPTR ((((unsigned long)PARM4) << 16) | PARM3)));
5369 trace_output_16 (sd, result);
5370 break;
5371 #endif
5372
5373 case 0x408: /* REVISIT: Added a dummy getenv call. */
5374 trace_input ("<getenv>", OP_MEMREF, OP_MEMREF, OP_VOID);
5375 RETVAL32 (0);
5376 trace_output_32 (sd, result);
5377 break;
5378
5379 case TARGET_SYS_exit:
5380 trace_input ("<exit>", OP_VOID, OP_VOID, OP_VOID);
5381 trace_output_void (sd);
5382 sim_engine_halt (sd, cpu, NULL, PC, sim_exited, GPR (2));
5383 break;
5384
5385 case TARGET_SYS_unlink:
5386 trace_input ("<unlink>", OP_MEMREF, OP_VOID, OP_VOID);
5387 RETVAL (cb->unlink (cb, MEMPTR (((unsigned long)PARM2 << 16) | PARM1)));
5388 trace_output_16 (sd, result);
5389 break;
5390
5391
5392 #ifdef TARGET_SYS_stat
5393 case TARGET_SYS_stat:
5394 trace_input ("<stat>", OP_VOID, OP_VOID, OP_VOID);
5395 /* stat system call. */
5396 {
5397 struct stat host_stat;
5398 reg_t buf;
5399
5400 RETVAL (stat (MEMPTR ((((unsigned long)PARM2) << 16)|PARM1), &host_stat));
5401
5402 buf = PARM2;
5403
5404 /* The hard-coded offsets and sizes were determined by using
5405 * the CR16 compiler on a test program that used struct stat.
5406 */
5407 SW (buf, host_stat.st_dev);
5408 SW (buf+2, host_stat.st_ino);
5409 SW (buf+4, host_stat.st_mode);
5410 SW (buf+6, host_stat.st_nlink);
5411 SW (buf+8, host_stat.st_uid);
5412 SW (buf+10, host_stat.st_gid);
5413 SW (buf+12, host_stat.st_rdev);
5414 SLW (buf+16, host_stat.st_size);
5415 SLW (buf+20, host_stat.st_atime);
5416 SLW (buf+28, host_stat.st_mtime);
5417 SLW (buf+36, host_stat.st_ctime);
5418 }
5419 trace_output_16 (sd, result);
5420 break;
5421 #endif
5422
5423 #ifdef TARGET_SYS_chown
5424 case TARGET_SYS_chown:
5425 trace_input ("<chown>", OP_VOID, OP_VOID, OP_VOID);
5426 RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
5427 trace_output_16 (sd, result);
5428 break;
5429 #endif
5430
5431 case TARGET_SYS_chmod:
5432 trace_input ("<chmod>", OP_VOID, OP_VOID, OP_VOID);
5433 RETVAL (chmod (MEMPTR (PARM1), PARM2));
5434 trace_output_16 (sd, result);
5435 break;
5436
5437 #ifdef TARGET_SYS_utime
5438 case TARGET_SYS_utime:
5439 trace_input ("<utime>", OP_REG, OP_REG, OP_REG);
5440 /* Cast the second argument to void *, to avoid type mismatch
5441 if a prototype is present. */
5442 RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
5443 trace_output_16 (sd, result);
5444 break;
5445 #endif
5446
5447 #ifdef TARGET_SYS_time
5448 case TARGET_SYS_time:
5449 trace_input ("<time>", OP_VOID, OP_VOID, OP_REG);
5450 RETVAL32 (time (NULL));
5451 trace_output_32 (sd, result);
5452 break;
5453 #endif
5454
5455 default:
5456 a = OP[0];
5457 switch (a)
5458 {
5459 case TRAP_BREAKPOINT:
5460 tmp = (PC);
5461 JMP(tmp);
5462 trace_output_void (sd);
5463 EXCEPTION (SIM_SIGTRAP);
5464 break;
5465 case SIGTRAP: /* supervisor call ? */
5466 trace_output_void (sd);
5467 sim_engine_halt (sd, cpu, NULL, PC, sim_exited, GPR (2));
5468 break;
5469 default:
5470 cb->error (cb, "Unknown syscall %d", FUNC);
5471 break;
5472 }
5473 }
5474 if ((uint16) result == (uint16) -1)
5475 RETERR (cb->get_errno (cb));
5476 else
5477 RETERR (0);
5478 break;
5479 }
5480 }
5481 }
5482
5483
5484 /* push. */
5485 void
5486 OP_3_9 (SIM_DESC sd, SIM_CPU *cpu)
5487 {
5488 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5489 uint32 tmp, sp_addr = (GPR32 (15)) - (a * 2) - 4, is_regp = 0;
5490 trace_input ("push", OP_CONSTANT3, OP_REG, OP_REG);
5491
5492 for (; i < a; ++i)
5493 {
5494 if ((b+i) <= 11)
5495 {
5496 SW (sp_addr, (GPR (b+i)));
5497 sp_addr +=2;
5498 }
5499 else
5500 {
5501 if (is_regp == 0)
5502 tmp = (GPR32 (b+i));
5503 else
5504 tmp = (GPR32 (b+i-1));
5505
5506 if ((a-i) > 1)
5507 {
5508 SLW (sp_addr, tmp);
5509 sp_addr +=4;
5510 }
5511 else
5512 {
5513 SW (sp_addr, tmp);
5514 sp_addr +=2;
5515 }
5516 ++i;
5517 is_regp = 1;
5518 }
5519 }
5520
5521 sp_addr +=4;
5522
5523 /* Store RA address. */
5524 tmp = (GPR32 (14));
5525 SLW(sp_addr,tmp);
5526
5527 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5528 SET_GPR32 (15, sp_addr); /* Update SP address. */
5529
5530 trace_output_void (sd);
5531 }
5532
5533 /* push. */
5534 void
5535 OP_1_8 (SIM_DESC sd, SIM_CPU *cpu)
5536 {
5537 uint32 sp_addr, tmp, is_regp = 0;
5538 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5539 trace_input ("push", OP_CONSTANT3, OP_REG, OP_VOID);
5540
5541 if (c == 1)
5542 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5543 else
5544 sp_addr = (GPR32 (15)) - (a * 2);
5545
5546 for (; i < a; ++i)
5547 {
5548 if ((b+i) <= 11)
5549 {
5550 SW (sp_addr, (GPR (b+i)));
5551 sp_addr +=2;
5552 }
5553 else
5554 {
5555 if (is_regp == 0)
5556 tmp = (GPR32 (b+i));
5557 else
5558 tmp = (GPR32 (b+i-1));
5559
5560 if ((a-i) > 1)
5561 {
5562 SLW (sp_addr, tmp);
5563 sp_addr +=4;
5564 }
5565 else
5566 {
5567 SW (sp_addr, tmp);
5568 sp_addr +=2;
5569 }
5570 ++i;
5571 is_regp = 1;
5572 }
5573 }
5574
5575 if (c == 1)
5576 {
5577 /* Store RA address. */
5578 tmp = (GPR32 (14));
5579 SLW(sp_addr,tmp);
5580 sp_addr = (GPR32 (15)) - (a * 2) - 4;
5581 }
5582 else
5583 sp_addr = (GPR32 (15)) - (a * 2);
5584
5585 SET_GPR32 (15, sp_addr); /* Update SP address. */
5586
5587 trace_output_void (sd);
5588 }
5589
5590
5591 /* push. */
5592 void
5593 OP_11E_10 (SIM_DESC sd, SIM_CPU *cpu)
5594 {
5595 uint32 sp_addr = (GPR32 (15)), tmp;
5596 trace_input ("push", OP_VOID, OP_VOID, OP_VOID);
5597 tmp = (GPR32 (14));
5598 SLW(sp_addr-4,tmp); /* Store RA address. */
5599 SET_GPR32 (15, (sp_addr - 4)); /* Update SP address. */
5600 trace_output_void (sd);
5601 }
5602
5603
5604 /* pop. */
5605 void
5606 OP_5_9 (SIM_DESC sd, SIM_CPU *cpu)
5607 {
5608 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5609 uint32 tmp, sp_addr = (GPR32 (15)), is_regp = 0;;
5610 trace_input ("pop", OP_CONSTANT3, OP_REG, OP_REG);
5611
5612 for (; i < a; ++i)
5613 {
5614 if ((b+i) <= 11)
5615 {
5616 SET_GPR ((b+i), RW(sp_addr));
5617 sp_addr +=2;
5618 }
5619 else
5620 {
5621 if ((a-i) > 1)
5622 {
5623 tmp = RLW(sp_addr);
5624 sp_addr +=4;
5625 }
5626 else
5627 {
5628 tmp = RW(sp_addr);
5629 sp_addr +=2;
5630
5631 if (is_regp == 0)
5632 tmp = (tmp << 16) | (GPR32 (b+i));
5633 else
5634 tmp = (tmp << 16) | (GPR32 (b+i-1));
5635 }
5636
5637 if (is_regp == 0)
5638 SET_GPR32 ((b+i), (((tmp & 0xffff) << 16)
5639 | ((tmp >> 16) & 0xffff)));
5640 else
5641 SET_GPR32 ((b+i-1), (((tmp & 0xffff) << 16)
5642 | ((tmp >> 16) & 0xffff)));
5643
5644 ++i;
5645 is_regp = 1;
5646 }
5647 }
5648
5649 tmp = RLW(sp_addr); /* store RA also. */
5650 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5651
5652 SET_GPR32 (15, (sp_addr + 4)); /* Update SP address. */
5653
5654 trace_output_void (sd);
5655 }
5656
5657 /* pop. */
5658 void
5659 OP_2_8 (SIM_DESC sd, SIM_CPU *cpu)
5660 {
5661 uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0;
5662 uint32 tmp, sp_addr = (GPR32 (15)), is_regp = 0;
5663 trace_input ("pop", OP_CONSTANT3, OP_REG, OP_VOID);
5664
5665 for (; i < a; ++i)
5666 {
5667 if ((b+i) <= 11)
5668 {
5669 SET_GPR ((b+i), RW(sp_addr));
5670 sp_addr +=2;
5671 }
5672 else
5673 {
5674 if ((a-i) > 1)
5675 {
5676 tmp = RLW(sp_addr);
5677 sp_addr +=4;
5678 }
5679 else
5680 {
5681 tmp = RW(sp_addr);
5682 sp_addr +=2;
5683
5684 if (is_regp == 0)
5685 tmp = ((tmp << 16) & 0xffffffff) | (GPR32 (b+i));
5686 else
5687 tmp = ((tmp << 16) & 0xffffffff) | (GPR32 (b+i-1));
5688 }
5689
5690 if (is_regp == 0)
5691 SET_GPR32 ((b+i), (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5692 else
5693 SET_GPR32 ((b+i-1), (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5694 ++i;
5695 is_regp = 1;
5696 }
5697 }
5698
5699 if (c == 1)
5700 {
5701 tmp = RLW(sp_addr); /* Store RA Reg. */
5702 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5703 sp_addr +=4;
5704 }
5705
5706 SET_GPR32 (15, sp_addr); /* Update SP address. */
5707
5708 trace_output_void (sd);
5709 }
5710
5711 /* pop. */
5712 void
5713 OP_21E_10 (SIM_DESC sd, SIM_CPU *cpu)
5714 {
5715 uint32 sp_addr = GPR32 (15);
5716 uint32 tmp;
5717 trace_input ("pop", OP_VOID, OP_VOID, OP_VOID);
5718
5719 tmp = RLW(sp_addr);
5720 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff)));
5721 SET_GPR32 (15, (sp_addr+4)); /* Update SP address. */
5722
5723 trace_output_void (sd);
5724 }
5725
5726 /* popret. */
5727 void
5728 OP_7_9 (SIM_DESC sd, SIM_CPU *cpu)
5729 {
5730 uint16 a = OP[0], b = OP[1];
5731 trace_input ("popret", OP_CONSTANT3, OP_REG, OP_REG);
5732 OP_5_9 (sd, cpu);
5733 JMP(((GPR32(14)) << 1) & 0xffffff);
5734
5735 trace_output_void (sd);
5736 }
5737
5738 /* popret. */
5739 void
5740 OP_3_8 (SIM_DESC sd, SIM_CPU *cpu)
5741 {
5742 uint16 a = OP[0], b = OP[1];
5743 trace_input ("popret", OP_CONSTANT3, OP_REG, OP_VOID);
5744 OP_2_8 (sd, cpu);
5745 JMP(((GPR32(14)) << 1) & 0xffffff);
5746
5747 trace_output_void (sd);
5748 }
5749
5750 /* popret. */
5751 void
5752 OP_31E_10 (SIM_DESC sd, SIM_CPU *cpu)
5753 {
5754 uint32 tmp;
5755 trace_input ("popret", OP_VOID, OP_VOID, OP_VOID);
5756 OP_21E_10 (sd, cpu);
5757 tmp = (((GPR32(14)) << 1) & 0xffffff);
5758 /* If the resulting PC value is less than 0x00_0000 or greater
5759 than 0xFF_FFFF, this instruction causes an IAD trap.*/
5760
5761 if ((tmp < 0x0) || (tmp > 0xFFFFFF))
5762 {
5763 trace_output_void (sd);
5764 EXCEPTION (SIM_SIGBUS);
5765 }
5766 else
5767 JMP (tmp);
5768
5769 trace_output_32 (sd, tmp);
5770 }
5771
5772
5773 /* cinv[i]. */
5774 void
5775 OP_A_10 (SIM_DESC sd, SIM_CPU *cpu)
5776 {
5777 trace_input ("cinv[i]", OP_VOID, OP_VOID, OP_VOID);
5778 SET_PSR_I (1);
5779 trace_output_void (sd);
5780 }
5781
5782 /* cinv[i,u]. */
5783 void
5784 OP_B_10 (SIM_DESC sd, SIM_CPU *cpu)
5785 {
5786 trace_input ("cinv[i,u]", OP_VOID, OP_VOID, OP_VOID);
5787 SET_PSR_I (1);
5788 trace_output_void (sd);
5789 }
5790
5791 /* cinv[d]. */
5792 void
5793 OP_C_10 (SIM_DESC sd, SIM_CPU *cpu)
5794 {
5795 trace_input ("cinv[d]", OP_VOID, OP_VOID, OP_VOID);
5796 SET_PSR_I (1);
5797 trace_output_void (sd);
5798 }
5799
5800 /* cinv[d,u]. */
5801 void
5802 OP_D_10 (SIM_DESC sd, SIM_CPU *cpu)
5803 {
5804 trace_input ("cinv[i,u]", OP_VOID, OP_VOID, OP_VOID);
5805 SET_PSR_I (1);
5806 trace_output_void (sd);
5807 }
5808
5809 /* cinv[d,i]. */
5810 void
5811 OP_E_10 (SIM_DESC sd, SIM_CPU *cpu)
5812 {
5813 trace_input ("cinv[d,i]", OP_VOID, OP_VOID, OP_VOID);
5814 SET_PSR_I (1);
5815 trace_output_void (sd);
5816 }
5817
5818 /* cinv[d,i,u]. */
5819 void
5820 OP_F_10 (SIM_DESC sd, SIM_CPU *cpu)
5821 {
5822 trace_input ("cinv[d,i,u]", OP_VOID, OP_VOID, OP_VOID);
5823 SET_PSR_I (1);
5824 trace_output_void (sd);
5825 }
5826
5827 /* retx. */
5828 void
5829 OP_3_10 (SIM_DESC sd, SIM_CPU *cpu)
5830 {
5831 trace_input ("retx", OP_VOID, OP_VOID, OP_VOID);
5832 SET_PSR_I (1);
5833 trace_output_void (sd);
5834 }
5835
5836 /* di. */
5837 void
5838 OP_4_10 (SIM_DESC sd, SIM_CPU *cpu)
5839 {
5840 trace_input ("di", OP_VOID, OP_VOID, OP_VOID);
5841 SET_PSR_I (1);
5842 trace_output_void (sd);
5843 }
5844
5845 /* ei. */
5846 void
5847 OP_5_10 (SIM_DESC sd, SIM_CPU *cpu)
5848 {
5849 trace_input ("ei", OP_VOID, OP_VOID, OP_VOID);
5850 SET_PSR_I (1);
5851 trace_output_void (sd);
5852 }
5853
5854 /* wait. */
5855 void
5856 OP_6_10 (SIM_DESC sd, SIM_CPU *cpu)
5857 {
5858 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
5859 trace_output_void (sd);
5860 EXCEPTION (SIM_SIGTRAP);
5861 }
5862
5863 /* ewait. */
5864 void
5865 OP_7_10 (SIM_DESC sd, SIM_CPU *cpu)
5866 {
5867 trace_input ("ewait", OP_VOID, OP_VOID, OP_VOID);
5868 SET_PSR_I (1);
5869 trace_output_void (sd);
5870 }
5871
5872 /* xorb. */
5873 void
5874 OP_28_8 (SIM_DESC sd, SIM_CPU *cpu)
5875 {
5876 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
5877 trace_input ("xorb", OP_CONSTANT4, OP_REG, OP_VOID);
5878 tmp = a ^ b;
5879 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
5880 trace_output_16 (sd, tmp);
5881 }
5882
5883 /* xorb. */
5884 void
5885 OP_28B_C (SIM_DESC sd, SIM_CPU *cpu)
5886 {
5887 uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff;
5888 trace_input ("xorb", OP_CONSTANT16, OP_REG, OP_VOID);
5889 tmp = a ^ b;
5890 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
5891 trace_output_16 (sd, tmp);
5892 }
5893
5894 /* xorb. */
5895 void
5896 OP_29_8 (SIM_DESC sd, SIM_CPU *cpu)
5897 {
5898 uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff;
5899 trace_input ("xorb", OP_REG, OP_REG, OP_VOID);
5900 tmp = a ^ b;
5901 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00)));
5902 trace_output_16 (sd, tmp);
5903 }
5904
5905 /* xorw. */
5906 void
5907 OP_2A_8 (SIM_DESC sd, SIM_CPU *cpu)
5908 {
5909 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
5910 trace_input ("xorw", OP_CONSTANT4, OP_REG, OP_VOID);
5911 tmp = a ^ b;
5912 SET_GPR (OP[1], tmp);
5913 trace_output_16 (sd, tmp);
5914 }
5915
5916 /* xorw. */
5917 void
5918 OP_2AB_C (SIM_DESC sd, SIM_CPU *cpu)
5919 {
5920 uint16 tmp, a = (OP[0]), b = (GPR (OP[1]));
5921 trace_input ("xorw", OP_CONSTANT16, OP_REG, OP_VOID);
5922 tmp = a ^ b;
5923 SET_GPR (OP[1], tmp);
5924 trace_output_16 (sd, tmp);
5925 }
5926
5927 /* xorw. */
5928 void
5929 OP_2B_8 (SIM_DESC sd, SIM_CPU *cpu)
5930 {
5931 uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1]));
5932 trace_input ("xorw", OP_REG, OP_REG, OP_VOID);
5933 tmp = a ^ b;
5934 SET_GPR (OP[1], tmp);
5935 trace_output_16 (sd, tmp);
5936 }
5937
5938 /*REVISIT FOR LPR/SPR . */
5939
5940 /* lpr. */
5941 void
5942 OP_140_14 (SIM_DESC sd, SIM_CPU *cpu)
5943 {
5944 uint16 a = GPR (OP[0]);
5945 trace_input ("lpr", OP_REG, OP_REG, OP_VOID);
5946 SET_CREG (OP[1], a);
5947 trace_output_16 (sd, a);
5948 }
5949
5950 /* lprd. */
5951 void
5952 OP_141_14 (SIM_DESC sd, SIM_CPU *cpu)
5953 {
5954 uint32 a = GPR32 (OP[0]);
5955 trace_input ("lprd", OP_REGP, OP_REG, OP_VOID);
5956 SET_CREG (OP[1], a);
5957 trace_output_flag (sd);
5958 }
5959
5960 /* spr. */
5961 void
5962 OP_142_14 (SIM_DESC sd, SIM_CPU *cpu)
5963 {
5964 uint16 a = CREG (OP[0]);
5965 trace_input ("spr", OP_REG, OP_REG, OP_VOID);
5966 SET_GPR (OP[1], a);
5967 trace_output_16 (sd, a);
5968 }
5969
5970 /* sprd. */
5971 void
5972 OP_143_14 (SIM_DESC sd, SIM_CPU *cpu)
5973 {
5974 uint32 a = CREG (OP[0]);
5975 trace_input ("sprd", OP_REGP, OP_REGP, OP_VOID);
5976 SET_GPR32 (OP[1], a);
5977 trace_output_32 (sd, a);
5978 }
5979
5980 /* null. */
5981 void
5982 OP_0_20 (SIM_DESC sd, SIM_CPU *cpu)
5983 {
5984 trace_input ("null", OP_VOID, OP_VOID, OP_VOID);
5985 sim_engine_halt (sd, cpu, NULL, PC, sim_exited, 0);
5986 }