sim/cris/semcrisv32f-switch.c

   1 /* Simulator instruction semantics for crisv32f.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996-2007 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU simulators.
   8
   9    This file is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    It is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License along
  20    with this program; if not, write to the Free Software Foundation, Inc.,
  21    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #ifdef DEFINE_LABELS
  26
  27   /* The labels have the case they have because the enum of insn types
  28      is all uppercase and in the non-stdc case the insn symbol is built
  29      into the enum name.  */
  30
  31   static struct {
  32     int index;
  33     void *label;
  34   } labels[] = {
  35     { CRISV32F_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
  36     { CRISV32F_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
  37     { CRISV32F_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
  38     { CRISV32F_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
  39     { CRISV32F_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
  40     { CRISV32F_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
  41     { CRISV32F_INSN_MOVE_B_R, && case_sem_INSN_MOVE_B_R },
  42     { CRISV32F_INSN_MOVE_W_R, && case_sem_INSN_MOVE_W_R },
  43     { CRISV32F_INSN_MOVE_D_R, && case_sem_INSN_MOVE_D_R },
  44     { CRISV32F_INSN_MOVEQ, && case_sem_INSN_MOVEQ },
  45     { CRISV32F_INSN_MOVS_B_R, && case_sem_INSN_MOVS_B_R },
  46     { CRISV32F_INSN_MOVS_W_R, && case_sem_INSN_MOVS_W_R },
  47     { CRISV32F_INSN_MOVU_B_R, && case_sem_INSN_MOVU_B_R },
  48     { CRISV32F_INSN_MOVU_W_R, && case_sem_INSN_MOVU_W_R },
  49     { CRISV32F_INSN_MOVECBR, && case_sem_INSN_MOVECBR },
  50     { CRISV32F_INSN_MOVECWR, && case_sem_INSN_MOVECWR },
  51     { CRISV32F_INSN_MOVECDR, && case_sem_INSN_MOVECDR },
  52     { CRISV32F_INSN_MOVSCBR, && case_sem_INSN_MOVSCBR },
  53     { CRISV32F_INSN_MOVSCWR, && case_sem_INSN_MOVSCWR },
  54     { CRISV32F_INSN_MOVUCBR, && case_sem_INSN_MOVUCBR },
  55     { CRISV32F_INSN_MOVUCWR, && case_sem_INSN_MOVUCWR },
  56     { CRISV32F_INSN_ADDQ, && case_sem_INSN_ADDQ },
  57     { CRISV32F_INSN_SUBQ, && case_sem_INSN_SUBQ },
  58     { CRISV32F_INSN_CMP_R_B_R, && case_sem_INSN_CMP_R_B_R },
  59     { CRISV32F_INSN_CMP_R_W_R, && case_sem_INSN_CMP_R_W_R },
  60     { CRISV32F_INSN_CMP_R_D_R, && case_sem_INSN_CMP_R_D_R },
  61     { CRISV32F_INSN_CMP_M_B_M, && case_sem_INSN_CMP_M_B_M },
  62     { CRISV32F_INSN_CMP_M_W_M, && case_sem_INSN_CMP_M_W_M },
  63     { CRISV32F_INSN_CMP_M_D_M, && case_sem_INSN_CMP_M_D_M },
  64     { CRISV32F_INSN_CMPCBR, && case_sem_INSN_CMPCBR },
  65     { CRISV32F_INSN_CMPCWR, && case_sem_INSN_CMPCWR },
  66     { CRISV32F_INSN_CMPCDR, && case_sem_INSN_CMPCDR },
  67     { CRISV32F_INSN_CMPQ, && case_sem_INSN_CMPQ },
  68     { CRISV32F_INSN_CMPS_M_B_M, && case_sem_INSN_CMPS_M_B_M },
  69     { CRISV32F_INSN_CMPS_M_W_M, && case_sem_INSN_CMPS_M_W_M },
  70     { CRISV32F_INSN_CMPSCBR, && case_sem_INSN_CMPSCBR },
  71     { CRISV32F_INSN_CMPSCWR, && case_sem_INSN_CMPSCWR },
  72     { CRISV32F_INSN_CMPU_M_B_M, && case_sem_INSN_CMPU_M_B_M },
  73     { CRISV32F_INSN_CMPU_M_W_M, && case_sem_INSN_CMPU_M_W_M },
  74     { CRISV32F_INSN_CMPUCBR, && case_sem_INSN_CMPUCBR },
  75     { CRISV32F_INSN_CMPUCWR, && case_sem_INSN_CMPUCWR },
  76     { CRISV32F_INSN_MOVE_M_B_M, && case_sem_INSN_MOVE_M_B_M },
  77     { CRISV32F_INSN_MOVE_M_W_M, && case_sem_INSN_MOVE_M_W_M },
  78     { CRISV32F_INSN_MOVE_M_D_M, && case_sem_INSN_MOVE_M_D_M },
  79     { CRISV32F_INSN_MOVS_M_B_M, && case_sem_INSN_MOVS_M_B_M },
  80     { CRISV32F_INSN_MOVS_M_W_M, && case_sem_INSN_MOVS_M_W_M },
  81     { CRISV32F_INSN_MOVU_M_B_M, && case_sem_INSN_MOVU_M_B_M },
  82     { CRISV32F_INSN_MOVU_M_W_M, && case_sem_INSN_MOVU_M_W_M },
  83     { CRISV32F_INSN_MOVE_R_SPRV32, && case_sem_INSN_MOVE_R_SPRV32 },
  84     { CRISV32F_INSN_MOVE_SPR_RV32, && case_sem_INSN_MOVE_SPR_RV32 },
  85     { CRISV32F_INSN_MOVE_M_SPRV32, && case_sem_INSN_MOVE_M_SPRV32 },
  86     { CRISV32F_INSN_MOVE_C_SPRV32_P2, && case_sem_INSN_MOVE_C_SPRV32_P2 },
  87     { CRISV32F_INSN_MOVE_C_SPRV32_P3, && case_sem_INSN_MOVE_C_SPRV32_P3 },
  88     { CRISV32F_INSN_MOVE_C_SPRV32_P5, && case_sem_INSN_MOVE_C_SPRV32_P5 },
  89     { CRISV32F_INSN_MOVE_C_SPRV32_P6, && case_sem_INSN_MOVE_C_SPRV32_P6 },
  90     { CRISV32F_INSN_MOVE_C_SPRV32_P7, && case_sem_INSN_MOVE_C_SPRV32_P7 },
  91     { CRISV32F_INSN_MOVE_C_SPRV32_P9, && case_sem_INSN_MOVE_C_SPRV32_P9 },
  92     { CRISV32F_INSN_MOVE_C_SPRV32_P10, && case_sem_INSN_MOVE_C_SPRV32_P10 },
  93     { CRISV32F_INSN_MOVE_C_SPRV32_P11, && case_sem_INSN_MOVE_C_SPRV32_P11 },
  94     { CRISV32F_INSN_MOVE_C_SPRV32_P12, && case_sem_INSN_MOVE_C_SPRV32_P12 },
  95     { CRISV32F_INSN_MOVE_C_SPRV32_P13, && case_sem_INSN_MOVE_C_SPRV32_P13 },
  96     { CRISV32F_INSN_MOVE_C_SPRV32_P14, && case_sem_INSN_MOVE_C_SPRV32_P14 },
  97     { CRISV32F_INSN_MOVE_C_SPRV32_P15, && case_sem_INSN_MOVE_C_SPRV32_P15 },
  98     { CRISV32F_INSN_MOVE_SPR_MV32, && case_sem_INSN_MOVE_SPR_MV32 },
  99     { CRISV32F_INSN_MOVE_SS_R, && case_sem_INSN_MOVE_SS_R },
 100     { CRISV32F_INSN_MOVE_R_SS, && case_sem_INSN_MOVE_R_SS },
 101     { CRISV32F_INSN_MOVEM_R_M_V32, && case_sem_INSN_MOVEM_R_M_V32 },
 102     { CRISV32F_INSN_MOVEM_M_R_V32, && case_sem_INSN_MOVEM_M_R_V32 },
 103     { CRISV32F_INSN_ADD_B_R, && case_sem_INSN_ADD_B_R },
 104     { CRISV32F_INSN_ADD_W_R, && case_sem_INSN_ADD_W_R },
 105     { CRISV32F_INSN_ADD_D_R, && case_sem_INSN_ADD_D_R },
 106     { CRISV32F_INSN_ADD_M_B_M, && case_sem_INSN_ADD_M_B_M },
 107     { CRISV32F_INSN_ADD_M_W_M, && case_sem_INSN_ADD_M_W_M },
 108     { CRISV32F_INSN_ADD_M_D_M, && case_sem_INSN_ADD_M_D_M },
 109     { CRISV32F_INSN_ADDCBR, && case_sem_INSN_ADDCBR },
 110     { CRISV32F_INSN_ADDCWR, && case_sem_INSN_ADDCWR },
 111     { CRISV32F_INSN_ADDCDR, && case_sem_INSN_ADDCDR },
 112     { CRISV32F_INSN_ADDS_B_R, && case_sem_INSN_ADDS_B_R },
 113     { CRISV32F_INSN_ADDS_W_R, && case_sem_INSN_ADDS_W_R },
 114     { CRISV32F_INSN_ADDS_M_B_M, && case_sem_INSN_ADDS_M_B_M },
 115     { CRISV32F_INSN_ADDS_M_W_M, && case_sem_INSN_ADDS_M_W_M },
 116     { CRISV32F_INSN_ADDSCBR, && case_sem_INSN_ADDSCBR },
 117     { CRISV32F_INSN_ADDSCWR, && case_sem_INSN_ADDSCWR },
 118     { CRISV32F_INSN_ADDU_B_R, && case_sem_INSN_ADDU_B_R },
 119     { CRISV32F_INSN_ADDU_W_R, && case_sem_INSN_ADDU_W_R },
 120     { CRISV32F_INSN_ADDU_M_B_M, && case_sem_INSN_ADDU_M_B_M },
 121     { CRISV32F_INSN_ADDU_M_W_M, && case_sem_INSN_ADDU_M_W_M },
 122     { CRISV32F_INSN_ADDUCBR, && case_sem_INSN_ADDUCBR },
 123     { CRISV32F_INSN_ADDUCWR, && case_sem_INSN_ADDUCWR },
 124     { CRISV32F_INSN_SUB_B_R, && case_sem_INSN_SUB_B_R },
 125     { CRISV32F_INSN_SUB_W_R, && case_sem_INSN_SUB_W_R },
 126     { CRISV32F_INSN_SUB_D_R, && case_sem_INSN_SUB_D_R },
 127     { CRISV32F_INSN_SUB_M_B_M, && case_sem_INSN_SUB_M_B_M },
 128     { CRISV32F_INSN_SUB_M_W_M, && case_sem_INSN_SUB_M_W_M },
 129     { CRISV32F_INSN_SUB_M_D_M, && case_sem_INSN_SUB_M_D_M },
 130     { CRISV32F_INSN_SUBCBR, && case_sem_INSN_SUBCBR },
 131     { CRISV32F_INSN_SUBCWR, && case_sem_INSN_SUBCWR },
 132     { CRISV32F_INSN_SUBCDR, && case_sem_INSN_SUBCDR },
 133     { CRISV32F_INSN_SUBS_B_R, && case_sem_INSN_SUBS_B_R },
 134     { CRISV32F_INSN_SUBS_W_R, && case_sem_INSN_SUBS_W_R },
 135     { CRISV32F_INSN_SUBS_M_B_M, && case_sem_INSN_SUBS_M_B_M },
 136     { CRISV32F_INSN_SUBS_M_W_M, && case_sem_INSN_SUBS_M_W_M },
 137     { CRISV32F_INSN_SUBSCBR, && case_sem_INSN_SUBSCBR },
 138     { CRISV32F_INSN_SUBSCWR, && case_sem_INSN_SUBSCWR },
 139     { CRISV32F_INSN_SUBU_B_R, && case_sem_INSN_SUBU_B_R },
 140     { CRISV32F_INSN_SUBU_W_R, && case_sem_INSN_SUBU_W_R },
 141     { CRISV32F_INSN_SUBU_M_B_M, && case_sem_INSN_SUBU_M_B_M },
 142     { CRISV32F_INSN_SUBU_M_W_M, && case_sem_INSN_SUBU_M_W_M },
 143     { CRISV32F_INSN_SUBUCBR, && case_sem_INSN_SUBUCBR },
 144     { CRISV32F_INSN_SUBUCWR, && case_sem_INSN_SUBUCWR },
 145     { CRISV32F_INSN_ADDC_R, && case_sem_INSN_ADDC_R },
 146     { CRISV32F_INSN_ADDC_M, && case_sem_INSN_ADDC_M },
 147     { CRISV32F_INSN_ADDC_C, && case_sem_INSN_ADDC_C },
 148     { CRISV32F_INSN_LAPC_D, && case_sem_INSN_LAPC_D },
 149     { CRISV32F_INSN_LAPCQ, && case_sem_INSN_LAPCQ },
 150     { CRISV32F_INSN_ADDI_B_R, && case_sem_INSN_ADDI_B_R },
 151     { CRISV32F_INSN_ADDI_W_R, && case_sem_INSN_ADDI_W_R },
 152     { CRISV32F_INSN_ADDI_D_R, && case_sem_INSN_ADDI_D_R },
 153     { CRISV32F_INSN_NEG_B_R, && case_sem_INSN_NEG_B_R },
 154     { CRISV32F_INSN_NEG_W_R, && case_sem_INSN_NEG_W_R },
 155     { CRISV32F_INSN_NEG_D_R, && case_sem_INSN_NEG_D_R },
 156     { CRISV32F_INSN_TEST_M_B_M, && case_sem_INSN_TEST_M_B_M },
 157     { CRISV32F_INSN_TEST_M_W_M, && case_sem_INSN_TEST_M_W_M },
 158     { CRISV32F_INSN_TEST_M_D_M, && case_sem_INSN_TEST_M_D_M },
 159     { CRISV32F_INSN_MOVE_R_M_B_M, && case_sem_INSN_MOVE_R_M_B_M },
 160     { CRISV32F_INSN_MOVE_R_M_W_M, && case_sem_INSN_MOVE_R_M_W_M },
 161     { CRISV32F_INSN_MOVE_R_M_D_M, && case_sem_INSN_MOVE_R_M_D_M },
 162     { CRISV32F_INSN_MULS_B, && case_sem_INSN_MULS_B },
 163     { CRISV32F_INSN_MULS_W, && case_sem_INSN_MULS_W },
 164     { CRISV32F_INSN_MULS_D, && case_sem_INSN_MULS_D },
 165     { CRISV32F_INSN_MULU_B, && case_sem_INSN_MULU_B },
 166     { CRISV32F_INSN_MULU_W, && case_sem_INSN_MULU_W },
 167     { CRISV32F_INSN_MULU_D, && case_sem_INSN_MULU_D },
 168     { CRISV32F_INSN_MCP, && case_sem_INSN_MCP },
 169     { CRISV32F_INSN_DSTEP, && case_sem_INSN_DSTEP },
 170     { CRISV32F_INSN_ABS, && case_sem_INSN_ABS },
 171     { CRISV32F_INSN_AND_B_R, && case_sem_INSN_AND_B_R },
 172     { CRISV32F_INSN_AND_W_R, && case_sem_INSN_AND_W_R },
 173     { CRISV32F_INSN_AND_D_R, && case_sem_INSN_AND_D_R },
 174     { CRISV32F_INSN_AND_M_B_M, && case_sem_INSN_AND_M_B_M },
 175     { CRISV32F_INSN_AND_M_W_M, && case_sem_INSN_AND_M_W_M },
 176     { CRISV32F_INSN_AND_M_D_M, && case_sem_INSN_AND_M_D_M },
 177     { CRISV32F_INSN_ANDCBR, && case_sem_INSN_ANDCBR },
 178     { CRISV32F_INSN_ANDCWR, && case_sem_INSN_ANDCWR },
 179     { CRISV32F_INSN_ANDCDR, && case_sem_INSN_ANDCDR },
 180     { CRISV32F_INSN_ANDQ, && case_sem_INSN_ANDQ },
 181     { CRISV32F_INSN_ORR_B_R, && case_sem_INSN_ORR_B_R },
 182     { CRISV32F_INSN_ORR_W_R, && case_sem_INSN_ORR_W_R },
 183     { CRISV32F_INSN_ORR_D_R, && case_sem_INSN_ORR_D_R },
 184     { CRISV32F_INSN_OR_M_B_M, && case_sem_INSN_OR_M_B_M },
 185     { CRISV32F_INSN_OR_M_W_M, && case_sem_INSN_OR_M_W_M },
 186     { CRISV32F_INSN_OR_M_D_M, && case_sem_INSN_OR_M_D_M },
 187     { CRISV32F_INSN_ORCBR, && case_sem_INSN_ORCBR },
 188     { CRISV32F_INSN_ORCWR, && case_sem_INSN_ORCWR },
 189     { CRISV32F_INSN_ORCDR, && case_sem_INSN_ORCDR },
 190     { CRISV32F_INSN_ORQ, && case_sem_INSN_ORQ },
 191     { CRISV32F_INSN_XOR, && case_sem_INSN_XOR },
 192     { CRISV32F_INSN_SWAP, && case_sem_INSN_SWAP },
 193     { CRISV32F_INSN_ASRR_B_R, && case_sem_INSN_ASRR_B_R },
 194     { CRISV32F_INSN_ASRR_W_R, && case_sem_INSN_ASRR_W_R },
 195     { CRISV32F_INSN_ASRR_D_R, && case_sem_INSN_ASRR_D_R },
 196     { CRISV32F_INSN_ASRQ, && case_sem_INSN_ASRQ },
 197     { CRISV32F_INSN_LSRR_B_R, && case_sem_INSN_LSRR_B_R },
 198     { CRISV32F_INSN_LSRR_W_R, && case_sem_INSN_LSRR_W_R },
 199     { CRISV32F_INSN_LSRR_D_R, && case_sem_INSN_LSRR_D_R },
 200     { CRISV32F_INSN_LSRQ, && case_sem_INSN_LSRQ },
 201     { CRISV32F_INSN_LSLR_B_R, && case_sem_INSN_LSLR_B_R },
 202     { CRISV32F_INSN_LSLR_W_R, && case_sem_INSN_LSLR_W_R },
 203     { CRISV32F_INSN_LSLR_D_R, && case_sem_INSN_LSLR_D_R },
 204     { CRISV32F_INSN_LSLQ, && case_sem_INSN_LSLQ },
 205     { CRISV32F_INSN_BTST, && case_sem_INSN_BTST },
 206     { CRISV32F_INSN_BTSTQ, && case_sem_INSN_BTSTQ },
 207     { CRISV32F_INSN_SETF, && case_sem_INSN_SETF },
 208     { CRISV32F_INSN_CLEARF, && case_sem_INSN_CLEARF },
 209     { CRISV32F_INSN_RFE, && case_sem_INSN_RFE },
 210     { CRISV32F_INSN_SFE, && case_sem_INSN_SFE },
 211     { CRISV32F_INSN_RFG, && case_sem_INSN_RFG },
 212     { CRISV32F_INSN_RFN, && case_sem_INSN_RFN },
 213     { CRISV32F_INSN_HALT, && case_sem_INSN_HALT },
 214     { CRISV32F_INSN_BCC_B, && case_sem_INSN_BCC_B },
 215     { CRISV32F_INSN_BA_B, && case_sem_INSN_BA_B },
 216     { CRISV32F_INSN_BCC_W, && case_sem_INSN_BCC_W },
 217     { CRISV32F_INSN_BA_W, && case_sem_INSN_BA_W },
 218     { CRISV32F_INSN_JAS_R, && case_sem_INSN_JAS_R },
 219     { CRISV32F_INSN_JAS_C, && case_sem_INSN_JAS_C },
 220     { CRISV32F_INSN_JUMP_P, && case_sem_INSN_JUMP_P },
 221     { CRISV32F_INSN_BAS_C, && case_sem_INSN_BAS_C },
 222     { CRISV32F_INSN_JASC_R, && case_sem_INSN_JASC_R },
 223     { CRISV32F_INSN_JASC_C, && case_sem_INSN_JASC_C },
 224     { CRISV32F_INSN_BASC_C, && case_sem_INSN_BASC_C },
 225     { CRISV32F_INSN_BREAK, && case_sem_INSN_BREAK },
 226     { CRISV32F_INSN_BOUND_R_B_R, && case_sem_INSN_BOUND_R_B_R },
 227     { CRISV32F_INSN_BOUND_R_W_R, && case_sem_INSN_BOUND_R_W_R },
 228     { CRISV32F_INSN_BOUND_R_D_R, && case_sem_INSN_BOUND_R_D_R },
 229     { CRISV32F_INSN_BOUND_CB, && case_sem_INSN_BOUND_CB },
 230     { CRISV32F_INSN_BOUND_CW, && case_sem_INSN_BOUND_CW },
 231     { CRISV32F_INSN_BOUND_CD, && case_sem_INSN_BOUND_CD },
 232     { CRISV32F_INSN_SCC, && case_sem_INSN_SCC },
 233     { CRISV32F_INSN_LZ, && case_sem_INSN_LZ },
 234     { CRISV32F_INSN_ADDOQ, && case_sem_INSN_ADDOQ },
 235     { CRISV32F_INSN_ADDO_M_B_M, && case_sem_INSN_ADDO_M_B_M },
 236     { CRISV32F_INSN_ADDO_M_W_M, && case_sem_INSN_ADDO_M_W_M },
 237     { CRISV32F_INSN_ADDO_M_D_M, && case_sem_INSN_ADDO_M_D_M },
 238     { CRISV32F_INSN_ADDO_CB, && case_sem_INSN_ADDO_CB },
 239     { CRISV32F_INSN_ADDO_CW, && case_sem_INSN_ADDO_CW },
 240     { CRISV32F_INSN_ADDO_CD, && case_sem_INSN_ADDO_CD },
 241     { CRISV32F_INSN_ADDI_ACR_B_R, && case_sem_INSN_ADDI_ACR_B_R },
 242     { CRISV32F_INSN_ADDI_ACR_W_R, && case_sem_INSN_ADDI_ACR_W_R },
 243     { CRISV32F_INSN_ADDI_ACR_D_R, && case_sem_INSN_ADDI_ACR_D_R },
 244     { CRISV32F_INSN_FIDXI, && case_sem_INSN_FIDXI },
 245     { CRISV32F_INSN_FTAGI, && case_sem_INSN_FTAGI },
 246     { CRISV32F_INSN_FIDXD, && case_sem_INSN_FIDXD },
 247     { CRISV32F_INSN_FTAGD, && case_sem_INSN_FTAGD },
 248     { 0, 0 }
 249   };
 250   int i;
 251
 252   for (i = 0; labels[i].label != 0; ++i)
 253     {
 254 #if FAST_P
 255       CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
 256 #else
 257       CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
 258 #endif
 259     }
 260
 261 #undef DEFINE_LABELS
 262 #endif /* DEFINE_LABELS */
 263
 264 #ifdef DEFINE_SWITCH
 265
 266 /* If hyper-fast [well not unnecessarily slow] execution is selected, turn
 267    off frills like tracing and profiling.  */
 268 /* FIXME: A better way would be to have TRACE_RESULT check for something
 269    that can cause it to be optimized out.  Another way would be to emit
 270    special handlers into the instruction "stream".  */
 271
 272 #if FAST_P
 273 #undef TRACE_RESULT
 274 #define TRACE_RESULT(cpu, abuf, name, type, val)
 275 #endif
 276
 277 #undef GET_ATTR
 278 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 279 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
 280 #else
 281 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
 282 #endif
 283
 284 {
 285
 286 #if WITH_SCACHE_PBB
 287
 288 /* Branch to next handler without going around main loop.  */
 289 #define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
 290 SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 291
 292 #else /* ! WITH_SCACHE_PBB */
 293
 294 #define NEXT(vpc) BREAK (sem)
 295 #ifdef __GNUC__
 296 #if FAST_P
 297   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
 298 #else
 299   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
 300 #endif
 301 #else
 302   SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
 303 #endif
 304
 305 #endif /* ! WITH_SCACHE_PBB */
 306
 307     {
 308
 309   CASE (sem, INSN_X_INVALID) : /* --invalid-- */
 310 {
 311   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 312   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 313 #define FLD(f) abuf->fields.fmt_empty.f
 314   int UNUSED written = 0;
 315   IADDR UNUSED pc = abuf->addr;
 316   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 317
 318   {
 319     /* Update the recorded pc in the cpu state struct.
 320        Only necessary for WITH_SCACHE case, but to avoid the
 321        conditional compilation ....  */
 322     SET_H_PC (pc);
 323     /* Virtual insns have zero size.  Overwrite vpc with address of next insn
 324        using the default-insn-bitsize spec.  When executing insns in parallel
 325        we may want to queue the fault and continue execution.  */
 326     vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 327     vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
 328   }
 329
 330 #undef FLD
 331 }
 332   NEXT (vpc);
 333
 334   CASE (sem, INSN_X_AFTER) : /* --after-- */
 335 {
 336   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 337   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 338 #define FLD(f) abuf->fields.fmt_empty.f
 339   int UNUSED written = 0;
 340   IADDR UNUSED pc = abuf->addr;
 341   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 342
 343   {
 344 #if WITH_SCACHE_PBB_CRISV32F
 345     crisv32f_pbb_after (current_cpu, sem_arg);
 346 #endif
 347   }
 348
 349 #undef FLD
 350 }
 351   NEXT (vpc);
 352
 353   CASE (sem, INSN_X_BEFORE) : /* --before-- */
 354 {
 355   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 356   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 357 #define FLD(f) abuf->fields.fmt_empty.f
 358   int UNUSED written = 0;
 359   IADDR UNUSED pc = abuf->addr;
 360   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 361
 362   {
 363 #if WITH_SCACHE_PBB_CRISV32F
 364     crisv32f_pbb_before (current_cpu, sem_arg);
 365 #endif
 366   }
 367
 368 #undef FLD
 369 }
 370   NEXT (vpc);
 371
 372   CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
 373 {
 374   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 375   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 376 #define FLD(f) abuf->fields.fmt_empty.f
 377   int UNUSED written = 0;
 378   IADDR UNUSED pc = abuf->addr;
 379   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 380
 381   {
 382 #if WITH_SCACHE_PBB_CRISV32F
 383 #ifdef DEFINE_SWITCH
 384     vpc = crisv32f_pbb_cti_chain (current_cpu, sem_arg,
 385                                pbb_br_type, pbb_br_npc);
 386     BREAK (sem);
 387 #else
 388     /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
 389     vpc = crisv32f_pbb_cti_chain (current_cpu, sem_arg,
 390                                CPU_PBB_BR_TYPE (current_cpu),
 391                                CPU_PBB_BR_NPC (current_cpu));
 392 #endif
 393 #endif
 394   }
 395
 396 #undef FLD
 397 }
 398   NEXT (vpc);
 399
 400   CASE (sem, INSN_X_CHAIN) : /* --chain-- */
 401 {
 402   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 403   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 404 #define FLD(f) abuf->fields.fmt_empty.f
 405   int UNUSED written = 0;
 406   IADDR UNUSED pc = abuf->addr;
 407   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 408
 409   {
 410 #if WITH_SCACHE_PBB_CRISV32F
 411     vpc = crisv32f_pbb_chain (current_cpu, sem_arg);
 412 #ifdef DEFINE_SWITCH
 413     BREAK (sem);
 414 #endif
 415 #endif
 416   }
 417
 418 #undef FLD
 419 }
 420   NEXT (vpc);
 421
 422   CASE (sem, INSN_X_BEGIN) : /* --begin-- */
 423 {
 424   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 425   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 426 #define FLD(f) abuf->fields.fmt_empty.f
 427   int UNUSED written = 0;
 428   IADDR UNUSED pc = abuf->addr;
 429   vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
 430
 431   {
 432 #if WITH_SCACHE_PBB_CRISV32F
 433 #if defined DEFINE_SWITCH || defined FAST_P
 434     /* In the switch case FAST_P is a constant, allowing several optimizations
 435        in any called inline functions.  */
 436     vpc = crisv32f_pbb_begin (current_cpu, FAST_P);
 437 #else
 438 #if 0 /* cgen engine can't handle dynamic fast/full switching yet.  */
 439     vpc = crisv32f_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
 440 #else
 441     vpc = crisv32f_pbb_begin (current_cpu, 0);
 442 #endif
 443 #endif
 444 #endif
 445   }
 446
 447 #undef FLD
 448 }
 449   NEXT (vpc);
 450
 451   CASE (sem, INSN_MOVE_B_R) : /* move.b move.m ${Rs},${Rd} */
 452 {
 453   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 454   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 455 #define FLD(f) abuf->fields.sfmt_addc_m.f
 456   int UNUSED written = 0;
 457   IADDR UNUSED pc = abuf->addr;
 458   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 459
 460 {
 461   QI tmp_newval;
 462   tmp_newval = GET_H_GR (FLD (f_operand1));
 463 {
 464   SI tmp_oldregval;
 465   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
 466   {
 467     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
 468     SET_H_GR (FLD (f_operand2), opval);
 469     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 470   }
 471 }
 472 {
 473   {
 474     BI opval = LTQI (tmp_newval, 0);
 475     CPU (h_nbit) = opval;
 476     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 477   }
 478   {
 479     BI opval = ANDIF (EQQI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 480     CPU (h_zbit) = opval;
 481     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 482   }
 483 SET_H_CBIT_MOVE (0);
 484 SET_H_VBIT_MOVE (0);
 485 {
 486   {
 487     BI opval = 0;
 488     CPU (h_xbit) = opval;
 489     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 490   }
 491   {
 492     BI opval = 0;
 493     SET_H_INSN_PREFIXED_P (opval);
 494     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 495   }
 496 }
 497 }
 498 }
 499
 500 #undef FLD
 501 }
 502   NEXT (vpc);
 503
 504   CASE (sem, INSN_MOVE_W_R) : /* move.w move.m ${Rs},${Rd} */
 505 {
 506   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 507   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 508 #define FLD(f) abuf->fields.sfmt_addc_m.f
 509   int UNUSED written = 0;
 510   IADDR UNUSED pc = abuf->addr;
 511   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 512
 513 {
 514   HI tmp_newval;
 515   tmp_newval = GET_H_GR (FLD (f_operand1));
 516 {
 517   SI tmp_oldregval;
 518   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
 519   {
 520     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
 521     SET_H_GR (FLD (f_operand2), opval);
 522     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 523   }
 524 }
 525 {
 526   {
 527     BI opval = LTHI (tmp_newval, 0);
 528     CPU (h_nbit) = opval;
 529     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 530   }
 531   {
 532     BI opval = ANDIF (EQHI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 533     CPU (h_zbit) = opval;
 534     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 535   }
 536 SET_H_CBIT_MOVE (0);
 537 SET_H_VBIT_MOVE (0);
 538 {
 539   {
 540     BI opval = 0;
 541     CPU (h_xbit) = opval;
 542     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 543   }
 544   {
 545     BI opval = 0;
 546     SET_H_INSN_PREFIXED_P (opval);
 547     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 548   }
 549 }
 550 }
 551 }
 552
 553 #undef FLD
 554 }
 555   NEXT (vpc);
 556
 557   CASE (sem, INSN_MOVE_D_R) : /* move.d move.m ${Rs},${Rd} */
 558 {
 559   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 560   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 561 #define FLD(f) abuf->fields.sfmt_addc_m.f
 562   int UNUSED written = 0;
 563   IADDR UNUSED pc = abuf->addr;
 564   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 565
 566 {
 567   SI tmp_newval;
 568   tmp_newval = GET_H_GR (FLD (f_operand1));
 569   {
 570     SI opval = tmp_newval;
 571     SET_H_GR (FLD (f_operand2), opval);
 572     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 573   }
 574 {
 575   {
 576     BI opval = LTSI (tmp_newval, 0);
 577     CPU (h_nbit) = opval;
 578     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 579   }
 580   {
 581     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 582     CPU (h_zbit) = opval;
 583     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 584   }
 585 SET_H_CBIT_MOVE (0);
 586 SET_H_VBIT_MOVE (0);
 587 {
 588   {
 589     BI opval = 0;
 590     CPU (h_xbit) = opval;
 591     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 592   }
 593   {
 594     BI opval = 0;
 595     SET_H_INSN_PREFIXED_P (opval);
 596     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 597   }
 598 }
 599 }
 600 }
 601
 602 #undef FLD
 603 }
 604   NEXT (vpc);
 605
 606   CASE (sem, INSN_MOVEQ) : /* moveq $i,$Rd */
 607 {
 608   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 609   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 610 #define FLD(f) abuf->fields.sfmt_moveq.f
 611   int UNUSED written = 0;
 612   IADDR UNUSED pc = abuf->addr;
 613   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 614
 615 {
 616   SI tmp_newval;
 617   tmp_newval = FLD (f_s6);
 618   {
 619     SI opval = tmp_newval;
 620     SET_H_GR (FLD (f_operand2), opval);
 621     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 622   }
 623 {
 624 SET_H_NBIT_MOVE (LTSI (tmp_newval, 0));
 625 SET_H_ZBIT_MOVE (ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))));
 626 SET_H_CBIT_MOVE (0);
 627 SET_H_VBIT_MOVE (0);
 628 {
 629   {
 630     BI opval = 0;
 631     CPU (h_xbit) = opval;
 632     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 633   }
 634   {
 635     BI opval = 0;
 636     SET_H_INSN_PREFIXED_P (opval);
 637     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 638   }
 639 }
 640 }
 641 }
 642
 643 #undef FLD
 644 }
 645   NEXT (vpc);
 646
 647   CASE (sem, INSN_MOVS_B_R) : /* movs.b movs.m ${Rs},${Rd} */
 648 {
 649   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 650   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 651 #define FLD(f) abuf->fields.sfmt_muls_b.f
 652   int UNUSED written = 0;
 653   IADDR UNUSED pc = abuf->addr;
 654   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 655
 656 {
 657   QI tmp_tmpops;
 658   SI tmp_newval;
 659   tmp_tmpops = GET_H_GR (FLD (f_operand1));
 660   tmp_newval = EXTQISI (tmp_tmpops);
 661   {
 662     SI opval = tmp_newval;
 663     SET_H_GR (FLD (f_operand2), opval);
 664     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 665   }
 666 {
 667   {
 668     BI opval = LTSI (tmp_newval, 0);
 669     CPU (h_nbit) = opval;
 670     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 671   }
 672   {
 673     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 674     CPU (h_zbit) = opval;
 675     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 676   }
 677 SET_H_CBIT_MOVE (0);
 678 SET_H_VBIT_MOVE (0);
 679 {
 680   {
 681     BI opval = 0;
 682     CPU (h_xbit) = opval;
 683     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 684   }
 685   {
 686     BI opval = 0;
 687     SET_H_INSN_PREFIXED_P (opval);
 688     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 689   }
 690 }
 691 }
 692 }
 693
 694 #undef FLD
 695 }
 696   NEXT (vpc);
 697
 698   CASE (sem, INSN_MOVS_W_R) : /* movs.w movs.m ${Rs},${Rd} */
 699 {
 700   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 701   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 702 #define FLD(f) abuf->fields.sfmt_muls_b.f
 703   int UNUSED written = 0;
 704   IADDR UNUSED pc = abuf->addr;
 705   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 706
 707 {
 708   HI tmp_tmpops;
 709   SI tmp_newval;
 710   tmp_tmpops = GET_H_GR (FLD (f_operand1));
 711   tmp_newval = EXTHISI (tmp_tmpops);
 712   {
 713     SI opval = tmp_newval;
 714     SET_H_GR (FLD (f_operand2), opval);
 715     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 716   }
 717 {
 718   {
 719     BI opval = LTSI (tmp_newval, 0);
 720     CPU (h_nbit) = opval;
 721     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 722   }
 723   {
 724     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 725     CPU (h_zbit) = opval;
 726     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 727   }
 728 SET_H_CBIT_MOVE (0);
 729 SET_H_VBIT_MOVE (0);
 730 {
 731   {
 732     BI opval = 0;
 733     CPU (h_xbit) = opval;
 734     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 735   }
 736   {
 737     BI opval = 0;
 738     SET_H_INSN_PREFIXED_P (opval);
 739     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 740   }
 741 }
 742 }
 743 }
 744
 745 #undef FLD
 746 }
 747   NEXT (vpc);
 748
 749   CASE (sem, INSN_MOVU_B_R) : /* movu.b movu.m ${Rs},${Rd} */
 750 {
 751   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 752   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 753 #define FLD(f) abuf->fields.sfmt_muls_b.f
 754   int UNUSED written = 0;
 755   IADDR UNUSED pc = abuf->addr;
 756   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 757
 758 {
 759   QI tmp_tmpops;
 760   SI tmp_newval;
 761   tmp_tmpops = GET_H_GR (FLD (f_operand1));
 762   tmp_newval = ZEXTQISI (tmp_tmpops);
 763   {
 764     SI opval = tmp_newval;
 765     SET_H_GR (FLD (f_operand2), opval);
 766     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 767   }
 768 {
 769   {
 770     BI opval = LTSI (tmp_newval, 0);
 771     CPU (h_nbit) = opval;
 772     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 773   }
 774   {
 775     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 776     CPU (h_zbit) = opval;
 777     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 778   }
 779 SET_H_CBIT_MOVE (0);
 780 SET_H_VBIT_MOVE (0);
 781 {
 782   {
 783     BI opval = 0;
 784     CPU (h_xbit) = opval;
 785     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 786   }
 787   {
 788     BI opval = 0;
 789     SET_H_INSN_PREFIXED_P (opval);
 790     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 791   }
 792 }
 793 }
 794 }
 795
 796 #undef FLD
 797 }
 798   NEXT (vpc);
 799
 800   CASE (sem, INSN_MOVU_W_R) : /* movu.w movu.m ${Rs},${Rd} */
 801 {
 802   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 803   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 804 #define FLD(f) abuf->fields.sfmt_muls_b.f
 805   int UNUSED written = 0;
 806   IADDR UNUSED pc = abuf->addr;
 807   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
 808
 809 {
 810   HI tmp_tmpops;
 811   SI tmp_newval;
 812   tmp_tmpops = GET_H_GR (FLD (f_operand1));
 813   tmp_newval = ZEXTHISI (tmp_tmpops);
 814   {
 815     SI opval = tmp_newval;
 816     SET_H_GR (FLD (f_operand2), opval);
 817     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 818   }
 819 {
 820   {
 821     BI opval = LTSI (tmp_newval, 0);
 822     CPU (h_nbit) = opval;
 823     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 824   }
 825   {
 826     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 827     CPU (h_zbit) = opval;
 828     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 829   }
 830 SET_H_CBIT_MOVE (0);
 831 SET_H_VBIT_MOVE (0);
 832 {
 833   {
 834     BI opval = 0;
 835     CPU (h_xbit) = opval;
 836     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 837   }
 838   {
 839     BI opval = 0;
 840     SET_H_INSN_PREFIXED_P (opval);
 841     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 842   }
 843 }
 844 }
 845 }
 846
 847 #undef FLD
 848 }
 849   NEXT (vpc);
 850
 851   CASE (sem, INSN_MOVECBR) : /* move.b ${sconst8},${Rd} */
 852 {
 853   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 854   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 855 #define FLD(f) abuf->fields.sfmt_addcbr.f
 856   int UNUSED written = 0;
 857   IADDR UNUSED pc = abuf->addr;
 858   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 859
 860 {
 861   QI tmp_newval;
 862   tmp_newval = FLD (f_indir_pc__byte);
 863 {
 864   SI tmp_oldregval;
 865   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
 866   {
 867     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
 868     SET_H_GR (FLD (f_operand2), opval);
 869     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 870   }
 871 }
 872 {
 873   {
 874     BI opval = LTQI (tmp_newval, 0);
 875     CPU (h_nbit) = opval;
 876     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 877   }
 878   {
 879     BI opval = ANDIF (EQQI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 880     CPU (h_zbit) = opval;
 881     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 882   }
 883 SET_H_CBIT_MOVE (0);
 884 SET_H_VBIT_MOVE (0);
 885 {
 886   {
 887     BI opval = 0;
 888     CPU (h_xbit) = opval;
 889     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 890   }
 891   {
 892     BI opval = 0;
 893     SET_H_INSN_PREFIXED_P (opval);
 894     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 895   }
 896 }
 897 }
 898 }
 899
 900 #undef FLD
 901 }
 902   NEXT (vpc);
 903
 904   CASE (sem, INSN_MOVECWR) : /* move.w ${sconst16},${Rd} */
 905 {
 906   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 907   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 908 #define FLD(f) abuf->fields.sfmt_addcwr.f
 909   int UNUSED written = 0;
 910   IADDR UNUSED pc = abuf->addr;
 911   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
 912
 913 {
 914   HI tmp_newval;
 915   tmp_newval = FLD (f_indir_pc__word);
 916 {
 917   SI tmp_oldregval;
 918   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
 919   {
 920     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
 921     SET_H_GR (FLD (f_operand2), opval);
 922     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 923   }
 924 }
 925 {
 926   {
 927     BI opval = LTHI (tmp_newval, 0);
 928     CPU (h_nbit) = opval;
 929     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 930   }
 931   {
 932     BI opval = ANDIF (EQHI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 933     CPU (h_zbit) = opval;
 934     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 935   }
 936 SET_H_CBIT_MOVE (0);
 937 SET_H_VBIT_MOVE (0);
 938 {
 939   {
 940     BI opval = 0;
 941     CPU (h_xbit) = opval;
 942     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 943   }
 944   {
 945     BI opval = 0;
 946     SET_H_INSN_PREFIXED_P (opval);
 947     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 948   }
 949 }
 950 }
 951 }
 952
 953 #undef FLD
 954 }
 955   NEXT (vpc);
 956
 957   CASE (sem, INSN_MOVECDR) : /* move.d ${const32},${Rd} */
 958 {
 959   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
 960   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 961 #define FLD(f) abuf->fields.sfmt_bound_cd.f
 962   int UNUSED written = 0;
 963   IADDR UNUSED pc = abuf->addr;
 964   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
 965
 966 {
 967   SI tmp_newval;
 968   tmp_newval = FLD (f_indir_pc__dword);
 969   {
 970     SI opval = tmp_newval;
 971     SET_H_GR (FLD (f_operand2), opval);
 972     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
 973   }
 974 {
 975   {
 976     BI opval = LTSI (tmp_newval, 0);
 977     CPU (h_nbit) = opval;
 978     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
 979   }
 980   {
 981     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
 982     CPU (h_zbit) = opval;
 983     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
 984   }
 985 SET_H_CBIT_MOVE (0);
 986 SET_H_VBIT_MOVE (0);
 987 {
 988   {
 989     BI opval = 0;
 990     CPU (h_xbit) = opval;
 991     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
 992   }
 993   {
 994     BI opval = 0;
 995     SET_H_INSN_PREFIXED_P (opval);
 996     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
 997   }
 998 }
 999 }
1000 }
1001
1002 #undef FLD
1003 }
1004   NEXT (vpc);
1005
1006   CASE (sem, INSN_MOVSCBR) : /* movs.b ${sconst8},${Rd} */
1007 {
1008   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1009   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1010 #define FLD(f) abuf->fields.sfmt_bound_cb.f
1011   int UNUSED written = 0;
1012   IADDR UNUSED pc = abuf->addr;
1013   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1014
1015 {
1016   SI tmp_newval;
1017   tmp_newval = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
1018   {
1019     SI opval = tmp_newval;
1020     SET_H_GR (FLD (f_operand2), opval);
1021     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1022   }
1023 {
1024   {
1025     BI opval = LTSI (tmp_newval, 0);
1026     CPU (h_nbit) = opval;
1027     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1028   }
1029   {
1030     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1031     CPU (h_zbit) = opval;
1032     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1033   }
1034 SET_H_CBIT_MOVE (0);
1035 SET_H_VBIT_MOVE (0);
1036 {
1037   {
1038     BI opval = 0;
1039     CPU (h_xbit) = opval;
1040     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1041   }
1042   {
1043     BI opval = 0;
1044     SET_H_INSN_PREFIXED_P (opval);
1045     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1046   }
1047 }
1048 }
1049 }
1050
1051 #undef FLD
1052 }
1053   NEXT (vpc);
1054
1055   CASE (sem, INSN_MOVSCWR) : /* movs.w ${sconst16},${Rd} */
1056 {
1057   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1058   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1059 #define FLD(f) abuf->fields.sfmt_bound_cw.f
1060   int UNUSED written = 0;
1061   IADDR UNUSED pc = abuf->addr;
1062   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1063
1064 {
1065   SI tmp_newval;
1066   tmp_newval = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
1067   {
1068     SI opval = tmp_newval;
1069     SET_H_GR (FLD (f_operand2), opval);
1070     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1071   }
1072 {
1073   {
1074     BI opval = LTSI (tmp_newval, 0);
1075     CPU (h_nbit) = opval;
1076     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1077   }
1078   {
1079     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1080     CPU (h_zbit) = opval;
1081     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1082   }
1083 SET_H_CBIT_MOVE (0);
1084 SET_H_VBIT_MOVE (0);
1085 {
1086   {
1087     BI opval = 0;
1088     CPU (h_xbit) = opval;
1089     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1090   }
1091   {
1092     BI opval = 0;
1093     SET_H_INSN_PREFIXED_P (opval);
1094     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1095   }
1096 }
1097 }
1098 }
1099
1100 #undef FLD
1101 }
1102   NEXT (vpc);
1103
1104   CASE (sem, INSN_MOVUCBR) : /* movu.b ${uconst8},${Rd} */
1105 {
1106   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1107   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1108 #define FLD(f) abuf->fields.sfmt_bound_cb.f
1109   int UNUSED written = 0;
1110   IADDR UNUSED pc = abuf->addr;
1111   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1112
1113 {
1114   SI tmp_newval;
1115   tmp_newval = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
1116   {
1117     SI opval = tmp_newval;
1118     SET_H_GR (FLD (f_operand2), opval);
1119     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1120   }
1121 {
1122   {
1123     BI opval = LTSI (tmp_newval, 0);
1124     CPU (h_nbit) = opval;
1125     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1126   }
1127   {
1128     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1129     CPU (h_zbit) = opval;
1130     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1131   }
1132 SET_H_CBIT_MOVE (0);
1133 SET_H_VBIT_MOVE (0);
1134 {
1135   {
1136     BI opval = 0;
1137     CPU (h_xbit) = opval;
1138     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1139   }
1140   {
1141     BI opval = 0;
1142     SET_H_INSN_PREFIXED_P (opval);
1143     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1144   }
1145 }
1146 }
1147 }
1148
1149 #undef FLD
1150 }
1151   NEXT (vpc);
1152
1153   CASE (sem, INSN_MOVUCWR) : /* movu.w ${uconst16},${Rd} */
1154 {
1155   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1156   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1157 #define FLD(f) abuf->fields.sfmt_bound_cw.f
1158   int UNUSED written = 0;
1159   IADDR UNUSED pc = abuf->addr;
1160   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1161
1162 {
1163   SI tmp_newval;
1164   tmp_newval = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
1165   {
1166     SI opval = tmp_newval;
1167     SET_H_GR (FLD (f_operand2), opval);
1168     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1169   }
1170 {
1171   {
1172     BI opval = LTSI (tmp_newval, 0);
1173     CPU (h_nbit) = opval;
1174     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1175   }
1176   {
1177     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
1178     CPU (h_zbit) = opval;
1179     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1180   }
1181 SET_H_CBIT_MOVE (0);
1182 SET_H_VBIT_MOVE (0);
1183 {
1184   {
1185     BI opval = 0;
1186     CPU (h_xbit) = opval;
1187     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1188   }
1189   {
1190     BI opval = 0;
1191     SET_H_INSN_PREFIXED_P (opval);
1192     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1193   }
1194 }
1195 }
1196 }
1197
1198 #undef FLD
1199 }
1200   NEXT (vpc);
1201
1202   CASE (sem, INSN_ADDQ) : /* addq $j,$Rd */
1203 {
1204   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1205   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1206 #define FLD(f) abuf->fields.sfmt_addq.f
1207   int UNUSED written = 0;
1208   IADDR UNUSED pc = abuf->addr;
1209   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1210
1211 {
1212   SI tmp_tmpopd;
1213   SI tmp_tmpops;
1214   BI tmp_carry;
1215   SI tmp_newval;
1216   tmp_tmpops = FLD (f_u6);
1217   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1218   tmp_carry = CPU (h_cbit);
1219   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1220   {
1221     SI opval = tmp_newval;
1222     SET_H_GR (FLD (f_operand2), opval);
1223     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1224   }
1225 {
1226   {
1227     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
1228     CPU (h_cbit) = opval;
1229     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1230   }
1231   {
1232     BI opval = LTSI (tmp_newval, 0);
1233     CPU (h_nbit) = opval;
1234     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1235   }
1236   {
1237     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1238     CPU (h_zbit) = opval;
1239     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1240   }
1241   {
1242     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1243     CPU (h_vbit) = opval;
1244     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1245   }
1246 {
1247   {
1248     BI opval = 0;
1249     CPU (h_xbit) = opval;
1250     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1251   }
1252   {
1253     BI opval = 0;
1254     SET_H_INSN_PREFIXED_P (opval);
1255     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1256   }
1257 }
1258 }
1259 }
1260
1261 #undef FLD
1262 }
1263   NEXT (vpc);
1264
1265   CASE (sem, INSN_SUBQ) : /* subq $j,$Rd */
1266 {
1267   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1268   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1269 #define FLD(f) abuf->fields.sfmt_addq.f
1270   int UNUSED written = 0;
1271   IADDR UNUSED pc = abuf->addr;
1272   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1273
1274 {
1275   SI tmp_tmpopd;
1276   SI tmp_tmpops;
1277   BI tmp_carry;
1278   SI tmp_newval;
1279   tmp_tmpops = FLD (f_u6);
1280   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1281   tmp_carry = CPU (h_cbit);
1282   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1283   {
1284     SI opval = tmp_newval;
1285     SET_H_GR (FLD (f_operand2), opval);
1286     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1287   }
1288 {
1289   {
1290     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1291     CPU (h_cbit) = opval;
1292     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1293   }
1294   {
1295     BI opval = LTSI (tmp_newval, 0);
1296     CPU (h_nbit) = opval;
1297     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1298   }
1299   {
1300     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1301     CPU (h_zbit) = opval;
1302     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1303   }
1304   {
1305     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1306     CPU (h_vbit) = opval;
1307     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1308   }
1309 {
1310   {
1311     BI opval = 0;
1312     CPU (h_xbit) = opval;
1313     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1314   }
1315   {
1316     BI opval = 0;
1317     SET_H_INSN_PREFIXED_P (opval);
1318     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1319   }
1320 }
1321 }
1322 }
1323
1324 #undef FLD
1325 }
1326   NEXT (vpc);
1327
1328   CASE (sem, INSN_CMP_R_B_R) : /* cmp-r.b $Rs,$Rd */
1329 {
1330   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1331   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1332 #define FLD(f) abuf->fields.sfmt_muls_b.f
1333   int UNUSED written = 0;
1334   IADDR UNUSED pc = abuf->addr;
1335   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1336
1337 {
1338   QI tmp_tmpopd;
1339   QI tmp_tmpops;
1340   BI tmp_carry;
1341   QI tmp_newval;
1342   tmp_tmpops = GET_H_GR (FLD (f_operand1));
1343   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1344   tmp_carry = CPU (h_cbit);
1345   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1346 ((void) 0); /*nop*/
1347 {
1348   {
1349     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
1350     CPU (h_cbit) = opval;
1351     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1352   }
1353   {
1354     BI opval = LTQI (tmp_newval, 0);
1355     CPU (h_nbit) = opval;
1356     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1357   }
1358   {
1359     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1360     CPU (h_zbit) = opval;
1361     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1362   }
1363   {
1364     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
1365     CPU (h_vbit) = opval;
1366     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1367   }
1368 {
1369   {
1370     BI opval = 0;
1371     CPU (h_xbit) = opval;
1372     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1373   }
1374   {
1375     BI opval = 0;
1376     SET_H_INSN_PREFIXED_P (opval);
1377     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1378   }
1379 }
1380 }
1381 }
1382
1383 #undef FLD
1384 }
1385   NEXT (vpc);
1386
1387   CASE (sem, INSN_CMP_R_W_R) : /* cmp-r.w $Rs,$Rd */
1388 {
1389   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1390   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1391 #define FLD(f) abuf->fields.sfmt_muls_b.f
1392   int UNUSED written = 0;
1393   IADDR UNUSED pc = abuf->addr;
1394   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1395
1396 {
1397   HI tmp_tmpopd;
1398   HI tmp_tmpops;
1399   BI tmp_carry;
1400   HI tmp_newval;
1401   tmp_tmpops = GET_H_GR (FLD (f_operand1));
1402   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1403   tmp_carry = CPU (h_cbit);
1404   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1405 ((void) 0); /*nop*/
1406 {
1407   {
1408     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
1409     CPU (h_cbit) = opval;
1410     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1411   }
1412   {
1413     BI opval = LTHI (tmp_newval, 0);
1414     CPU (h_nbit) = opval;
1415     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1416   }
1417   {
1418     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1419     CPU (h_zbit) = opval;
1420     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1421   }
1422   {
1423     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
1424     CPU (h_vbit) = opval;
1425     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1426   }
1427 {
1428   {
1429     BI opval = 0;
1430     CPU (h_xbit) = opval;
1431     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1432   }
1433   {
1434     BI opval = 0;
1435     SET_H_INSN_PREFIXED_P (opval);
1436     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1437   }
1438 }
1439 }
1440 }
1441
1442 #undef FLD
1443 }
1444   NEXT (vpc);
1445
1446   CASE (sem, INSN_CMP_R_D_R) : /* cmp-r.d $Rs,$Rd */
1447 {
1448   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1449   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1450 #define FLD(f) abuf->fields.sfmt_muls_b.f
1451   int UNUSED written = 0;
1452   IADDR UNUSED pc = abuf->addr;
1453   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1454
1455 {
1456   SI tmp_tmpopd;
1457   SI tmp_tmpops;
1458   BI tmp_carry;
1459   SI tmp_newval;
1460   tmp_tmpops = GET_H_GR (FLD (f_operand1));
1461   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1462   tmp_carry = CPU (h_cbit);
1463   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1464 ((void) 0); /*nop*/
1465 {
1466   {
1467     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1468     CPU (h_cbit) = opval;
1469     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1470   }
1471   {
1472     BI opval = LTSI (tmp_newval, 0);
1473     CPU (h_nbit) = opval;
1474     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1475   }
1476   {
1477     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1478     CPU (h_zbit) = opval;
1479     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1480   }
1481   {
1482     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1483     CPU (h_vbit) = opval;
1484     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1485   }
1486 {
1487   {
1488     BI opval = 0;
1489     CPU (h_xbit) = opval;
1490     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1491   }
1492   {
1493     BI opval = 0;
1494     SET_H_INSN_PREFIXED_P (opval);
1495     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1496   }
1497 }
1498 }
1499 }
1500
1501 #undef FLD
1502 }
1503   NEXT (vpc);
1504
1505   CASE (sem, INSN_CMP_M_B_M) : /* cmp-m.b [${Rs}${inc}],${Rd} */
1506 {
1507   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1508   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1509 #define FLD(f) abuf->fields.sfmt_addc_m.f
1510   int UNUSED written = 0;
1511   IADDR UNUSED pc = abuf->addr;
1512   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1513
1514 {
1515   QI tmp_tmpopd;
1516   QI tmp_tmpops;
1517   BI tmp_carry;
1518   QI tmp_newval;
1519   tmp_tmpops = ({   SI tmp_addr;
1520   QI tmp_tmp_mem;
1521   BI tmp_postinc;
1522   tmp_postinc = FLD (f_memmode);
1523 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
1524 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
1525 ; if (NEBI (tmp_postinc, 0)) {
1526 {
1527 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
1528   tmp_addr = ADDSI (tmp_addr, 1);
1529 }
1530   {
1531     SI opval = tmp_addr;
1532     SET_H_GR (FLD (f_operand1), opval);
1533     written |= (1 << 9);
1534     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1535   }
1536 }
1537 }
1538 ; tmp_tmp_mem; });
1539   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1540   tmp_carry = CPU (h_cbit);
1541   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1542 ((void) 0); /*nop*/
1543 {
1544   {
1545     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
1546     CPU (h_cbit) = opval;
1547     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1548   }
1549   {
1550     BI opval = LTQI (tmp_newval, 0);
1551     CPU (h_nbit) = opval;
1552     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1553   }
1554   {
1555     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1556     CPU (h_zbit) = opval;
1557     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1558   }
1559   {
1560     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
1561     CPU (h_vbit) = opval;
1562     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1563   }
1564 {
1565   {
1566     BI opval = 0;
1567     CPU (h_xbit) = opval;
1568     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1569   }
1570   {
1571     BI opval = 0;
1572     SET_H_INSN_PREFIXED_P (opval);
1573     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1574   }
1575 }
1576 }
1577 }
1578
1579   abuf->written = written;
1580 #undef FLD
1581 }
1582   NEXT (vpc);
1583
1584   CASE (sem, INSN_CMP_M_W_M) : /* cmp-m.w [${Rs}${inc}],${Rd} */
1585 {
1586   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1587   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1588 #define FLD(f) abuf->fields.sfmt_addc_m.f
1589   int UNUSED written = 0;
1590   IADDR UNUSED pc = abuf->addr;
1591   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1592
1593 {
1594   HI tmp_tmpopd;
1595   HI tmp_tmpops;
1596   BI tmp_carry;
1597   HI tmp_newval;
1598   tmp_tmpops = ({   SI tmp_addr;
1599   HI tmp_tmp_mem;
1600   BI tmp_postinc;
1601   tmp_postinc = FLD (f_memmode);
1602 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
1603 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
1604 ; if (NEBI (tmp_postinc, 0)) {
1605 {
1606 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
1607   tmp_addr = ADDSI (tmp_addr, 2);
1608 }
1609   {
1610     SI opval = tmp_addr;
1611     SET_H_GR (FLD (f_operand1), opval);
1612     written |= (1 << 9);
1613     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1614   }
1615 }
1616 }
1617 ; tmp_tmp_mem; });
1618   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1619   tmp_carry = CPU (h_cbit);
1620   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1621 ((void) 0); /*nop*/
1622 {
1623   {
1624     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
1625     CPU (h_cbit) = opval;
1626     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1627   }
1628   {
1629     BI opval = LTHI (tmp_newval, 0);
1630     CPU (h_nbit) = opval;
1631     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1632   }
1633   {
1634     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1635     CPU (h_zbit) = opval;
1636     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1637   }
1638   {
1639     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
1640     CPU (h_vbit) = opval;
1641     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1642   }
1643 {
1644   {
1645     BI opval = 0;
1646     CPU (h_xbit) = opval;
1647     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1648   }
1649   {
1650     BI opval = 0;
1651     SET_H_INSN_PREFIXED_P (opval);
1652     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1653   }
1654 }
1655 }
1656 }
1657
1658   abuf->written = written;
1659 #undef FLD
1660 }
1661   NEXT (vpc);
1662
1663   CASE (sem, INSN_CMP_M_D_M) : /* cmp-m.d [${Rs}${inc}],${Rd} */
1664 {
1665   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1666   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1667 #define FLD(f) abuf->fields.sfmt_addc_m.f
1668   int UNUSED written = 0;
1669   IADDR UNUSED pc = abuf->addr;
1670   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1671
1672 {
1673   SI tmp_tmpopd;
1674   SI tmp_tmpops;
1675   BI tmp_carry;
1676   SI tmp_newval;
1677   tmp_tmpops = ({   SI tmp_addr;
1678   SI tmp_tmp_mem;
1679   BI tmp_postinc;
1680   tmp_postinc = FLD (f_memmode);
1681 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
1682 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
1683 ; if (NEBI (tmp_postinc, 0)) {
1684 {
1685 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
1686   tmp_addr = ADDSI (tmp_addr, 4);
1687 }
1688   {
1689     SI opval = tmp_addr;
1690     SET_H_GR (FLD (f_operand1), opval);
1691     written |= (1 << 9);
1692     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1693   }
1694 }
1695 }
1696 ; tmp_tmp_mem; });
1697   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1698   tmp_carry = CPU (h_cbit);
1699   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1700 ((void) 0); /*nop*/
1701 {
1702   {
1703     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1704     CPU (h_cbit) = opval;
1705     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1706   }
1707   {
1708     BI opval = LTSI (tmp_newval, 0);
1709     CPU (h_nbit) = opval;
1710     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1711   }
1712   {
1713     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1714     CPU (h_zbit) = opval;
1715     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1716   }
1717   {
1718     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1719     CPU (h_vbit) = opval;
1720     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1721   }
1722 {
1723   {
1724     BI opval = 0;
1725     CPU (h_xbit) = opval;
1726     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1727   }
1728   {
1729     BI opval = 0;
1730     SET_H_INSN_PREFIXED_P (opval);
1731     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1732   }
1733 }
1734 }
1735 }
1736
1737   abuf->written = written;
1738 #undef FLD
1739 }
1740   NEXT (vpc);
1741
1742   CASE (sem, INSN_CMPCBR) : /* cmp.b $sconst8,$Rd */
1743 {
1744   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1745   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1746 #define FLD(f) abuf->fields.sfmt_bound_cb.f
1747   int UNUSED written = 0;
1748   IADDR UNUSED pc = abuf->addr;
1749   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1750
1751 {
1752   QI tmp_tmpopd;
1753   QI tmp_tmpops;
1754   BI tmp_carry;
1755   QI tmp_newval;
1756   tmp_tmpops = TRUNCSIQI (FLD (f_indir_pc__byte));
1757   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1758   tmp_carry = CPU (h_cbit);
1759   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1760 ((void) 0); /*nop*/
1761 {
1762   {
1763     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
1764     CPU (h_cbit) = opval;
1765     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1766   }
1767   {
1768     BI opval = LTQI (tmp_newval, 0);
1769     CPU (h_nbit) = opval;
1770     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1771   }
1772   {
1773     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1774     CPU (h_zbit) = opval;
1775     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1776   }
1777   {
1778     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
1779     CPU (h_vbit) = opval;
1780     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1781   }
1782 {
1783   {
1784     BI opval = 0;
1785     CPU (h_xbit) = opval;
1786     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1787   }
1788   {
1789     BI opval = 0;
1790     SET_H_INSN_PREFIXED_P (opval);
1791     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1792   }
1793 }
1794 }
1795 }
1796
1797 #undef FLD
1798 }
1799   NEXT (vpc);
1800
1801   CASE (sem, INSN_CMPCWR) : /* cmp.w $sconst16,$Rd */
1802 {
1803   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1804   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1805 #define FLD(f) abuf->fields.sfmt_bound_cw.f
1806   int UNUSED written = 0;
1807   IADDR UNUSED pc = abuf->addr;
1808   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
1809
1810 {
1811   HI tmp_tmpopd;
1812   HI tmp_tmpops;
1813   BI tmp_carry;
1814   HI tmp_newval;
1815   tmp_tmpops = TRUNCSIHI (FLD (f_indir_pc__word));
1816   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1817   tmp_carry = CPU (h_cbit);
1818   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1819 ((void) 0); /*nop*/
1820 {
1821   {
1822     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
1823     CPU (h_cbit) = opval;
1824     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1825   }
1826   {
1827     BI opval = LTHI (tmp_newval, 0);
1828     CPU (h_nbit) = opval;
1829     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1830   }
1831   {
1832     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1833     CPU (h_zbit) = opval;
1834     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1835   }
1836   {
1837     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
1838     CPU (h_vbit) = opval;
1839     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1840   }
1841 {
1842   {
1843     BI opval = 0;
1844     CPU (h_xbit) = opval;
1845     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1846   }
1847   {
1848     BI opval = 0;
1849     SET_H_INSN_PREFIXED_P (opval);
1850     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1851   }
1852 }
1853 }
1854 }
1855
1856 #undef FLD
1857 }
1858   NEXT (vpc);
1859
1860   CASE (sem, INSN_CMPCDR) : /* cmp.d $const32,$Rd */
1861 {
1862   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1863   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1864 #define FLD(f) abuf->fields.sfmt_bound_cd.f
1865   int UNUSED written = 0;
1866   IADDR UNUSED pc = abuf->addr;
1867   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
1868
1869 {
1870   SI tmp_tmpopd;
1871   SI tmp_tmpops;
1872   BI tmp_carry;
1873   SI tmp_newval;
1874   tmp_tmpops = FLD (f_indir_pc__dword);
1875   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1876   tmp_carry = CPU (h_cbit);
1877   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1878 ((void) 0); /*nop*/
1879 {
1880   {
1881     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1882     CPU (h_cbit) = opval;
1883     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1884   }
1885   {
1886     BI opval = LTSI (tmp_newval, 0);
1887     CPU (h_nbit) = opval;
1888     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1889   }
1890   {
1891     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1892     CPU (h_zbit) = opval;
1893     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1894   }
1895   {
1896     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1897     CPU (h_vbit) = opval;
1898     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1899   }
1900 {
1901   {
1902     BI opval = 0;
1903     CPU (h_xbit) = opval;
1904     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1905   }
1906   {
1907     BI opval = 0;
1908     SET_H_INSN_PREFIXED_P (opval);
1909     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1910   }
1911 }
1912 }
1913 }
1914
1915 #undef FLD
1916 }
1917   NEXT (vpc);
1918
1919   CASE (sem, INSN_CMPQ) : /* cmpq $i,$Rd */
1920 {
1921   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1922   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1923 #define FLD(f) abuf->fields.sfmt_andq.f
1924   int UNUSED written = 0;
1925   IADDR UNUSED pc = abuf->addr;
1926   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1927
1928 {
1929   SI tmp_tmpopd;
1930   SI tmp_tmpops;
1931   BI tmp_carry;
1932   SI tmp_newval;
1933   tmp_tmpops = FLD (f_s6);
1934   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
1935   tmp_carry = CPU (h_cbit);
1936   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
1937 ((void) 0); /*nop*/
1938 {
1939   {
1940     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
1941     CPU (h_cbit) = opval;
1942     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1943   }
1944   {
1945     BI opval = LTSI (tmp_newval, 0);
1946     CPU (h_nbit) = opval;
1947     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1948   }
1949   {
1950     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
1951     CPU (h_zbit) = opval;
1952     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1953   }
1954   {
1955     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
1956     CPU (h_vbit) = opval;
1957     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1958   }
1959 {
1960   {
1961     BI opval = 0;
1962     CPU (h_xbit) = opval;
1963     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
1964   }
1965   {
1966     BI opval = 0;
1967     SET_H_INSN_PREFIXED_P (opval);
1968     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
1969   }
1970 }
1971 }
1972 }
1973
1974 #undef FLD
1975 }
1976   NEXT (vpc);
1977
1978   CASE (sem, INSN_CMPS_M_B_M) : /* cmps-m.b [${Rs}${inc}],$Rd */
1979 {
1980   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1981   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1982 #define FLD(f) abuf->fields.sfmt_addc_m.f
1983   int UNUSED written = 0;
1984   IADDR UNUSED pc = abuf->addr;
1985   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1986
1987 {
1988   SI tmp_tmpopd;
1989   SI tmp_tmpops;
1990   BI tmp_carry;
1991   SI tmp_newval;
1992   tmp_tmpops = EXTQISI (({   SI tmp_addr;
1993   QI tmp_tmp_mem;
1994   BI tmp_postinc;
1995   tmp_postinc = FLD (f_memmode);
1996 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
1997 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
1998 ; if (NEBI (tmp_postinc, 0)) {
1999 {
2000 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2001   tmp_addr = ADDSI (tmp_addr, 1);
2002 }
2003   {
2004     SI opval = tmp_addr;
2005     SET_H_GR (FLD (f_operand1), opval);
2006     written |= (1 << 9);
2007     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2008   }
2009 }
2010 }
2011 ; tmp_tmp_mem; }));
2012   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2013   tmp_carry = CPU (h_cbit);
2014   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2015 ((void) 0); /*nop*/
2016 {
2017   {
2018     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2019     CPU (h_cbit) = opval;
2020     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2021   }
2022   {
2023     BI opval = LTSI (tmp_newval, 0);
2024     CPU (h_nbit) = opval;
2025     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2026   }
2027   {
2028     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2029     CPU (h_zbit) = opval;
2030     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2031   }
2032   {
2033     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2034     CPU (h_vbit) = opval;
2035     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2036   }
2037 {
2038   {
2039     BI opval = 0;
2040     CPU (h_xbit) = opval;
2041     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2042   }
2043   {
2044     BI opval = 0;
2045     SET_H_INSN_PREFIXED_P (opval);
2046     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2047   }
2048 }
2049 }
2050 }
2051
2052   abuf->written = written;
2053 #undef FLD
2054 }
2055   NEXT (vpc);
2056
2057   CASE (sem, INSN_CMPS_M_W_M) : /* cmps-m.w [${Rs}${inc}],$Rd */
2058 {
2059   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2060   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2061 #define FLD(f) abuf->fields.sfmt_addc_m.f
2062   int UNUSED written = 0;
2063   IADDR UNUSED pc = abuf->addr;
2064   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2065
2066 {
2067   SI tmp_tmpopd;
2068   SI tmp_tmpops;
2069   BI tmp_carry;
2070   SI tmp_newval;
2071   tmp_tmpops = EXTHISI (({   SI tmp_addr;
2072   HI tmp_tmp_mem;
2073   BI tmp_postinc;
2074   tmp_postinc = FLD (f_memmode);
2075 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2076 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2077 ; if (NEBI (tmp_postinc, 0)) {
2078 {
2079 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2080   tmp_addr = ADDSI (tmp_addr, 2);
2081 }
2082   {
2083     SI opval = tmp_addr;
2084     SET_H_GR (FLD (f_operand1), opval);
2085     written |= (1 << 9);
2086     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2087   }
2088 }
2089 }
2090 ; tmp_tmp_mem; }));
2091   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2092   tmp_carry = CPU (h_cbit);
2093   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2094 ((void) 0); /*nop*/
2095 {
2096   {
2097     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2098     CPU (h_cbit) = opval;
2099     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2100   }
2101   {
2102     BI opval = LTSI (tmp_newval, 0);
2103     CPU (h_nbit) = opval;
2104     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2105   }
2106   {
2107     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2108     CPU (h_zbit) = opval;
2109     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2110   }
2111   {
2112     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2113     CPU (h_vbit) = opval;
2114     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2115   }
2116 {
2117   {
2118     BI opval = 0;
2119     CPU (h_xbit) = opval;
2120     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2121   }
2122   {
2123     BI opval = 0;
2124     SET_H_INSN_PREFIXED_P (opval);
2125     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2126   }
2127 }
2128 }
2129 }
2130
2131   abuf->written = written;
2132 #undef FLD
2133 }
2134   NEXT (vpc);
2135
2136   CASE (sem, INSN_CMPSCBR) : /* [${Rs}${inc}],$Rd */
2137 {
2138   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2139   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2140 #define FLD(f) abuf->fields.sfmt_bound_cb.f
2141   int UNUSED written = 0;
2142   IADDR UNUSED pc = abuf->addr;
2143   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2144
2145 {
2146   SI tmp_tmpopd;
2147   SI tmp_tmpops;
2148   BI tmp_carry;
2149   SI tmp_newval;
2150   tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
2151   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2152   tmp_carry = CPU (h_cbit);
2153   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2154 ((void) 0); /*nop*/
2155 {
2156   {
2157     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2158     CPU (h_cbit) = opval;
2159     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2160   }
2161   {
2162     BI opval = LTSI (tmp_newval, 0);
2163     CPU (h_nbit) = opval;
2164     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2165   }
2166   {
2167     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2168     CPU (h_zbit) = opval;
2169     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2170   }
2171   {
2172     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2173     CPU (h_vbit) = opval;
2174     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2175   }
2176 {
2177   {
2178     BI opval = 0;
2179     CPU (h_xbit) = opval;
2180     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2181   }
2182   {
2183     BI opval = 0;
2184     SET_H_INSN_PREFIXED_P (opval);
2185     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2186   }
2187 }
2188 }
2189 }
2190
2191 #undef FLD
2192 }
2193   NEXT (vpc);
2194
2195   CASE (sem, INSN_CMPSCWR) : /* [${Rs}${inc}],$Rd */
2196 {
2197   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2198   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2199 #define FLD(f) abuf->fields.sfmt_bound_cw.f
2200   int UNUSED written = 0;
2201   IADDR UNUSED pc = abuf->addr;
2202   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2203
2204 {
2205   SI tmp_tmpopd;
2206   SI tmp_tmpops;
2207   BI tmp_carry;
2208   SI tmp_newval;
2209   tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
2210   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2211   tmp_carry = CPU (h_cbit);
2212   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2213 ((void) 0); /*nop*/
2214 {
2215   {
2216     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2217     CPU (h_cbit) = opval;
2218     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2219   }
2220   {
2221     BI opval = LTSI (tmp_newval, 0);
2222     CPU (h_nbit) = opval;
2223     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2224   }
2225   {
2226     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2227     CPU (h_zbit) = opval;
2228     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2229   }
2230   {
2231     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2232     CPU (h_vbit) = opval;
2233     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2234   }
2235 {
2236   {
2237     BI opval = 0;
2238     CPU (h_xbit) = opval;
2239     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2240   }
2241   {
2242     BI opval = 0;
2243     SET_H_INSN_PREFIXED_P (opval);
2244     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2245   }
2246 }
2247 }
2248 }
2249
2250 #undef FLD
2251 }
2252   NEXT (vpc);
2253
2254   CASE (sem, INSN_CMPU_M_B_M) : /* cmpu-m.b [${Rs}${inc}],$Rd */
2255 {
2256   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2257   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2258 #define FLD(f) abuf->fields.sfmt_addc_m.f
2259   int UNUSED written = 0;
2260   IADDR UNUSED pc = abuf->addr;
2261   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2262
2263 {
2264   SI tmp_tmpopd;
2265   SI tmp_tmpops;
2266   BI tmp_carry;
2267   SI tmp_newval;
2268   tmp_tmpops = ZEXTQISI (({   SI tmp_addr;
2269   QI tmp_tmp_mem;
2270   BI tmp_postinc;
2271   tmp_postinc = FLD (f_memmode);
2272 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2273 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2274 ; if (NEBI (tmp_postinc, 0)) {
2275 {
2276 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2277   tmp_addr = ADDSI (tmp_addr, 1);
2278 }
2279   {
2280     SI opval = tmp_addr;
2281     SET_H_GR (FLD (f_operand1), opval);
2282     written |= (1 << 9);
2283     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2284   }
2285 }
2286 }
2287 ; tmp_tmp_mem; }));
2288   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2289   tmp_carry = CPU (h_cbit);
2290   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2291 ((void) 0); /*nop*/
2292 {
2293   {
2294     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2295     CPU (h_cbit) = opval;
2296     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2297   }
2298   {
2299     BI opval = LTSI (tmp_newval, 0);
2300     CPU (h_nbit) = opval;
2301     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2302   }
2303   {
2304     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2305     CPU (h_zbit) = opval;
2306     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2307   }
2308   {
2309     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2310     CPU (h_vbit) = opval;
2311     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2312   }
2313 {
2314   {
2315     BI opval = 0;
2316     CPU (h_xbit) = opval;
2317     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2318   }
2319   {
2320     BI opval = 0;
2321     SET_H_INSN_PREFIXED_P (opval);
2322     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2323   }
2324 }
2325 }
2326 }
2327
2328   abuf->written = written;
2329 #undef FLD
2330 }
2331   NEXT (vpc);
2332
2333   CASE (sem, INSN_CMPU_M_W_M) : /* cmpu-m.w [${Rs}${inc}],$Rd */
2334 {
2335   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2336   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2337 #define FLD(f) abuf->fields.sfmt_addc_m.f
2338   int UNUSED written = 0;
2339   IADDR UNUSED pc = abuf->addr;
2340   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2341
2342 {
2343   SI tmp_tmpopd;
2344   SI tmp_tmpops;
2345   BI tmp_carry;
2346   SI tmp_newval;
2347   tmp_tmpops = ZEXTHISI (({   SI tmp_addr;
2348   HI tmp_tmp_mem;
2349   BI tmp_postinc;
2350   tmp_postinc = FLD (f_memmode);
2351 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2352 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2353 ; if (NEBI (tmp_postinc, 0)) {
2354 {
2355 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2356   tmp_addr = ADDSI (tmp_addr, 2);
2357 }
2358   {
2359     SI opval = tmp_addr;
2360     SET_H_GR (FLD (f_operand1), opval);
2361     written |= (1 << 9);
2362     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2363   }
2364 }
2365 }
2366 ; tmp_tmp_mem; }));
2367   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2368   tmp_carry = CPU (h_cbit);
2369   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2370 ((void) 0); /*nop*/
2371 {
2372   {
2373     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2374     CPU (h_cbit) = opval;
2375     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2376   }
2377   {
2378     BI opval = LTSI (tmp_newval, 0);
2379     CPU (h_nbit) = opval;
2380     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2381   }
2382   {
2383     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2384     CPU (h_zbit) = opval;
2385     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2386   }
2387   {
2388     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2389     CPU (h_vbit) = opval;
2390     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2391   }
2392 {
2393   {
2394     BI opval = 0;
2395     CPU (h_xbit) = opval;
2396     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2397   }
2398   {
2399     BI opval = 0;
2400     SET_H_INSN_PREFIXED_P (opval);
2401     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2402   }
2403 }
2404 }
2405 }
2406
2407   abuf->written = written;
2408 #undef FLD
2409 }
2410   NEXT (vpc);
2411
2412   CASE (sem, INSN_CMPUCBR) : /* [${Rs}${inc}],$Rd */
2413 {
2414   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2415   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2416 #define FLD(f) abuf->fields.sfmt_bound_cb.f
2417   int UNUSED written = 0;
2418   IADDR UNUSED pc = abuf->addr;
2419   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2420
2421 {
2422   SI tmp_tmpopd;
2423   SI tmp_tmpops;
2424   BI tmp_carry;
2425   SI tmp_newval;
2426   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
2427   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2428   tmp_carry = CPU (h_cbit);
2429   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2430 ((void) 0); /*nop*/
2431 {
2432   {
2433     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2434     CPU (h_cbit) = opval;
2435     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2436   }
2437   {
2438     BI opval = LTSI (tmp_newval, 0);
2439     CPU (h_nbit) = opval;
2440     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2441   }
2442   {
2443     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2444     CPU (h_zbit) = opval;
2445     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2446   }
2447   {
2448     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2449     CPU (h_vbit) = opval;
2450     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2451   }
2452 {
2453   {
2454     BI opval = 0;
2455     CPU (h_xbit) = opval;
2456     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2457   }
2458   {
2459     BI opval = 0;
2460     SET_H_INSN_PREFIXED_P (opval);
2461     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2462   }
2463 }
2464 }
2465 }
2466
2467 #undef FLD
2468 }
2469   NEXT (vpc);
2470
2471   CASE (sem, INSN_CMPUCWR) : /* [${Rs}${inc}],$Rd */
2472 {
2473   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2474   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2475 #define FLD(f) abuf->fields.sfmt_bound_cw.f
2476   int UNUSED written = 0;
2477   IADDR UNUSED pc = abuf->addr;
2478   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2479
2480 {
2481   SI tmp_tmpopd;
2482   SI tmp_tmpops;
2483   BI tmp_carry;
2484   SI tmp_newval;
2485   tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
2486   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
2487   tmp_carry = CPU (h_cbit);
2488   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
2489 ((void) 0); /*nop*/
2490 {
2491   {
2492     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
2493     CPU (h_cbit) = opval;
2494     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2495   }
2496   {
2497     BI opval = LTSI (tmp_newval, 0);
2498     CPU (h_nbit) = opval;
2499     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2500   }
2501   {
2502     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
2503     CPU (h_zbit) = opval;
2504     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2505   }
2506   {
2507     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
2508     CPU (h_vbit) = opval;
2509     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
2510   }
2511 {
2512   {
2513     BI opval = 0;
2514     CPU (h_xbit) = opval;
2515     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2516   }
2517   {
2518     BI opval = 0;
2519     SET_H_INSN_PREFIXED_P (opval);
2520     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2521   }
2522 }
2523 }
2524 }
2525
2526 #undef FLD
2527 }
2528   NEXT (vpc);
2529
2530   CASE (sem, INSN_MOVE_M_B_M) : /* move-m.b [${Rs}${inc}],${Rd} */
2531 {
2532   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2533   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2534 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
2535   int UNUSED written = 0;
2536   IADDR UNUSED pc = abuf->addr;
2537   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2538
2539 {
2540   SI tmp_tmp;
2541   tmp_tmp = ({   SI tmp_addr;
2542   QI tmp_tmp_mem;
2543   BI tmp_postinc;
2544   tmp_postinc = FLD (f_memmode);
2545 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2546 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2547 ; if (NEBI (tmp_postinc, 0)) {
2548 {
2549 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2550   tmp_addr = ADDSI (tmp_addr, 1);
2551 }
2552   {
2553     SI opval = tmp_addr;
2554     SET_H_GR (FLD (f_operand1), opval);
2555     written |= (1 << 10);
2556     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2557   }
2558 }
2559 }
2560 ; tmp_tmp_mem; });
2561 {
2562   SI tmp_oldregval;
2563   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
2564   {
2565     SI opval = ORSI (ANDSI (tmp_tmp, 255), ANDSI (tmp_oldregval, 0xffffff00));
2566     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
2567     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2568   }
2569 }
2570 {
2571   {
2572     BI opval = LTQI (tmp_tmp, 0);
2573     CPU (h_nbit) = opval;
2574     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2575   }
2576   {
2577     BI opval = ANDIF (EQQI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2578     CPU (h_zbit) = opval;
2579     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2580   }
2581 SET_H_CBIT_MOVE (0);
2582 SET_H_VBIT_MOVE (0);
2583 {
2584   {
2585     BI opval = 0;
2586     CPU (h_xbit) = opval;
2587     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2588   }
2589   {
2590     BI opval = 0;
2591     SET_H_INSN_PREFIXED_P (opval);
2592     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2593   }
2594 }
2595 }
2596 }
2597
2598   abuf->written = written;
2599 #undef FLD
2600 }
2601   NEXT (vpc);
2602
2603   CASE (sem, INSN_MOVE_M_W_M) : /* move-m.w [${Rs}${inc}],${Rd} */
2604 {
2605   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2606   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2607 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
2608   int UNUSED written = 0;
2609   IADDR UNUSED pc = abuf->addr;
2610   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2611
2612 {
2613   SI tmp_tmp;
2614   tmp_tmp = ({   SI tmp_addr;
2615   HI tmp_tmp_mem;
2616   BI tmp_postinc;
2617   tmp_postinc = FLD (f_memmode);
2618 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2619 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2620 ; if (NEBI (tmp_postinc, 0)) {
2621 {
2622 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2623   tmp_addr = ADDSI (tmp_addr, 2);
2624 }
2625   {
2626     SI opval = tmp_addr;
2627     SET_H_GR (FLD (f_operand1), opval);
2628     written |= (1 << 10);
2629     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2630   }
2631 }
2632 }
2633 ; tmp_tmp_mem; });
2634 {
2635   SI tmp_oldregval;
2636   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
2637   {
2638     SI opval = ORSI (ANDSI (tmp_tmp, 65535), ANDSI (tmp_oldregval, 0xffff0000));
2639     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
2640     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2641   }
2642 }
2643 {
2644   {
2645     BI opval = LTHI (tmp_tmp, 0);
2646     CPU (h_nbit) = opval;
2647     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2648   }
2649   {
2650     BI opval = ANDIF (EQHI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2651     CPU (h_zbit) = opval;
2652     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2653   }
2654 SET_H_CBIT_MOVE (0);
2655 SET_H_VBIT_MOVE (0);
2656 {
2657   {
2658     BI opval = 0;
2659     CPU (h_xbit) = opval;
2660     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2661   }
2662   {
2663     BI opval = 0;
2664     SET_H_INSN_PREFIXED_P (opval);
2665     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2666   }
2667 }
2668 }
2669 }
2670
2671   abuf->written = written;
2672 #undef FLD
2673 }
2674   NEXT (vpc);
2675
2676   CASE (sem, INSN_MOVE_M_D_M) : /* move-m.d [${Rs}${inc}],${Rd} */
2677 {
2678   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2679   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2680 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
2681   int UNUSED written = 0;
2682   IADDR UNUSED pc = abuf->addr;
2683   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2684
2685 {
2686   SI tmp_tmp;
2687   tmp_tmp = ({   SI tmp_addr;
2688   SI tmp_tmp_mem;
2689   BI tmp_postinc;
2690   tmp_postinc = FLD (f_memmode);
2691 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2692 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
2693 ; if (NEBI (tmp_postinc, 0)) {
2694 {
2695 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2696   tmp_addr = ADDSI (tmp_addr, 4);
2697 }
2698   {
2699     SI opval = tmp_addr;
2700     SET_H_GR (FLD (f_operand1), opval);
2701     written |= (1 << 9);
2702     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2703   }
2704 }
2705 }
2706 ; tmp_tmp_mem; });
2707   {
2708     SI opval = tmp_tmp;
2709     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
2710     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2711   }
2712 {
2713   {
2714     BI opval = LTSI (tmp_tmp, 0);
2715     CPU (h_nbit) = opval;
2716     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2717   }
2718   {
2719     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2720     CPU (h_zbit) = opval;
2721     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2722   }
2723 SET_H_CBIT_MOVE (0);
2724 SET_H_VBIT_MOVE (0);
2725 {
2726   {
2727     BI opval = 0;
2728     CPU (h_xbit) = opval;
2729     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2730   }
2731   {
2732     BI opval = 0;
2733     SET_H_INSN_PREFIXED_P (opval);
2734     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2735   }
2736 }
2737 }
2738 }
2739
2740   abuf->written = written;
2741 #undef FLD
2742 }
2743   NEXT (vpc);
2744
2745   CASE (sem, INSN_MOVS_M_B_M) : /* movs-m.b [${Rs}${inc}],${Rd} */
2746 {
2747   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2748   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2749 #define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
2750   int UNUSED written = 0;
2751   IADDR UNUSED pc = abuf->addr;
2752   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2753
2754 {
2755   SI tmp_tmp;
2756   tmp_tmp = EXTQISI (({   SI tmp_addr;
2757   QI tmp_tmp_mem;
2758   BI tmp_postinc;
2759   tmp_postinc = FLD (f_memmode);
2760 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2761 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2762 ; if (NEBI (tmp_postinc, 0)) {
2763 {
2764 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2765   tmp_addr = ADDSI (tmp_addr, 1);
2766 }
2767   {
2768     SI opval = tmp_addr;
2769     SET_H_GR (FLD (f_operand1), opval);
2770     written |= (1 << 8);
2771     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2772   }
2773 }
2774 }
2775 ; tmp_tmp_mem; }));
2776 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
2777   {
2778     SI opval = tmp_tmp;
2779     SET_H_GR (FLD (f_operand1), opval);
2780     written |= (1 << 8);
2781     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2782   }
2783 } else {
2784   {
2785     SI opval = tmp_tmp;
2786     SET_H_GR (FLD (f_operand2), opval);
2787     written |= (1 << 7);
2788     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2789   }
2790 }
2791 {
2792   {
2793     BI opval = LTSI (tmp_tmp, 0);
2794     CPU (h_nbit) = opval;
2795     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2796   }
2797   {
2798     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2799     CPU (h_zbit) = opval;
2800     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2801   }
2802 SET_H_CBIT_MOVE (0);
2803 SET_H_VBIT_MOVE (0);
2804 {
2805   {
2806     BI opval = 0;
2807     CPU (h_xbit) = opval;
2808     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2809   }
2810   {
2811     BI opval = 0;
2812     SET_H_INSN_PREFIXED_P (opval);
2813     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2814   }
2815 }
2816 }
2817 }
2818
2819   abuf->written = written;
2820 #undef FLD
2821 }
2822   NEXT (vpc);
2823
2824   CASE (sem, INSN_MOVS_M_W_M) : /* movs-m.w [${Rs}${inc}],${Rd} */
2825 {
2826   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2827   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2828 #define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
2829   int UNUSED written = 0;
2830   IADDR UNUSED pc = abuf->addr;
2831   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2832
2833 {
2834   SI tmp_tmp;
2835   tmp_tmp = EXTHISI (({   SI tmp_addr;
2836   HI tmp_tmp_mem;
2837   BI tmp_postinc;
2838   tmp_postinc = FLD (f_memmode);
2839 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2840 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2841 ; if (NEBI (tmp_postinc, 0)) {
2842 {
2843 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2844   tmp_addr = ADDSI (tmp_addr, 2);
2845 }
2846   {
2847     SI opval = tmp_addr;
2848     SET_H_GR (FLD (f_operand1), opval);
2849     written |= (1 << 8);
2850     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2851   }
2852 }
2853 }
2854 ; tmp_tmp_mem; }));
2855 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
2856   {
2857     SI opval = tmp_tmp;
2858     SET_H_GR (FLD (f_operand1), opval);
2859     written |= (1 << 8);
2860     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2861   }
2862 } else {
2863   {
2864     SI opval = tmp_tmp;
2865     SET_H_GR (FLD (f_operand2), opval);
2866     written |= (1 << 7);
2867     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2868   }
2869 }
2870 {
2871   {
2872     BI opval = LTSI (tmp_tmp, 0);
2873     CPU (h_nbit) = opval;
2874     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2875   }
2876   {
2877     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2878     CPU (h_zbit) = opval;
2879     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2880   }
2881 SET_H_CBIT_MOVE (0);
2882 SET_H_VBIT_MOVE (0);
2883 {
2884   {
2885     BI opval = 0;
2886     CPU (h_xbit) = opval;
2887     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2888   }
2889   {
2890     BI opval = 0;
2891     SET_H_INSN_PREFIXED_P (opval);
2892     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2893   }
2894 }
2895 }
2896 }
2897
2898   abuf->written = written;
2899 #undef FLD
2900 }
2901   NEXT (vpc);
2902
2903   CASE (sem, INSN_MOVU_M_B_M) : /* movu-m.b [${Rs}${inc}],${Rd} */
2904 {
2905   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2906   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2907 #define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
2908   int UNUSED written = 0;
2909   IADDR UNUSED pc = abuf->addr;
2910   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2911
2912 {
2913   SI tmp_tmp;
2914   tmp_tmp = ZEXTQISI (({   SI tmp_addr;
2915   QI tmp_tmp_mem;
2916   BI tmp_postinc;
2917   tmp_postinc = FLD (f_memmode);
2918 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2919 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
2920 ; if (NEBI (tmp_postinc, 0)) {
2921 {
2922 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
2923   tmp_addr = ADDSI (tmp_addr, 1);
2924 }
2925   {
2926     SI opval = tmp_addr;
2927     SET_H_GR (FLD (f_operand1), opval);
2928     written |= (1 << 8);
2929     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2930   }
2931 }
2932 }
2933 ; tmp_tmp_mem; }));
2934 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
2935   {
2936     SI opval = tmp_tmp;
2937     SET_H_GR (FLD (f_operand1), opval);
2938     written |= (1 << 8);
2939     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2940   }
2941 } else {
2942   {
2943     SI opval = tmp_tmp;
2944     SET_H_GR (FLD (f_operand2), opval);
2945     written |= (1 << 7);
2946     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2947   }
2948 }
2949 {
2950   {
2951     BI opval = LTSI (tmp_tmp, 0);
2952     CPU (h_nbit) = opval;
2953     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2954   }
2955   {
2956     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
2957     CPU (h_zbit) = opval;
2958     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2959   }
2960 SET_H_CBIT_MOVE (0);
2961 SET_H_VBIT_MOVE (0);
2962 {
2963   {
2964     BI opval = 0;
2965     CPU (h_xbit) = opval;
2966     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
2967   }
2968   {
2969     BI opval = 0;
2970     SET_H_INSN_PREFIXED_P (opval);
2971     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
2972   }
2973 }
2974 }
2975 }
2976
2977   abuf->written = written;
2978 #undef FLD
2979 }
2980   NEXT (vpc);
2981
2982   CASE (sem, INSN_MOVU_M_W_M) : /* movu-m.w [${Rs}${inc}],${Rd} */
2983 {
2984   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2985   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2986 #define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
2987   int UNUSED written = 0;
2988   IADDR UNUSED pc = abuf->addr;
2989   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2990
2991 {
2992   SI tmp_tmp;
2993   tmp_tmp = ZEXTHISI (({   SI tmp_addr;
2994   HI tmp_tmp_mem;
2995   BI tmp_postinc;
2996   tmp_postinc = FLD (f_memmode);
2997 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
2998 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
2999 ; if (NEBI (tmp_postinc, 0)) {
3000 {
3001 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3002   tmp_addr = ADDSI (tmp_addr, 2);
3003 }
3004   {
3005     SI opval = tmp_addr;
3006     SET_H_GR (FLD (f_operand1), opval);
3007     written |= (1 << 8);
3008     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3009   }
3010 }
3011 }
3012 ; tmp_tmp_mem; }));
3013 if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
3014   {
3015     SI opval = tmp_tmp;
3016     SET_H_GR (FLD (f_operand1), opval);
3017     written |= (1 << 8);
3018     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3019   }
3020 } else {
3021   {
3022     SI opval = tmp_tmp;
3023     SET_H_GR (FLD (f_operand2), opval);
3024     written |= (1 << 7);
3025     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3026   }
3027 }
3028 {
3029   {
3030     BI opval = LTSI (tmp_tmp, 0);
3031     CPU (h_nbit) = opval;
3032     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
3033   }
3034   {
3035     BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
3036     CPU (h_zbit) = opval;
3037     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
3038   }
3039 SET_H_CBIT_MOVE (0);
3040 SET_H_VBIT_MOVE (0);
3041 {
3042   {
3043     BI opval = 0;
3044     CPU (h_xbit) = opval;
3045     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3046   }
3047   {
3048     BI opval = 0;
3049     SET_H_INSN_PREFIXED_P (opval);
3050     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3051   }
3052 }
3053 }
3054 }
3055
3056   abuf->written = written;
3057 #undef FLD
3058 }
3059   NEXT (vpc);
3060
3061   CASE (sem, INSN_MOVE_R_SPRV32) : /* move ${Rs},${Pd} */
3062 {
3063   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3064   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3065 #define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
3066   int UNUSED written = 0;
3067   IADDR UNUSED pc = abuf->addr;
3068   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3069
3070 {
3071   SI tmp_tmp;
3072   SI tmp_rno;
3073   tmp_tmp = GET_H_GR (FLD (f_operand1));
3074   tmp_rno = FLD (f_operand2);
3075 if (ORIF (ORIF (EQSI (tmp_rno, 0), EQSI (tmp_rno, 1)), ORIF (EQSI (tmp_rno, 4), EQSI (tmp_rno, 8)))) {
3076 cgen_rtx_error (current_cpu, "move-r-spr: trying to set a read-only special register");
3077 }
3078  else {
3079   {
3080     SI opval = tmp_tmp;
3081     SET_H_SR (FLD (f_operand2), opval);
3082     written |= (1 << 2);
3083     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3084   }
3085 }
3086 {
3087   {
3088     BI opval = 0;
3089     CPU (h_xbit) = opval;
3090     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3091   }
3092   {
3093     BI opval = 0;
3094     SET_H_INSN_PREFIXED_P (opval);
3095     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3096   }
3097 }
3098 }
3099
3100   abuf->written = written;
3101 #undef FLD
3102 }
3103   NEXT (vpc);
3104
3105   CASE (sem, INSN_MOVE_SPR_RV32) : /* move ${Ps},${Rd-sfield} */
3106 {
3107   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3108   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3109 #define FLD(f) abuf->fields.sfmt_mcp.f
3110   int UNUSED written = 0;
3111   IADDR UNUSED pc = abuf->addr;
3112   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3113
3114 {
3115   SI tmp_grno;
3116   SI tmp_prno;
3117   SI tmp_newval;
3118   tmp_prno = FLD (f_operand2);
3119   tmp_newval = GET_H_SR (FLD (f_operand2));
3120 if (EQSI (tmp_prno, 2)) {
3121 {
3122   SI tmp_oldregval;
3123   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1));
3124   {
3125     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
3126     SET_H_GR (FLD (f_operand1), opval);
3127     written |= (1 << 4);
3128     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3129   }
3130 }
3131 }
3132  else if (EQSI (tmp_prno, 3)) {
3133 {
3134   SI tmp_oldregval;
3135   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1));
3136   {
3137     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
3138     SET_H_GR (FLD (f_operand1), opval);
3139     written |= (1 << 4);
3140     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3141   }
3142 }
3143 }
3144  else if (EQSI (tmp_prno, 5)) {
3145   {
3146     SI opval = tmp_newval;
3147     SET_H_GR (FLD (f_operand1), opval);
3148     written |= (1 << 4);
3149     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3150   }
3151 }
3152  else if (EQSI (tmp_prno, 6)) {
3153   {
3154     SI opval = tmp_newval;
3155     SET_H_GR (FLD (f_operand1), opval);
3156     written |= (1 << 4);
3157     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3158   }
3159 }
3160  else if (EQSI (tmp_prno, 7)) {
3161   {
3162     SI opval = tmp_newval;
3163     SET_H_GR (FLD (f_operand1), opval);
3164     written |= (1 << 4);
3165     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3166   }
3167 }
3168  else if (EQSI (tmp_prno, 9)) {
3169   {
3170     SI opval = tmp_newval;
3171     SET_H_GR (FLD (f_operand1), opval);
3172     written |= (1 << 4);
3173     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3174   }
3175 }
3176  else if (EQSI (tmp_prno, 10)) {
3177   {
3178     SI opval = tmp_newval;
3179     SET_H_GR (FLD (f_operand1), opval);
3180     written |= (1 << 4);
3181     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3182   }
3183 }
3184  else if (EQSI (tmp_prno, 11)) {
3185   {
3186     SI opval = tmp_newval;
3187     SET_H_GR (FLD (f_operand1), opval);
3188     written |= (1 << 4);
3189     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3190   }
3191 }
3192  else if (EQSI (tmp_prno, 12)) {
3193   {
3194     SI opval = tmp_newval;
3195     SET_H_GR (FLD (f_operand1), opval);
3196     written |= (1 << 4);
3197     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3198   }
3199 }
3200  else if (EQSI (tmp_prno, 13)) {
3201   {
3202     SI opval = tmp_newval;
3203     SET_H_GR (FLD (f_operand1), opval);
3204     written |= (1 << 4);
3205     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3206   }
3207 }
3208  else if (EQSI (tmp_prno, 14)) {
3209   {
3210     SI opval = tmp_newval;
3211     SET_H_GR (FLD (f_operand1), opval);
3212     written |= (1 << 4);
3213     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3214   }
3215 }
3216  else if (EQSI (tmp_prno, 15)) {
3217   {
3218     SI opval = tmp_newval;
3219     SET_H_GR (FLD (f_operand1), opval);
3220     written |= (1 << 4);
3221     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3222   }
3223 }
3224  else if (EQSI (tmp_prno, 0)) {
3225 {
3226   SI tmp_oldregval;
3227   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1));
3228   {
3229     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
3230     SET_H_GR (FLD (f_operand1), opval);
3231     written |= (1 << 4);
3232     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3233   }
3234 }
3235 }
3236  else if (EQSI (tmp_prno, 1)) {
3237 {
3238   SI tmp_oldregval;
3239   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1));
3240   {
3241     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
3242     SET_H_GR (FLD (f_operand1), opval);
3243     written |= (1 << 4);
3244     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3245   }
3246 }
3247 }
3248  else if (EQSI (tmp_prno, 4)) {
3249 {
3250   SI tmp_oldregval;
3251   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1));
3252   {
3253     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
3254     SET_H_GR (FLD (f_operand1), opval);
3255     written |= (1 << 4);
3256     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3257   }
3258 }
3259 }
3260  else if (EQSI (tmp_prno, 8)) {
3261   {
3262     SI opval = tmp_newval;
3263     SET_H_GR (FLD (f_operand1), opval);
3264     written |= (1 << 4);
3265     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3266   }
3267 }
3268  else {
3269 cgen_rtx_error (current_cpu, "move-spr-r from unimplemented register");
3270 }
3271 {
3272   {
3273     BI opval = 0;
3274     CPU (h_xbit) = opval;
3275     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3276   }
3277   {
3278     BI opval = 0;
3279     SET_H_INSN_PREFIXED_P (opval);
3280     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3281   }
3282 }
3283 }
3284
3285   abuf->written = written;
3286 #undef FLD
3287 }
3288   NEXT (vpc);
3289
3290   CASE (sem, INSN_MOVE_M_SPRV32) : /* move [${Rs}${inc}],${Pd} */
3291 {
3292   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3293   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3294 #define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
3295   int UNUSED written = 0;
3296   IADDR UNUSED pc = abuf->addr;
3297   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3298
3299 {
3300   SI tmp_rno;
3301   SI tmp_newval;
3302   tmp_rno = FLD (f_operand2);
3303 if (EQSI (tmp_rno, 2)) {
3304   tmp_newval = EXTQISI (({   SI tmp_addr;
3305   QI tmp_tmp_mem;
3306   BI tmp_postinc;
3307   tmp_postinc = FLD (f_memmode);
3308 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3309 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
3310 ; if (NEBI (tmp_postinc, 0)) {
3311 {
3312 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3313   tmp_addr = ADDSI (tmp_addr, 1);
3314 }
3315   {
3316     SI opval = tmp_addr;
3317     SET_H_GR (FLD (f_operand1), opval);
3318     written |= (1 << 8);
3319     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3320   }
3321 }
3322 }
3323 ; tmp_tmp_mem; }));
3324 }
3325  else if (EQSI (tmp_rno, 3)) {
3326   tmp_newval = EXTQISI (({   SI tmp_addr;
3327   QI tmp_tmp_mem;
3328   BI tmp_postinc;
3329   tmp_postinc = FLD (f_memmode);
3330 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3331 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
3332 ; if (NEBI (tmp_postinc, 0)) {
3333 {
3334 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3335   tmp_addr = ADDSI (tmp_addr, 1);
3336 }
3337   {
3338     SI opval = tmp_addr;
3339     SET_H_GR (FLD (f_operand1), opval);
3340     written |= (1 << 8);
3341     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3342   }
3343 }
3344 }
3345 ; tmp_tmp_mem; }));
3346 }
3347  else if (EQSI (tmp_rno, 5)) {
3348   tmp_newval = ({   SI tmp_addr;
3349   SI tmp_tmp_mem;
3350   BI tmp_postinc;
3351   tmp_postinc = FLD (f_memmode);
3352 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3353 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3354 ; if (NEBI (tmp_postinc, 0)) {
3355 {
3356 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3357   tmp_addr = ADDSI (tmp_addr, 4);
3358 }
3359   {
3360     SI opval = tmp_addr;
3361     SET_H_GR (FLD (f_operand1), opval);
3362     written |= (1 << 8);
3363     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3364   }
3365 }
3366 }
3367 ; tmp_tmp_mem; });
3368 }
3369  else if (EQSI (tmp_rno, 6)) {
3370   tmp_newval = ({   SI tmp_addr;
3371   SI tmp_tmp_mem;
3372   BI tmp_postinc;
3373   tmp_postinc = FLD (f_memmode);
3374 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3375 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3376 ; if (NEBI (tmp_postinc, 0)) {
3377 {
3378 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3379   tmp_addr = ADDSI (tmp_addr, 4);
3380 }
3381   {
3382     SI opval = tmp_addr;
3383     SET_H_GR (FLD (f_operand1), opval);
3384     written |= (1 << 8);
3385     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3386   }
3387 }
3388 }
3389 ; tmp_tmp_mem; });
3390 }
3391  else if (EQSI (tmp_rno, 7)) {
3392   tmp_newval = ({   SI tmp_addr;
3393   SI tmp_tmp_mem;
3394   BI tmp_postinc;
3395   tmp_postinc = FLD (f_memmode);
3396 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3397 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3398 ; if (NEBI (tmp_postinc, 0)) {
3399 {
3400 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3401   tmp_addr = ADDSI (tmp_addr, 4);
3402 }
3403   {
3404     SI opval = tmp_addr;
3405     SET_H_GR (FLD (f_operand1), opval);
3406     written |= (1 << 8);
3407     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3408   }
3409 }
3410 }
3411 ; tmp_tmp_mem; });
3412 }
3413  else if (EQSI (tmp_rno, 9)) {
3414   tmp_newval = ({   SI tmp_addr;
3415   SI tmp_tmp_mem;
3416   BI tmp_postinc;
3417   tmp_postinc = FLD (f_memmode);
3418 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3419 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3420 ; if (NEBI (tmp_postinc, 0)) {
3421 {
3422 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3423   tmp_addr = ADDSI (tmp_addr, 4);
3424 }
3425   {
3426     SI opval = tmp_addr;
3427     SET_H_GR (FLD (f_operand1), opval);
3428     written |= (1 << 8);
3429     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3430   }
3431 }
3432 }
3433 ; tmp_tmp_mem; });
3434 }
3435  else if (EQSI (tmp_rno, 10)) {
3436   tmp_newval = ({   SI tmp_addr;
3437   SI tmp_tmp_mem;
3438   BI tmp_postinc;
3439   tmp_postinc = FLD (f_memmode);
3440 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3441 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3442 ; if (NEBI (tmp_postinc, 0)) {
3443 {
3444 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3445   tmp_addr = ADDSI (tmp_addr, 4);
3446 }
3447   {
3448     SI opval = tmp_addr;
3449     SET_H_GR (FLD (f_operand1), opval);
3450     written |= (1 << 8);
3451     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3452   }
3453 }
3454 }
3455 ; tmp_tmp_mem; });
3456 }
3457  else if (EQSI (tmp_rno, 11)) {
3458   tmp_newval = ({   SI tmp_addr;
3459   SI tmp_tmp_mem;
3460   BI tmp_postinc;
3461   tmp_postinc = FLD (f_memmode);
3462 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3463 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3464 ; if (NEBI (tmp_postinc, 0)) {
3465 {
3466 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3467   tmp_addr = ADDSI (tmp_addr, 4);
3468 }
3469   {
3470     SI opval = tmp_addr;
3471     SET_H_GR (FLD (f_operand1), opval);
3472     written |= (1 << 8);
3473     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3474   }
3475 }
3476 }
3477 ; tmp_tmp_mem; });
3478 }
3479  else if (EQSI (tmp_rno, 12)) {
3480   tmp_newval = ({   SI tmp_addr;
3481   SI tmp_tmp_mem;
3482   BI tmp_postinc;
3483   tmp_postinc = FLD (f_memmode);
3484 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3485 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3486 ; if (NEBI (tmp_postinc, 0)) {
3487 {
3488 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3489   tmp_addr = ADDSI (tmp_addr, 4);
3490 }
3491   {
3492     SI opval = tmp_addr;
3493     SET_H_GR (FLD (f_operand1), opval);
3494     written |= (1 << 8);
3495     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3496   }
3497 }
3498 }
3499 ; tmp_tmp_mem; });
3500 }
3501  else if (EQSI (tmp_rno, 13)) {
3502   tmp_newval = ({   SI tmp_addr;
3503   SI tmp_tmp_mem;
3504   BI tmp_postinc;
3505   tmp_postinc = FLD (f_memmode);
3506 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3507 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3508 ; if (NEBI (tmp_postinc, 0)) {
3509 {
3510 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3511   tmp_addr = ADDSI (tmp_addr, 4);
3512 }
3513   {
3514     SI opval = tmp_addr;
3515     SET_H_GR (FLD (f_operand1), opval);
3516     written |= (1 << 8);
3517     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3518   }
3519 }
3520 }
3521 ; tmp_tmp_mem; });
3522 }
3523  else if (EQSI (tmp_rno, 14)) {
3524   tmp_newval = ({   SI tmp_addr;
3525   SI tmp_tmp_mem;
3526   BI tmp_postinc;
3527   tmp_postinc = FLD (f_memmode);
3528 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3529 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3530 ; if (NEBI (tmp_postinc, 0)) {
3531 {
3532 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3533   tmp_addr = ADDSI (tmp_addr, 4);
3534 }
3535   {
3536     SI opval = tmp_addr;
3537     SET_H_GR (FLD (f_operand1), opval);
3538     written |= (1 << 8);
3539     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3540   }
3541 }
3542 }
3543 ; tmp_tmp_mem; });
3544 }
3545  else if (EQSI (tmp_rno, 15)) {
3546   tmp_newval = ({   SI tmp_addr;
3547   SI tmp_tmp_mem;
3548   BI tmp_postinc;
3549   tmp_postinc = FLD (f_memmode);
3550 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
3551 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
3552 ; if (NEBI (tmp_postinc, 0)) {
3553 {
3554 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
3555   tmp_addr = ADDSI (tmp_addr, 4);
3556 }
3557   {
3558     SI opval = tmp_addr;
3559     SET_H_GR (FLD (f_operand1), opval);
3560     written |= (1 << 8);
3561     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
3562   }
3563 }
3564 }
3565 ; tmp_tmp_mem; });
3566 }
3567  else {
3568 cgen_rtx_error (current_cpu, "Trying to set unimplemented special register");
3569 }
3570   {
3571     SI opval = tmp_newval;
3572     SET_H_SR (FLD (f_operand2), opval);
3573     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3574   }
3575 {
3576   {
3577     BI opval = 0;
3578     CPU (h_xbit) = opval;
3579     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3580   }
3581   {
3582     BI opval = 0;
3583     SET_H_INSN_PREFIXED_P (opval);
3584     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3585   }
3586 }
3587 }
3588
3589   abuf->written = written;
3590 #undef FLD
3591 }
3592   NEXT (vpc);
3593
3594   CASE (sem, INSN_MOVE_C_SPRV32_P2) : /* move ${const32},${Pd} */
3595 {
3596   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3597   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3598 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3599   int UNUSED written = 0;
3600   IADDR UNUSED pc = abuf->addr;
3601   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3602
3603 {
3604   {
3605     SI opval = FLD (f_indir_pc__dword);
3606     SET_H_SR (FLD (f_operand2), opval);
3607     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3608   }
3609 {
3610   {
3611     BI opval = 0;
3612     CPU (h_xbit) = opval;
3613     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3614   }
3615   {
3616     BI opval = 0;
3617     SET_H_INSN_PREFIXED_P (opval);
3618     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3619   }
3620 }
3621 }
3622
3623 #undef FLD
3624 }
3625   NEXT (vpc);
3626
3627   CASE (sem, INSN_MOVE_C_SPRV32_P3) : /* move ${const32},${Pd} */
3628 {
3629   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3630   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3631 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3632   int UNUSED written = 0;
3633   IADDR UNUSED pc = abuf->addr;
3634   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3635
3636 {
3637   {
3638     SI opval = FLD (f_indir_pc__dword);
3639     SET_H_SR (FLD (f_operand2), opval);
3640     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3641   }
3642 {
3643   {
3644     BI opval = 0;
3645     CPU (h_xbit) = opval;
3646     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3647   }
3648   {
3649     BI opval = 0;
3650     SET_H_INSN_PREFIXED_P (opval);
3651     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3652   }
3653 }
3654 }
3655
3656 #undef FLD
3657 }
3658   NEXT (vpc);
3659
3660   CASE (sem, INSN_MOVE_C_SPRV32_P5) : /* move ${const32},${Pd} */
3661 {
3662   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3663   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3664 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3665   int UNUSED written = 0;
3666   IADDR UNUSED pc = abuf->addr;
3667   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3668
3669 {
3670   {
3671     SI opval = FLD (f_indir_pc__dword);
3672     SET_H_SR (FLD (f_operand2), opval);
3673     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3674   }
3675 {
3676   {
3677     BI opval = 0;
3678     CPU (h_xbit) = opval;
3679     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3680   }
3681   {
3682     BI opval = 0;
3683     SET_H_INSN_PREFIXED_P (opval);
3684     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3685   }
3686 }
3687 }
3688
3689 #undef FLD
3690 }
3691   NEXT (vpc);
3692
3693   CASE (sem, INSN_MOVE_C_SPRV32_P6) : /* move ${const32},${Pd} */
3694 {
3695   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3696   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3697 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3698   int UNUSED written = 0;
3699   IADDR UNUSED pc = abuf->addr;
3700   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3701
3702 {
3703   {
3704     SI opval = FLD (f_indir_pc__dword);
3705     SET_H_SR (FLD (f_operand2), opval);
3706     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3707   }
3708 {
3709   {
3710     BI opval = 0;
3711     CPU (h_xbit) = opval;
3712     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3713   }
3714   {
3715     BI opval = 0;
3716     SET_H_INSN_PREFIXED_P (opval);
3717     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3718   }
3719 }
3720 }
3721
3722 #undef FLD
3723 }
3724   NEXT (vpc);
3725
3726   CASE (sem, INSN_MOVE_C_SPRV32_P7) : /* move ${const32},${Pd} */
3727 {
3728   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3729   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3730 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3731   int UNUSED written = 0;
3732   IADDR UNUSED pc = abuf->addr;
3733   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3734
3735 {
3736   {
3737     SI opval = FLD (f_indir_pc__dword);
3738     SET_H_SR (FLD (f_operand2), opval);
3739     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3740   }
3741 {
3742   {
3743     BI opval = 0;
3744     CPU (h_xbit) = opval;
3745     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3746   }
3747   {
3748     BI opval = 0;
3749     SET_H_INSN_PREFIXED_P (opval);
3750     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3751   }
3752 }
3753 }
3754
3755 #undef FLD
3756 }
3757   NEXT (vpc);
3758
3759   CASE (sem, INSN_MOVE_C_SPRV32_P9) : /* move ${const32},${Pd} */
3760 {
3761   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3762   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3763 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3764   int UNUSED written = 0;
3765   IADDR UNUSED pc = abuf->addr;
3766   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3767
3768 {
3769   {
3770     SI opval = FLD (f_indir_pc__dword);
3771     SET_H_SR (FLD (f_operand2), opval);
3772     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3773   }
3774 {
3775   {
3776     BI opval = 0;
3777     CPU (h_xbit) = opval;
3778     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3779   }
3780   {
3781     BI opval = 0;
3782     SET_H_INSN_PREFIXED_P (opval);
3783     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3784   }
3785 }
3786 }
3787
3788 #undef FLD
3789 }
3790   NEXT (vpc);
3791
3792   CASE (sem, INSN_MOVE_C_SPRV32_P10) : /* move ${const32},${Pd} */
3793 {
3794   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3795   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3796 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3797   int UNUSED written = 0;
3798   IADDR UNUSED pc = abuf->addr;
3799   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3800
3801 {
3802   {
3803     SI opval = FLD (f_indir_pc__dword);
3804     SET_H_SR (FLD (f_operand2), opval);
3805     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3806   }
3807 {
3808   {
3809     BI opval = 0;
3810     CPU (h_xbit) = opval;
3811     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3812   }
3813   {
3814     BI opval = 0;
3815     SET_H_INSN_PREFIXED_P (opval);
3816     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3817   }
3818 }
3819 }
3820
3821 #undef FLD
3822 }
3823   NEXT (vpc);
3824
3825   CASE (sem, INSN_MOVE_C_SPRV32_P11) : /* move ${const32},${Pd} */
3826 {
3827   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3828   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3829 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3830   int UNUSED written = 0;
3831   IADDR UNUSED pc = abuf->addr;
3832   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3833
3834 {
3835   {
3836     SI opval = FLD (f_indir_pc__dword);
3837     SET_H_SR (FLD (f_operand2), opval);
3838     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3839   }
3840 {
3841   {
3842     BI opval = 0;
3843     CPU (h_xbit) = opval;
3844     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3845   }
3846   {
3847     BI opval = 0;
3848     SET_H_INSN_PREFIXED_P (opval);
3849     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3850   }
3851 }
3852 }
3853
3854 #undef FLD
3855 }
3856   NEXT (vpc);
3857
3858   CASE (sem, INSN_MOVE_C_SPRV32_P12) : /* move ${const32},${Pd} */
3859 {
3860   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3861   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3862 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3863   int UNUSED written = 0;
3864   IADDR UNUSED pc = abuf->addr;
3865   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3866
3867 {
3868   {
3869     SI opval = FLD (f_indir_pc__dword);
3870     SET_H_SR (FLD (f_operand2), opval);
3871     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3872   }
3873 {
3874   {
3875     BI opval = 0;
3876     CPU (h_xbit) = opval;
3877     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3878   }
3879   {
3880     BI opval = 0;
3881     SET_H_INSN_PREFIXED_P (opval);
3882     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3883   }
3884 }
3885 }
3886
3887 #undef FLD
3888 }
3889   NEXT (vpc);
3890
3891   CASE (sem, INSN_MOVE_C_SPRV32_P13) : /* move ${const32},${Pd} */
3892 {
3893   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3894   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3895 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3896   int UNUSED written = 0;
3897   IADDR UNUSED pc = abuf->addr;
3898   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3899
3900 {
3901   {
3902     SI opval = FLD (f_indir_pc__dword);
3903     SET_H_SR (FLD (f_operand2), opval);
3904     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3905   }
3906 {
3907   {
3908     BI opval = 0;
3909     CPU (h_xbit) = opval;
3910     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3911   }
3912   {
3913     BI opval = 0;
3914     SET_H_INSN_PREFIXED_P (opval);
3915     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3916   }
3917 }
3918 }
3919
3920 #undef FLD
3921 }
3922   NEXT (vpc);
3923
3924   CASE (sem, INSN_MOVE_C_SPRV32_P14) : /* move ${const32},${Pd} */
3925 {
3926   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3927   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3928 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3929   int UNUSED written = 0;
3930   IADDR UNUSED pc = abuf->addr;
3931   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3932
3933 {
3934   {
3935     SI opval = FLD (f_indir_pc__dword);
3936     SET_H_SR (FLD (f_operand2), opval);
3937     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3938   }
3939 {
3940   {
3941     BI opval = 0;
3942     CPU (h_xbit) = opval;
3943     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3944   }
3945   {
3946     BI opval = 0;
3947     SET_H_INSN_PREFIXED_P (opval);
3948     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3949   }
3950 }
3951 }
3952
3953 #undef FLD
3954 }
3955   NEXT (vpc);
3956
3957   CASE (sem, INSN_MOVE_C_SPRV32_P15) : /* move ${const32},${Pd} */
3958 {
3959   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3960   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3961 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
3962   int UNUSED written = 0;
3963   IADDR UNUSED pc = abuf->addr;
3964   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
3965
3966 {
3967   {
3968     SI opval = FLD (f_indir_pc__dword);
3969     SET_H_SR (FLD (f_operand2), opval);
3970     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
3971   }
3972 {
3973   {
3974     BI opval = 0;
3975     CPU (h_xbit) = opval;
3976     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
3977   }
3978   {
3979     BI opval = 0;
3980     SET_H_INSN_PREFIXED_P (opval);
3981     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
3982   }
3983 }
3984 }
3985
3986 #undef FLD
3987 }
3988   NEXT (vpc);
3989
3990   CASE (sem, INSN_MOVE_SPR_MV32) : /* move ${Ps},[${Rd-sfield}${inc}] */
3991 {
3992   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3993   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3994 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
3995   int UNUSED written = 0;
3996   IADDR UNUSED pc = abuf->addr;
3997   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3998
3999 {
4000   SI tmp_rno;
4001   tmp_rno = FLD (f_operand2);
4002 if (EQSI (tmp_rno, 2)) {
4003 {
4004   SI tmp_addr;
4005   BI tmp_postinc;
4006   tmp_postinc = FLD (f_memmode);
4007   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4008 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4009 if (EQBI (CPU (h_pbit), 0)) {
4010 {
4011   {
4012     QI opval = GET_H_SR (FLD (f_operand2));
4013     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4014     written |= (1 << 12);
4015     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4016   }
4017   {
4018     BI opval = CPU (h_pbit);
4019     CPU (h_cbit) = opval;
4020     written |= (1 << 10);
4021     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4022   }
4023 }
4024 } else {
4025   {
4026     BI opval = 1;
4027     CPU (h_cbit) = opval;
4028     written |= (1 << 10);
4029     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4030   }
4031 }
4032 } else {
4033   {
4034     QI opval = GET_H_SR (FLD (f_operand2));
4035     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4036     written |= (1 << 12);
4037     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4038   }
4039 }
4040 if (NEBI (tmp_postinc, 0)) {
4041 {
4042 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4043   tmp_addr = ADDSI (tmp_addr, 1);
4044 }
4045   {
4046     SI opval = tmp_addr;
4047     SET_H_GR (FLD (f_operand1), opval);
4048     written |= (1 << 9);
4049     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4050   }
4051 }
4052 }
4053 }
4054 }
4055  else if (EQSI (tmp_rno, 3)) {
4056 {
4057   SI tmp_addr;
4058   BI tmp_postinc;
4059   tmp_postinc = FLD (f_memmode);
4060   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4061 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4062 if (EQBI (CPU (h_pbit), 0)) {
4063 {
4064   {
4065     QI opval = GET_H_SR (FLD (f_operand2));
4066     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4067     written |= (1 << 12);
4068     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4069   }
4070   {
4071     BI opval = CPU (h_pbit);
4072     CPU (h_cbit) = opval;
4073     written |= (1 << 10);
4074     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4075   }
4076 }
4077 } else {
4078   {
4079     BI opval = 1;
4080     CPU (h_cbit) = opval;
4081     written |= (1 << 10);
4082     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4083   }
4084 }
4085 } else {
4086   {
4087     QI opval = GET_H_SR (FLD (f_operand2));
4088     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4089     written |= (1 << 12);
4090     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4091   }
4092 }
4093 if (NEBI (tmp_postinc, 0)) {
4094 {
4095 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4096   tmp_addr = ADDSI (tmp_addr, 1);
4097 }
4098   {
4099     SI opval = tmp_addr;
4100     SET_H_GR (FLD (f_operand1), opval);
4101     written |= (1 << 9);
4102     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4103   }
4104 }
4105 }
4106 }
4107 }
4108  else if (EQSI (tmp_rno, 5)) {
4109 {
4110   SI tmp_addr;
4111   BI tmp_postinc;
4112   tmp_postinc = FLD (f_memmode);
4113   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4114 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4115 if (EQBI (CPU (h_pbit), 0)) {
4116 {
4117   {
4118     SI opval = GET_H_SR (FLD (f_operand2));
4119     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4120     written |= (1 << 13);
4121     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4122   }
4123   {
4124     BI opval = CPU (h_pbit);
4125     CPU (h_cbit) = opval;
4126     written |= (1 << 10);
4127     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4128   }
4129 }
4130 } else {
4131   {
4132     BI opval = 1;
4133     CPU (h_cbit) = opval;
4134     written |= (1 << 10);
4135     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4136   }
4137 }
4138 } else {
4139   {
4140     SI opval = GET_H_SR (FLD (f_operand2));
4141     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4142     written |= (1 << 13);
4143     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4144   }
4145 }
4146 if (NEBI (tmp_postinc, 0)) {
4147 {
4148 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4149   tmp_addr = ADDSI (tmp_addr, 4);
4150 }
4151   {
4152     SI opval = tmp_addr;
4153     SET_H_GR (FLD (f_operand1), opval);
4154     written |= (1 << 9);
4155     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4156   }
4157 }
4158 }
4159 }
4160 }
4161  else if (EQSI (tmp_rno, 6)) {
4162 {
4163   SI tmp_addr;
4164   BI tmp_postinc;
4165   tmp_postinc = FLD (f_memmode);
4166   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4167 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4168 if (EQBI (CPU (h_pbit), 0)) {
4169 {
4170   {
4171     SI opval = GET_H_SR (FLD (f_operand2));
4172     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4173     written |= (1 << 13);
4174     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4175   }
4176   {
4177     BI opval = CPU (h_pbit);
4178     CPU (h_cbit) = opval;
4179     written |= (1 << 10);
4180     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4181   }
4182 }
4183 } else {
4184   {
4185     BI opval = 1;
4186     CPU (h_cbit) = opval;
4187     written |= (1 << 10);
4188     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4189   }
4190 }
4191 } else {
4192   {
4193     SI opval = GET_H_SR (FLD (f_operand2));
4194     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4195     written |= (1 << 13);
4196     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4197   }
4198 }
4199 if (NEBI (tmp_postinc, 0)) {
4200 {
4201 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4202   tmp_addr = ADDSI (tmp_addr, 4);
4203 }
4204   {
4205     SI opval = tmp_addr;
4206     SET_H_GR (FLD (f_operand1), opval);
4207     written |= (1 << 9);
4208     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4209   }
4210 }
4211 }
4212 }
4213 }
4214  else if (EQSI (tmp_rno, 7)) {
4215 {
4216   SI tmp_addr;
4217   BI tmp_postinc;
4218   tmp_postinc = FLD (f_memmode);
4219   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4220 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4221 if (EQBI (CPU (h_pbit), 0)) {
4222 {
4223   {
4224     SI opval = GET_H_SR (FLD (f_operand2));
4225     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4226     written |= (1 << 13);
4227     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4228   }
4229   {
4230     BI opval = CPU (h_pbit);
4231     CPU (h_cbit) = opval;
4232     written |= (1 << 10);
4233     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4234   }
4235 }
4236 } else {
4237   {
4238     BI opval = 1;
4239     CPU (h_cbit) = opval;
4240     written |= (1 << 10);
4241     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4242   }
4243 }
4244 } else {
4245   {
4246     SI opval = GET_H_SR (FLD (f_operand2));
4247     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4248     written |= (1 << 13);
4249     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4250   }
4251 }
4252 if (NEBI (tmp_postinc, 0)) {
4253 {
4254 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4255   tmp_addr = ADDSI (tmp_addr, 4);
4256 }
4257   {
4258     SI opval = tmp_addr;
4259     SET_H_GR (FLD (f_operand1), opval);
4260     written |= (1 << 9);
4261     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4262   }
4263 }
4264 }
4265 }
4266 }
4267  else if (EQSI (tmp_rno, 9)) {
4268 {
4269   SI tmp_addr;
4270   BI tmp_postinc;
4271   tmp_postinc = FLD (f_memmode);
4272   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4273 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4274 if (EQBI (CPU (h_pbit), 0)) {
4275 {
4276   {
4277     SI opval = GET_H_SR (FLD (f_operand2));
4278     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4279     written |= (1 << 13);
4280     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4281   }
4282   {
4283     BI opval = CPU (h_pbit);
4284     CPU (h_cbit) = opval;
4285     written |= (1 << 10);
4286     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4287   }
4288 }
4289 } else {
4290   {
4291     BI opval = 1;
4292     CPU (h_cbit) = opval;
4293     written |= (1 << 10);
4294     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4295   }
4296 }
4297 } else {
4298   {
4299     SI opval = GET_H_SR (FLD (f_operand2));
4300     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4301     written |= (1 << 13);
4302     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4303   }
4304 }
4305 if (NEBI (tmp_postinc, 0)) {
4306 {
4307 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4308   tmp_addr = ADDSI (tmp_addr, 4);
4309 }
4310   {
4311     SI opval = tmp_addr;
4312     SET_H_GR (FLD (f_operand1), opval);
4313     written |= (1 << 9);
4314     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4315   }
4316 }
4317 }
4318 }
4319 }
4320  else if (EQSI (tmp_rno, 10)) {
4321 {
4322   SI tmp_addr;
4323   BI tmp_postinc;
4324   tmp_postinc = FLD (f_memmode);
4325   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4326 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4327 if (EQBI (CPU (h_pbit), 0)) {
4328 {
4329   {
4330     SI opval = GET_H_SR (FLD (f_operand2));
4331     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4332     written |= (1 << 13);
4333     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4334   }
4335   {
4336     BI opval = CPU (h_pbit);
4337     CPU (h_cbit) = opval;
4338     written |= (1 << 10);
4339     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4340   }
4341 }
4342 } else {
4343   {
4344     BI opval = 1;
4345     CPU (h_cbit) = opval;
4346     written |= (1 << 10);
4347     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4348   }
4349 }
4350 } else {
4351   {
4352     SI opval = GET_H_SR (FLD (f_operand2));
4353     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4354     written |= (1 << 13);
4355     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4356   }
4357 }
4358 if (NEBI (tmp_postinc, 0)) {
4359 {
4360 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4361   tmp_addr = ADDSI (tmp_addr, 4);
4362 }
4363   {
4364     SI opval = tmp_addr;
4365     SET_H_GR (FLD (f_operand1), opval);
4366     written |= (1 << 9);
4367     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4368   }
4369 }
4370 }
4371 }
4372 }
4373  else if (EQSI (tmp_rno, 11)) {
4374 {
4375   SI tmp_addr;
4376   BI tmp_postinc;
4377   tmp_postinc = FLD (f_memmode);
4378   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4379 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4380 if (EQBI (CPU (h_pbit), 0)) {
4381 {
4382   {
4383     SI opval = GET_H_SR (FLD (f_operand2));
4384     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4385     written |= (1 << 13);
4386     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4387   }
4388   {
4389     BI opval = CPU (h_pbit);
4390     CPU (h_cbit) = opval;
4391     written |= (1 << 10);
4392     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4393   }
4394 }
4395 } else {
4396   {
4397     BI opval = 1;
4398     CPU (h_cbit) = opval;
4399     written |= (1 << 10);
4400     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4401   }
4402 }
4403 } else {
4404   {
4405     SI opval = GET_H_SR (FLD (f_operand2));
4406     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4407     written |= (1 << 13);
4408     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4409   }
4410 }
4411 if (NEBI (tmp_postinc, 0)) {
4412 {
4413 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4414   tmp_addr = ADDSI (tmp_addr, 4);
4415 }
4416   {
4417     SI opval = tmp_addr;
4418     SET_H_GR (FLD (f_operand1), opval);
4419     written |= (1 << 9);
4420     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4421   }
4422 }
4423 }
4424 }
4425 }
4426  else if (EQSI (tmp_rno, 12)) {
4427 {
4428   SI tmp_addr;
4429   BI tmp_postinc;
4430   tmp_postinc = FLD (f_memmode);
4431   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4432 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4433 if (EQBI (CPU (h_pbit), 0)) {
4434 {
4435   {
4436     SI opval = GET_H_SR (FLD (f_operand2));
4437     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4438     written |= (1 << 13);
4439     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4440   }
4441   {
4442     BI opval = CPU (h_pbit);
4443     CPU (h_cbit) = opval;
4444     written |= (1 << 10);
4445     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4446   }
4447 }
4448 } else {
4449   {
4450     BI opval = 1;
4451     CPU (h_cbit) = opval;
4452     written |= (1 << 10);
4453     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4454   }
4455 }
4456 } else {
4457   {
4458     SI opval = GET_H_SR (FLD (f_operand2));
4459     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4460     written |= (1 << 13);
4461     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4462   }
4463 }
4464 if (NEBI (tmp_postinc, 0)) {
4465 {
4466 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4467   tmp_addr = ADDSI (tmp_addr, 4);
4468 }
4469   {
4470     SI opval = tmp_addr;
4471     SET_H_GR (FLD (f_operand1), opval);
4472     written |= (1 << 9);
4473     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4474   }
4475 }
4476 }
4477 }
4478 }
4479  else if (EQSI (tmp_rno, 13)) {
4480 {
4481   SI tmp_addr;
4482   BI tmp_postinc;
4483   tmp_postinc = FLD (f_memmode);
4484   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4485 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4486 if (EQBI (CPU (h_pbit), 0)) {
4487 {
4488   {
4489     SI opval = GET_H_SR (FLD (f_operand2));
4490     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4491     written |= (1 << 13);
4492     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4493   }
4494   {
4495     BI opval = CPU (h_pbit);
4496     CPU (h_cbit) = opval;
4497     written |= (1 << 10);
4498     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4499   }
4500 }
4501 } else {
4502   {
4503     BI opval = 1;
4504     CPU (h_cbit) = opval;
4505     written |= (1 << 10);
4506     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4507   }
4508 }
4509 } else {
4510   {
4511     SI opval = GET_H_SR (FLD (f_operand2));
4512     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4513     written |= (1 << 13);
4514     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4515   }
4516 }
4517 if (NEBI (tmp_postinc, 0)) {
4518 {
4519 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4520   tmp_addr = ADDSI (tmp_addr, 4);
4521 }
4522   {
4523     SI opval = tmp_addr;
4524     SET_H_GR (FLD (f_operand1), opval);
4525     written |= (1 << 9);
4526     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4527   }
4528 }
4529 }
4530 }
4531 }
4532  else if (EQSI (tmp_rno, 14)) {
4533 {
4534   SI tmp_addr;
4535   BI tmp_postinc;
4536   tmp_postinc = FLD (f_memmode);
4537   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4538 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4539 if (EQBI (CPU (h_pbit), 0)) {
4540 {
4541   {
4542     SI opval = GET_H_SR (FLD (f_operand2));
4543     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4544     written |= (1 << 13);
4545     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4546   }
4547   {
4548     BI opval = CPU (h_pbit);
4549     CPU (h_cbit) = opval;
4550     written |= (1 << 10);
4551     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4552   }
4553 }
4554 } else {
4555   {
4556     BI opval = 1;
4557     CPU (h_cbit) = opval;
4558     written |= (1 << 10);
4559     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4560   }
4561 }
4562 } else {
4563   {
4564     SI opval = GET_H_SR (FLD (f_operand2));
4565     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4566     written |= (1 << 13);
4567     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4568   }
4569 }
4570 if (NEBI (tmp_postinc, 0)) {
4571 {
4572 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4573   tmp_addr = ADDSI (tmp_addr, 4);
4574 }
4575   {
4576     SI opval = tmp_addr;
4577     SET_H_GR (FLD (f_operand1), opval);
4578     written |= (1 << 9);
4579     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4580   }
4581 }
4582 }
4583 }
4584 }
4585  else if (EQSI (tmp_rno, 15)) {
4586 {
4587   SI tmp_addr;
4588   BI tmp_postinc;
4589   tmp_postinc = FLD (f_memmode);
4590   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4591 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4592 if (EQBI (CPU (h_pbit), 0)) {
4593 {
4594   {
4595     SI opval = GET_H_SR (FLD (f_operand2));
4596     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4597     written |= (1 << 13);
4598     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4599   }
4600   {
4601     BI opval = CPU (h_pbit);
4602     CPU (h_cbit) = opval;
4603     written |= (1 << 10);
4604     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4605   }
4606 }
4607 } else {
4608   {
4609     BI opval = 1;
4610     CPU (h_cbit) = opval;
4611     written |= (1 << 10);
4612     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4613   }
4614 }
4615 } else {
4616   {
4617     SI opval = GET_H_SR (FLD (f_operand2));
4618     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4619     written |= (1 << 13);
4620     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4621   }
4622 }
4623 if (NEBI (tmp_postinc, 0)) {
4624 {
4625 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4626   tmp_addr = ADDSI (tmp_addr, 4);
4627 }
4628   {
4629     SI opval = tmp_addr;
4630     SET_H_GR (FLD (f_operand1), opval);
4631     written |= (1 << 9);
4632     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4633   }
4634 }
4635 }
4636 }
4637 }
4638  else if (EQSI (tmp_rno, 0)) {
4639 {
4640   SI tmp_addr;
4641   BI tmp_postinc;
4642   tmp_postinc = FLD (f_memmode);
4643   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4644 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4645 if (EQBI (CPU (h_pbit), 0)) {
4646 {
4647   {
4648     QI opval = GET_H_SR (FLD (f_operand2));
4649     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4650     written |= (1 << 12);
4651     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4652   }
4653   {
4654     BI opval = CPU (h_pbit);
4655     CPU (h_cbit) = opval;
4656     written |= (1 << 10);
4657     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4658   }
4659 }
4660 } else {
4661   {
4662     BI opval = 1;
4663     CPU (h_cbit) = opval;
4664     written |= (1 << 10);
4665     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4666   }
4667 }
4668 } else {
4669   {
4670     QI opval = GET_H_SR (FLD (f_operand2));
4671     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4672     written |= (1 << 12);
4673     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4674   }
4675 }
4676 if (NEBI (tmp_postinc, 0)) {
4677 {
4678 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4679   tmp_addr = ADDSI (tmp_addr, 1);
4680 }
4681   {
4682     SI opval = tmp_addr;
4683     SET_H_GR (FLD (f_operand1), opval);
4684     written |= (1 << 9);
4685     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4686   }
4687 }
4688 }
4689 }
4690 }
4691  else if (EQSI (tmp_rno, 1)) {
4692 {
4693   SI tmp_addr;
4694   BI tmp_postinc;
4695   tmp_postinc = FLD (f_memmode);
4696   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4697 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4698 if (EQBI (CPU (h_pbit), 0)) {
4699 {
4700   {
4701     QI opval = GET_H_SR (FLD (f_operand2));
4702     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4703     written |= (1 << 12);
4704     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4705   }
4706   {
4707     BI opval = CPU (h_pbit);
4708     CPU (h_cbit) = opval;
4709     written |= (1 << 10);
4710     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4711   }
4712 }
4713 } else {
4714   {
4715     BI opval = 1;
4716     CPU (h_cbit) = opval;
4717     written |= (1 << 10);
4718     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4719   }
4720 }
4721 } else {
4722   {
4723     QI opval = GET_H_SR (FLD (f_operand2));
4724     SETMEMQI (current_cpu, pc, tmp_addr, opval);
4725     written |= (1 << 12);
4726     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4727   }
4728 }
4729 if (NEBI (tmp_postinc, 0)) {
4730 {
4731 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4732   tmp_addr = ADDSI (tmp_addr, 1);
4733 }
4734   {
4735     SI opval = tmp_addr;
4736     SET_H_GR (FLD (f_operand1), opval);
4737     written |= (1 << 9);
4738     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4739   }
4740 }
4741 }
4742 }
4743 }
4744  else if (EQSI (tmp_rno, 4)) {
4745 {
4746   SI tmp_addr;
4747   BI tmp_postinc;
4748   tmp_postinc = FLD (f_memmode);
4749   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4750 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4751 if (EQBI (CPU (h_pbit), 0)) {
4752 {
4753   {
4754     HI opval = GET_H_SR (FLD (f_operand2));
4755     SETMEMHI (current_cpu, pc, tmp_addr, opval);
4756     written |= (1 << 11);
4757     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4758   }
4759   {
4760     BI opval = CPU (h_pbit);
4761     CPU (h_cbit) = opval;
4762     written |= (1 << 10);
4763     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4764   }
4765 }
4766 } else {
4767   {
4768     BI opval = 1;
4769     CPU (h_cbit) = opval;
4770     written |= (1 << 10);
4771     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4772   }
4773 }
4774 } else {
4775   {
4776     HI opval = GET_H_SR (FLD (f_operand2));
4777     SETMEMHI (current_cpu, pc, tmp_addr, opval);
4778     written |= (1 << 11);
4779     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4780   }
4781 }
4782 if (NEBI (tmp_postinc, 0)) {
4783 {
4784 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4785   tmp_addr = ADDSI (tmp_addr, 2);
4786 }
4787   {
4788     SI opval = tmp_addr;
4789     SET_H_GR (FLD (f_operand1), opval);
4790     written |= (1 << 9);
4791     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4792   }
4793 }
4794 }
4795 }
4796 }
4797  else if (EQSI (tmp_rno, 8)) {
4798 {
4799   SI tmp_addr;
4800   BI tmp_postinc;
4801   tmp_postinc = FLD (f_memmode);
4802   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
4803 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
4804 if (EQBI (CPU (h_pbit), 0)) {
4805 {
4806   {
4807     SI opval = GET_H_SR (FLD (f_operand2));
4808     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4809     written |= (1 << 13);
4810     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4811   }
4812   {
4813     BI opval = CPU (h_pbit);
4814     CPU (h_cbit) = opval;
4815     written |= (1 << 10);
4816     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4817   }
4818 }
4819 } else {
4820   {
4821     BI opval = 1;
4822     CPU (h_cbit) = opval;
4823     written |= (1 << 10);
4824     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
4825   }
4826 }
4827 } else {
4828   {
4829     SI opval = GET_H_SR (FLD (f_operand2));
4830     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4831     written |= (1 << 13);
4832     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4833   }
4834 }
4835 if (NEBI (tmp_postinc, 0)) {
4836 {
4837 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
4838   tmp_addr = ADDSI (tmp_addr, 4);
4839 }
4840   {
4841     SI opval = tmp_addr;
4842     SET_H_GR (FLD (f_operand1), opval);
4843     written |= (1 << 9);
4844     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4845   }
4846 }
4847 }
4848 }
4849 }
4850  else {
4851 cgen_rtx_error (current_cpu, "write from unimplemented special register");
4852 }
4853 {
4854   {
4855     BI opval = 0;
4856     CPU (h_xbit) = opval;
4857     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
4858   }
4859   {
4860     BI opval = 0;
4861     SET_H_INSN_PREFIXED_P (opval);
4862     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
4863   }
4864 }
4865 }
4866
4867   abuf->written = written;
4868 #undef FLD
4869 }
4870   NEXT (vpc);
4871
4872   CASE (sem, INSN_MOVE_SS_R) : /* move ${Ss},${Rd-sfield} */
4873 {
4874   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4875   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4876 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
4877   int UNUSED written = 0;
4878   IADDR UNUSED pc = abuf->addr;
4879   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4880
4881 {
4882   {
4883     SI opval = GET_H_SUPR (FLD (f_operand2));
4884     SET_H_GR (FLD (f_operand1), opval);
4885     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4886   }
4887 {
4888   {
4889     BI opval = 0;
4890     CPU (h_xbit) = opval;
4891     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
4892   }
4893   {
4894     BI opval = 0;
4895     SET_H_INSN_PREFIXED_P (opval);
4896     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
4897   }
4898 }
4899 }
4900
4901 #undef FLD
4902 }
4903   NEXT (vpc);
4904
4905   CASE (sem, INSN_MOVE_R_SS) : /* move ${Rs},${Sd} */
4906 {
4907   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4908   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4909 #define FLD(f) abuf->fields.sfmt_mcp.f
4910   int UNUSED written = 0;
4911   IADDR UNUSED pc = abuf->addr;
4912   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4913
4914 {
4915   {
4916     SI opval = GET_H_GR (FLD (f_operand1));
4917     SET_H_SUPR (FLD (f_operand2), opval);
4918     TRACE_RESULT (current_cpu, abuf, "supr", 'x', opval);
4919   }
4920 {
4921   {
4922     BI opval = 0;
4923     CPU (h_xbit) = opval;
4924     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
4925   }
4926   {
4927     BI opval = 0;
4928     SET_H_INSN_PREFIXED_P (opval);
4929     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
4930   }
4931 }
4932 }
4933
4934 #undef FLD
4935 }
4936   NEXT (vpc);
4937
4938   CASE (sem, INSN_MOVEM_R_M_V32) : /* movem ${Rs-dfield},[${Rd-sfield}${inc}] */
4939 {
4940   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4941   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4942 #define FLD(f) abuf->fields.sfmt_movem_r_m_v32.f
4943   int UNUSED written = 0;
4944   IADDR UNUSED pc = abuf->addr;
4945   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4946
4947 {
4948   SI tmp_addr;
4949   BI tmp_postinc;
4950   tmp_postinc = FLD (f_memmode);
4951 {
4952   SI tmp_dummy;
4953   tmp_dummy = GET_H_GR (FLD (f_operand2));
4954 }
4955   tmp_addr = GET_H_GR (FLD (f_operand1));
4956 {
4957 if (GESI (FLD (f_operand2), 0)) {
4958 {
4959   SI tmp_tmp;
4960   tmp_tmp = GET_H_GR (((UINT) 0));
4961   {
4962     SI opval = tmp_tmp;
4963     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4964     written |= (1 << 21);
4965     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4966   }
4967   tmp_addr = ADDSI (tmp_addr, 4);
4968 }
4969 }
4970 if (GESI (FLD (f_operand2), 1)) {
4971 {
4972   SI tmp_tmp;
4973   tmp_tmp = GET_H_GR (((UINT) 1));
4974   {
4975     SI opval = tmp_tmp;
4976     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4977     written |= (1 << 21);
4978     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4979   }
4980   tmp_addr = ADDSI (tmp_addr, 4);
4981 }
4982 }
4983 if (GESI (FLD (f_operand2), 2)) {
4984 {
4985   SI tmp_tmp;
4986   tmp_tmp = GET_H_GR (((UINT) 2));
4987   {
4988     SI opval = tmp_tmp;
4989     SETMEMSI (current_cpu, pc, tmp_addr, opval);
4990     written |= (1 << 21);
4991     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4992   }
4993   tmp_addr = ADDSI (tmp_addr, 4);
4994 }
4995 }
4996 if (GESI (FLD (f_operand2), 3)) {
4997 {
4998   SI tmp_tmp;
4999   tmp_tmp = GET_H_GR (((UINT) 3));
5000   {
5001     SI opval = tmp_tmp;
5002     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5003     written |= (1 << 21);
5004     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5005   }
5006   tmp_addr = ADDSI (tmp_addr, 4);
5007 }
5008 }
5009 if (GESI (FLD (f_operand2), 4)) {
5010 {
5011   SI tmp_tmp;
5012   tmp_tmp = GET_H_GR (((UINT) 4));
5013   {
5014     SI opval = tmp_tmp;
5015     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5016     written |= (1 << 21);
5017     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5018   }
5019   tmp_addr = ADDSI (tmp_addr, 4);
5020 }
5021 }
5022 if (GESI (FLD (f_operand2), 5)) {
5023 {
5024   SI tmp_tmp;
5025   tmp_tmp = GET_H_GR (((UINT) 5));
5026   {
5027     SI opval = tmp_tmp;
5028     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5029     written |= (1 << 21);
5030     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5031   }
5032   tmp_addr = ADDSI (tmp_addr, 4);
5033 }
5034 }
5035 if (GESI (FLD (f_operand2), 6)) {
5036 {
5037   SI tmp_tmp;
5038   tmp_tmp = GET_H_GR (((UINT) 6));
5039   {
5040     SI opval = tmp_tmp;
5041     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5042     written |= (1 << 21);
5043     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5044   }
5045   tmp_addr = ADDSI (tmp_addr, 4);
5046 }
5047 }
5048 if (GESI (FLD (f_operand2), 7)) {
5049 {
5050   SI tmp_tmp;
5051   tmp_tmp = GET_H_GR (((UINT) 7));
5052   {
5053     SI opval = tmp_tmp;
5054     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5055     written |= (1 << 21);
5056     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5057   }
5058   tmp_addr = ADDSI (tmp_addr, 4);
5059 }
5060 }
5061 if (GESI (FLD (f_operand2), 8)) {
5062 {
5063   SI tmp_tmp;
5064   tmp_tmp = GET_H_GR (((UINT) 8));
5065   {
5066     SI opval = tmp_tmp;
5067     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5068     written |= (1 << 21);
5069     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5070   }
5071   tmp_addr = ADDSI (tmp_addr, 4);
5072 }
5073 }
5074 if (GESI (FLD (f_operand2), 9)) {
5075 {
5076   SI tmp_tmp;
5077   tmp_tmp = GET_H_GR (((UINT) 9));
5078   {
5079     SI opval = tmp_tmp;
5080     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5081     written |= (1 << 21);
5082     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5083   }
5084   tmp_addr = ADDSI (tmp_addr, 4);
5085 }
5086 }
5087 if (GESI (FLD (f_operand2), 10)) {
5088 {
5089   SI tmp_tmp;
5090   tmp_tmp = GET_H_GR (((UINT) 10));
5091   {
5092     SI opval = tmp_tmp;
5093     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5094     written |= (1 << 21);
5095     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5096   }
5097   tmp_addr = ADDSI (tmp_addr, 4);
5098 }
5099 }
5100 if (GESI (FLD (f_operand2), 11)) {
5101 {
5102   SI tmp_tmp;
5103   tmp_tmp = GET_H_GR (((UINT) 11));
5104   {
5105     SI opval = tmp_tmp;
5106     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5107     written |= (1 << 21);
5108     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5109   }
5110   tmp_addr = ADDSI (tmp_addr, 4);
5111 }
5112 }
5113 if (GESI (FLD (f_operand2), 12)) {
5114 {
5115   SI tmp_tmp;
5116   tmp_tmp = GET_H_GR (((UINT) 12));
5117   {
5118     SI opval = tmp_tmp;
5119     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5120     written |= (1 << 21);
5121     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5122   }
5123   tmp_addr = ADDSI (tmp_addr, 4);
5124 }
5125 }
5126 if (GESI (FLD (f_operand2), 13)) {
5127 {
5128   SI tmp_tmp;
5129   tmp_tmp = GET_H_GR (((UINT) 13));
5130   {
5131     SI opval = tmp_tmp;
5132     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5133     written |= (1 << 21);
5134     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5135   }
5136   tmp_addr = ADDSI (tmp_addr, 4);
5137 }
5138 }
5139 if (GESI (FLD (f_operand2), 14)) {
5140 {
5141   SI tmp_tmp;
5142   tmp_tmp = GET_H_GR (((UINT) 14));
5143   {
5144     SI opval = tmp_tmp;
5145     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5146     written |= (1 << 21);
5147     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5148   }
5149   tmp_addr = ADDSI (tmp_addr, 4);
5150 }
5151 }
5152 if (GESI (FLD (f_operand2), 15)) {
5153 {
5154   SI tmp_tmp;
5155   tmp_tmp = GET_H_GR (((UINT) 15));
5156   {
5157     SI opval = tmp_tmp;
5158     SETMEMSI (current_cpu, pc, tmp_addr, opval);
5159     written |= (1 << 21);
5160     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5161   }
5162   tmp_addr = ADDSI (tmp_addr, 4);
5163 }
5164 }
5165 }
5166 if (NEBI (tmp_postinc, 0)) {
5167   {
5168     SI opval = tmp_addr;
5169     SET_H_GR (FLD (f_operand1), opval);
5170     written |= (1 << 20);
5171     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5172   }
5173 }
5174 {
5175   {
5176     BI opval = 0;
5177     CPU (h_xbit) = opval;
5178     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5179   }
5180   {
5181     BI opval = 0;
5182     SET_H_INSN_PREFIXED_P (opval);
5183     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5184   }
5185 }
5186 }
5187
5188   abuf->written = written;
5189 #undef FLD
5190 }
5191   NEXT (vpc);
5192
5193   CASE (sem, INSN_MOVEM_M_R_V32) : /* movem [${Rs}${inc}],${Rd} */
5194 {
5195   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5196   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5197 #define FLD(f) abuf->fields.sfmt_movem_m_r_v32.f
5198   int UNUSED written = 0;
5199   IADDR UNUSED pc = abuf->addr;
5200   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5201
5202 {
5203   SI tmp_addr;
5204   BI tmp_postinc;
5205   tmp_postinc = FLD (f_memmode);
5206   tmp_addr = GET_H_GR (FLD (f_operand1));
5207 {
5208   SI tmp_dummy;
5209   tmp_dummy = GET_H_GR (FLD (f_operand2));
5210 }
5211 {
5212 if (GESI (FLD (f_operand2), 0)) {
5213 {
5214   SI tmp_tmp;
5215   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5216   {
5217     SI opval = tmp_tmp;
5218     SET_H_GR (((UINT) 0), opval);
5219     written |= (1 << 6);
5220     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5221   }
5222   tmp_addr = ADDSI (tmp_addr, 4);
5223 }
5224 }
5225 if (GESI (FLD (f_operand2), 1)) {
5226 {
5227   SI tmp_tmp;
5228   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5229   {
5230     SI opval = tmp_tmp;
5231     SET_H_GR (((UINT) 1), opval);
5232     written |= (1 << 7);
5233     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5234   }
5235   tmp_addr = ADDSI (tmp_addr, 4);
5236 }
5237 }
5238 if (GESI (FLD (f_operand2), 2)) {
5239 {
5240   SI tmp_tmp;
5241   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5242   {
5243     SI opval = tmp_tmp;
5244     SET_H_GR (((UINT) 2), opval);
5245     written |= (1 << 14);
5246     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5247   }
5248   tmp_addr = ADDSI (tmp_addr, 4);
5249 }
5250 }
5251 if (GESI (FLD (f_operand2), 3)) {
5252 {
5253   SI tmp_tmp;
5254   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5255   {
5256     SI opval = tmp_tmp;
5257     SET_H_GR (((UINT) 3), opval);
5258     written |= (1 << 15);
5259     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5260   }
5261   tmp_addr = ADDSI (tmp_addr, 4);
5262 }
5263 }
5264 if (GESI (FLD (f_operand2), 4)) {
5265 {
5266   SI tmp_tmp;
5267   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5268   {
5269     SI opval = tmp_tmp;
5270     SET_H_GR (((UINT) 4), opval);
5271     written |= (1 << 16);
5272     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5273   }
5274   tmp_addr = ADDSI (tmp_addr, 4);
5275 }
5276 }
5277 if (GESI (FLD (f_operand2), 5)) {
5278 {
5279   SI tmp_tmp;
5280   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5281   {
5282     SI opval = tmp_tmp;
5283     SET_H_GR (((UINT) 5), opval);
5284     written |= (1 << 17);
5285     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5286   }
5287   tmp_addr = ADDSI (tmp_addr, 4);
5288 }
5289 }
5290 if (GESI (FLD (f_operand2), 6)) {
5291 {
5292   SI tmp_tmp;
5293   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5294   {
5295     SI opval = tmp_tmp;
5296     SET_H_GR (((UINT) 6), opval);
5297     written |= (1 << 18);
5298     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5299   }
5300   tmp_addr = ADDSI (tmp_addr, 4);
5301 }
5302 }
5303 if (GESI (FLD (f_operand2), 7)) {
5304 {
5305   SI tmp_tmp;
5306   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5307   {
5308     SI opval = tmp_tmp;
5309     SET_H_GR (((UINT) 7), opval);
5310     written |= (1 << 19);
5311     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5312   }
5313   tmp_addr = ADDSI (tmp_addr, 4);
5314 }
5315 }
5316 if (GESI (FLD (f_operand2), 8)) {
5317 {
5318   SI tmp_tmp;
5319   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5320   {
5321     SI opval = tmp_tmp;
5322     SET_H_GR (((UINT) 8), opval);
5323     written |= (1 << 20);
5324     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5325   }
5326   tmp_addr = ADDSI (tmp_addr, 4);
5327 }
5328 }
5329 if (GESI (FLD (f_operand2), 9)) {
5330 {
5331   SI tmp_tmp;
5332   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5333   {
5334     SI opval = tmp_tmp;
5335     SET_H_GR (((UINT) 9), opval);
5336     written |= (1 << 21);
5337     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5338   }
5339   tmp_addr = ADDSI (tmp_addr, 4);
5340 }
5341 }
5342 if (GESI (FLD (f_operand2), 10)) {
5343 {
5344   SI tmp_tmp;
5345   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5346   {
5347     SI opval = tmp_tmp;
5348     SET_H_GR (((UINT) 10), opval);
5349     written |= (1 << 8);
5350     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5351   }
5352   tmp_addr = ADDSI (tmp_addr, 4);
5353 }
5354 }
5355 if (GESI (FLD (f_operand2), 11)) {
5356 {
5357   SI tmp_tmp;
5358   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5359   {
5360     SI opval = tmp_tmp;
5361     SET_H_GR (((UINT) 11), opval);
5362     written |= (1 << 9);
5363     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5364   }
5365   tmp_addr = ADDSI (tmp_addr, 4);
5366 }
5367 }
5368 if (GESI (FLD (f_operand2), 12)) {
5369 {
5370   SI tmp_tmp;
5371   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5372   {
5373     SI opval = tmp_tmp;
5374     SET_H_GR (((UINT) 12), opval);
5375     written |= (1 << 10);
5376     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5377   }
5378   tmp_addr = ADDSI (tmp_addr, 4);
5379 }
5380 }
5381 if (GESI (FLD (f_operand2), 13)) {
5382 {
5383   SI tmp_tmp;
5384   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5385   {
5386     SI opval = tmp_tmp;
5387     SET_H_GR (((UINT) 13), opval);
5388     written |= (1 << 11);
5389     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5390   }
5391   tmp_addr = ADDSI (tmp_addr, 4);
5392 }
5393 }
5394 if (GESI (FLD (f_operand2), 14)) {
5395 {
5396   SI tmp_tmp;
5397   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5398   {
5399     SI opval = tmp_tmp;
5400     SET_H_GR (((UINT) 14), opval);
5401     written |= (1 << 12);
5402     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5403   }
5404   tmp_addr = ADDSI (tmp_addr, 4);
5405 }
5406 }
5407 if (GESI (FLD (f_operand2), 15)) {
5408 {
5409   SI tmp_tmp;
5410   tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
5411   {
5412     SI opval = tmp_tmp;
5413     SET_H_GR (((UINT) 15), opval);
5414     written |= (1 << 13);
5415     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5416   }
5417   tmp_addr = ADDSI (tmp_addr, 4);
5418 }
5419 }
5420 }
5421 if (NEBI (tmp_postinc, 0)) {
5422   {
5423     SI opval = tmp_addr;
5424     SET_H_GR (FLD (f_operand1), opval);
5425     written |= (1 << 5);
5426     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5427   }
5428 }
5429 {
5430   {
5431     BI opval = 0;
5432     CPU (h_xbit) = opval;
5433     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5434   }
5435   {
5436     BI opval = 0;
5437     SET_H_INSN_PREFIXED_P (opval);
5438     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5439   }
5440 }
5441 }
5442
5443   abuf->written = written;
5444 #undef FLD
5445 }
5446   NEXT (vpc);
5447
5448   CASE (sem, INSN_ADD_B_R) : /* add.b $Rs,$Rd */
5449 {
5450   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5451   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5452 #define FLD(f) abuf->fields.sfmt_addc_m.f
5453   int UNUSED written = 0;
5454   IADDR UNUSED pc = abuf->addr;
5455   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5456
5457 {
5458   QI tmp_tmpopd;
5459   QI tmp_tmpops;
5460   BI tmp_carry;
5461   QI tmp_newval;
5462   tmp_tmpops = GET_H_GR (FLD (f_operand1));
5463   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5464   tmp_carry = CPU (h_cbit);
5465   tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5466 {
5467   SI tmp_oldregval;
5468   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
5469   {
5470     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
5471     SET_H_GR (FLD (f_operand2), opval);
5472     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5473   }
5474 }
5475 {
5476   {
5477     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
5478     CPU (h_cbit) = opval;
5479     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5480   }
5481   {
5482     BI opval = LTQI (tmp_newval, 0);
5483     CPU (h_nbit) = opval;
5484     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5485   }
5486   {
5487     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5488     CPU (h_zbit) = opval;
5489     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5490   }
5491   {
5492     BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
5493     CPU (h_vbit) = opval;
5494     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5495   }
5496 {
5497   {
5498     BI opval = 0;
5499     CPU (h_xbit) = opval;
5500     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5501   }
5502   {
5503     BI opval = 0;
5504     SET_H_INSN_PREFIXED_P (opval);
5505     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5506   }
5507 }
5508 }
5509 }
5510
5511 #undef FLD
5512 }
5513   NEXT (vpc);
5514
5515   CASE (sem, INSN_ADD_W_R) : /* add.w $Rs,$Rd */
5516 {
5517   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5518   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5519 #define FLD(f) abuf->fields.sfmt_addc_m.f
5520   int UNUSED written = 0;
5521   IADDR UNUSED pc = abuf->addr;
5522   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5523
5524 {
5525   HI tmp_tmpopd;
5526   HI tmp_tmpops;
5527   BI tmp_carry;
5528   HI tmp_newval;
5529   tmp_tmpops = GET_H_GR (FLD (f_operand1));
5530   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5531   tmp_carry = CPU (h_cbit);
5532   tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5533 {
5534   SI tmp_oldregval;
5535   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
5536   {
5537     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
5538     SET_H_GR (FLD (f_operand2), opval);
5539     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5540   }
5541 }
5542 {
5543   {
5544     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
5545     CPU (h_cbit) = opval;
5546     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5547   }
5548   {
5549     BI opval = LTHI (tmp_newval, 0);
5550     CPU (h_nbit) = opval;
5551     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5552   }
5553   {
5554     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5555     CPU (h_zbit) = opval;
5556     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5557   }
5558   {
5559     BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
5560     CPU (h_vbit) = opval;
5561     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5562   }
5563 {
5564   {
5565     BI opval = 0;
5566     CPU (h_xbit) = opval;
5567     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5568   }
5569   {
5570     BI opval = 0;
5571     SET_H_INSN_PREFIXED_P (opval);
5572     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5573   }
5574 }
5575 }
5576 }
5577
5578 #undef FLD
5579 }
5580   NEXT (vpc);
5581
5582   CASE (sem, INSN_ADD_D_R) : /* add.d $Rs,$Rd */
5583 {
5584   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5585   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5586 #define FLD(f) abuf->fields.sfmt_addc_m.f
5587   int UNUSED written = 0;
5588   IADDR UNUSED pc = abuf->addr;
5589   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5590
5591 {
5592   SI tmp_tmpopd;
5593   SI tmp_tmpops;
5594   BI tmp_carry;
5595   SI tmp_newval;
5596   tmp_tmpops = GET_H_GR (FLD (f_operand1));
5597   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5598   tmp_carry = CPU (h_cbit);
5599   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5600   {
5601     SI opval = tmp_newval;
5602     SET_H_GR (FLD (f_operand2), opval);
5603     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5604   }
5605 {
5606   {
5607     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
5608     CPU (h_cbit) = opval;
5609     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5610   }
5611   {
5612     BI opval = LTSI (tmp_newval, 0);
5613     CPU (h_nbit) = opval;
5614     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5615   }
5616   {
5617     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5618     CPU (h_zbit) = opval;
5619     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5620   }
5621   {
5622     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
5623     CPU (h_vbit) = opval;
5624     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5625   }
5626 {
5627   {
5628     BI opval = 0;
5629     CPU (h_xbit) = opval;
5630     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5631   }
5632   {
5633     BI opval = 0;
5634     SET_H_INSN_PREFIXED_P (opval);
5635     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5636   }
5637 }
5638 }
5639 }
5640
5641 #undef FLD
5642 }
5643   NEXT (vpc);
5644
5645   CASE (sem, INSN_ADD_M_B_M) : /* add-m.b [${Rs}${inc}],${Rd} */
5646 {
5647   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5648   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5649 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
5650   int UNUSED written = 0;
5651   IADDR UNUSED pc = abuf->addr;
5652   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5653
5654 {
5655   QI tmp_tmpopd;
5656   QI tmp_tmpops;
5657   BI tmp_carry;
5658   QI tmp_newval;
5659   tmp_tmpops = ({   SI tmp_addr;
5660   QI tmp_tmp_mem;
5661   BI tmp_postinc;
5662   tmp_postinc = FLD (f_memmode);
5663 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
5664 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
5665 ; if (NEBI (tmp_postinc, 0)) {
5666 {
5667 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
5668   tmp_addr = ADDSI (tmp_addr, 1);
5669 }
5670   {
5671     SI opval = tmp_addr;
5672     SET_H_GR (FLD (f_operand1), opval);
5673     written |= (1 << 12);
5674     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5675   }
5676 }
5677 }
5678 ; tmp_tmp_mem; });
5679   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5680   tmp_carry = CPU (h_cbit);
5681   tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5682 {
5683   SI tmp_oldregval;
5684   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
5685   {
5686     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
5687     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
5688     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5689   }
5690 }
5691 {
5692   {
5693     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
5694     CPU (h_cbit) = opval;
5695     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5696   }
5697   {
5698     BI opval = LTQI (tmp_newval, 0);
5699     CPU (h_nbit) = opval;
5700     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5701   }
5702   {
5703     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5704     CPU (h_zbit) = opval;
5705     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5706   }
5707   {
5708     BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
5709     CPU (h_vbit) = opval;
5710     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5711   }
5712 {
5713   {
5714     BI opval = 0;
5715     CPU (h_xbit) = opval;
5716     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5717   }
5718   {
5719     BI opval = 0;
5720     SET_H_INSN_PREFIXED_P (opval);
5721     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5722   }
5723 }
5724 }
5725 }
5726
5727   abuf->written = written;
5728 #undef FLD
5729 }
5730   NEXT (vpc);
5731
5732   CASE (sem, INSN_ADD_M_W_M) : /* add-m.w [${Rs}${inc}],${Rd} */
5733 {
5734   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5735   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5736 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
5737   int UNUSED written = 0;
5738   IADDR UNUSED pc = abuf->addr;
5739   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5740
5741 {
5742   HI tmp_tmpopd;
5743   HI tmp_tmpops;
5744   BI tmp_carry;
5745   HI tmp_newval;
5746   tmp_tmpops = ({   SI tmp_addr;
5747   HI tmp_tmp_mem;
5748   BI tmp_postinc;
5749   tmp_postinc = FLD (f_memmode);
5750 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
5751 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
5752 ; if (NEBI (tmp_postinc, 0)) {
5753 {
5754 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
5755   tmp_addr = ADDSI (tmp_addr, 2);
5756 }
5757   {
5758     SI opval = tmp_addr;
5759     SET_H_GR (FLD (f_operand1), opval);
5760     written |= (1 << 12);
5761     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5762   }
5763 }
5764 }
5765 ; tmp_tmp_mem; });
5766   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5767   tmp_carry = CPU (h_cbit);
5768   tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5769 {
5770   SI tmp_oldregval;
5771   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
5772   {
5773     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
5774     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
5775     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5776   }
5777 }
5778 {
5779   {
5780     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
5781     CPU (h_cbit) = opval;
5782     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5783   }
5784   {
5785     BI opval = LTHI (tmp_newval, 0);
5786     CPU (h_nbit) = opval;
5787     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5788   }
5789   {
5790     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5791     CPU (h_zbit) = opval;
5792     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5793   }
5794   {
5795     BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
5796     CPU (h_vbit) = opval;
5797     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5798   }
5799 {
5800   {
5801     BI opval = 0;
5802     CPU (h_xbit) = opval;
5803     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5804   }
5805   {
5806     BI opval = 0;
5807     SET_H_INSN_PREFIXED_P (opval);
5808     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5809   }
5810 }
5811 }
5812 }
5813
5814   abuf->written = written;
5815 #undef FLD
5816 }
5817   NEXT (vpc);
5818
5819   CASE (sem, INSN_ADD_M_D_M) : /* add-m.d [${Rs}${inc}],${Rd} */
5820 {
5821   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5822   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5823 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
5824   int UNUSED written = 0;
5825   IADDR UNUSED pc = abuf->addr;
5826   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5827
5828 {
5829   SI tmp_tmpopd;
5830   SI tmp_tmpops;
5831   BI tmp_carry;
5832   SI tmp_newval;
5833   tmp_tmpops = ({   SI tmp_addr;
5834   SI tmp_tmp_mem;
5835   BI tmp_postinc;
5836   tmp_postinc = FLD (f_memmode);
5837 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
5838 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
5839 ; if (NEBI (tmp_postinc, 0)) {
5840 {
5841 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
5842   tmp_addr = ADDSI (tmp_addr, 4);
5843 }
5844   {
5845     SI opval = tmp_addr;
5846     SET_H_GR (FLD (f_operand1), opval);
5847     written |= (1 << 11);
5848     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5849   }
5850 }
5851 }
5852 ; tmp_tmp_mem; });
5853   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5854   tmp_carry = CPU (h_cbit);
5855   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5856   {
5857     SI opval = tmp_newval;
5858     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
5859     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5860   }
5861 {
5862   {
5863     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
5864     CPU (h_cbit) = opval;
5865     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5866   }
5867   {
5868     BI opval = LTSI (tmp_newval, 0);
5869     CPU (h_nbit) = opval;
5870     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5871   }
5872   {
5873     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5874     CPU (h_zbit) = opval;
5875     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5876   }
5877   {
5878     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
5879     CPU (h_vbit) = opval;
5880     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5881   }
5882 {
5883   {
5884     BI opval = 0;
5885     CPU (h_xbit) = opval;
5886     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5887   }
5888   {
5889     BI opval = 0;
5890     SET_H_INSN_PREFIXED_P (opval);
5891     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5892   }
5893 }
5894 }
5895 }
5896
5897   abuf->written = written;
5898 #undef FLD
5899 }
5900   NEXT (vpc);
5901
5902   CASE (sem, INSN_ADDCBR) : /* add.b ${sconst8}],${Rd} */
5903 {
5904   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5905   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5906 #define FLD(f) abuf->fields.sfmt_addcbr.f
5907   int UNUSED written = 0;
5908   IADDR UNUSED pc = abuf->addr;
5909   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
5910
5911 {
5912   QI tmp_tmpopd;
5913   QI tmp_tmpops;
5914   BI tmp_carry;
5915   QI tmp_newval;
5916   tmp_tmpops = FLD (f_indir_pc__byte);
5917   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5918   tmp_carry = CPU (h_cbit);
5919   tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5920 {
5921   SI tmp_oldregval;
5922   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
5923   {
5924     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
5925     SET_H_GR (FLD (f_operand2), opval);
5926     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5927   }
5928 }
5929 {
5930   {
5931     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
5932     CPU (h_cbit) = opval;
5933     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
5934   }
5935   {
5936     BI opval = LTQI (tmp_newval, 0);
5937     CPU (h_nbit) = opval;
5938     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
5939   }
5940   {
5941     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
5942     CPU (h_zbit) = opval;
5943     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
5944   }
5945   {
5946     BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
5947     CPU (h_vbit) = opval;
5948     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
5949   }
5950 {
5951   {
5952     BI opval = 0;
5953     CPU (h_xbit) = opval;
5954     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
5955   }
5956   {
5957     BI opval = 0;
5958     SET_H_INSN_PREFIXED_P (opval);
5959     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
5960   }
5961 }
5962 }
5963 }
5964
5965 #undef FLD
5966 }
5967   NEXT (vpc);
5968
5969   CASE (sem, INSN_ADDCWR) : /* add.w ${sconst16}],${Rd} */
5970 {
5971   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5972   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5973 #define FLD(f) abuf->fields.sfmt_addcwr.f
5974   int UNUSED written = 0;
5975   IADDR UNUSED pc = abuf->addr;
5976   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
5977
5978 {
5979   HI tmp_tmpopd;
5980   HI tmp_tmpops;
5981   BI tmp_carry;
5982   HI tmp_newval;
5983   tmp_tmpops = FLD (f_indir_pc__word);
5984   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
5985   tmp_carry = CPU (h_cbit);
5986   tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
5987 {
5988   SI tmp_oldregval;
5989   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
5990   {
5991     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
5992     SET_H_GR (FLD (f_operand2), opval);
5993     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5994   }
5995 }
5996 {
5997   {
5998     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
5999     CPU (h_cbit) = opval;
6000     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6001   }
6002   {
6003     BI opval = LTHI (tmp_newval, 0);
6004     CPU (h_nbit) = opval;
6005     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6006   }
6007   {
6008     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6009     CPU (h_zbit) = opval;
6010     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6011   }
6012   {
6013     BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
6014     CPU (h_vbit) = opval;
6015     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6016   }
6017 {
6018   {
6019     BI opval = 0;
6020     CPU (h_xbit) = opval;
6021     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6022   }
6023   {
6024     BI opval = 0;
6025     SET_H_INSN_PREFIXED_P (opval);
6026     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6027   }
6028 }
6029 }
6030 }
6031
6032 #undef FLD
6033 }
6034   NEXT (vpc);
6035
6036   CASE (sem, INSN_ADDCDR) : /* add.d ${const32}],${Rd} */
6037 {
6038   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6039   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6040 #define FLD(f) abuf->fields.sfmt_addcdr.f
6041   int UNUSED written = 0;
6042   IADDR UNUSED pc = abuf->addr;
6043   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
6044
6045 {
6046   SI tmp_tmpopd;
6047   SI tmp_tmpops;
6048   BI tmp_carry;
6049   SI tmp_newval;
6050   tmp_tmpops = FLD (f_indir_pc__dword);
6051   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6052   tmp_carry = CPU (h_cbit);
6053   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6054   {
6055     SI opval = tmp_newval;
6056     SET_H_GR (FLD (f_operand2), opval);
6057     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6058   }
6059 {
6060   {
6061     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6062     CPU (h_cbit) = opval;
6063     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6064   }
6065   {
6066     BI opval = LTSI (tmp_newval, 0);
6067     CPU (h_nbit) = opval;
6068     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6069   }
6070   {
6071     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6072     CPU (h_zbit) = opval;
6073     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6074   }
6075   {
6076     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6077     CPU (h_vbit) = opval;
6078     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6079   }
6080 {
6081   {
6082     BI opval = 0;
6083     CPU (h_xbit) = opval;
6084     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6085   }
6086   {
6087     BI opval = 0;
6088     SET_H_INSN_PREFIXED_P (opval);
6089     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6090   }
6091 }
6092 }
6093 }
6094
6095 #undef FLD
6096 }
6097   NEXT (vpc);
6098
6099   CASE (sem, INSN_ADDS_B_R) : /* adds.b $Rs,$Rd */
6100 {
6101   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6102   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6103 #define FLD(f) abuf->fields.sfmt_addc_m.f
6104   int UNUSED written = 0;
6105   IADDR UNUSED pc = abuf->addr;
6106   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6107
6108 {
6109   SI tmp_tmpopd;
6110   SI tmp_tmpops;
6111   BI tmp_carry;
6112   SI tmp_newval;
6113   tmp_tmpops = EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
6114   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6115   tmp_carry = CPU (h_cbit);
6116   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6117   {
6118     SI opval = tmp_newval;
6119     SET_H_GR (FLD (f_operand2), opval);
6120     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6121   }
6122 {
6123   {
6124     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6125     CPU (h_cbit) = opval;
6126     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6127   }
6128   {
6129     BI opval = LTSI (tmp_newval, 0);
6130     CPU (h_nbit) = opval;
6131     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6132   }
6133   {
6134     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6135     CPU (h_zbit) = opval;
6136     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6137   }
6138   {
6139     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6140     CPU (h_vbit) = opval;
6141     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6142   }
6143 {
6144   {
6145     BI opval = 0;
6146     CPU (h_xbit) = opval;
6147     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6148   }
6149   {
6150     BI opval = 0;
6151     SET_H_INSN_PREFIXED_P (opval);
6152     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6153   }
6154 }
6155 }
6156 }
6157
6158 #undef FLD
6159 }
6160   NEXT (vpc);
6161
6162   CASE (sem, INSN_ADDS_W_R) : /* adds.w $Rs,$Rd */
6163 {
6164   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6165   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6166 #define FLD(f) abuf->fields.sfmt_addc_m.f
6167   int UNUSED written = 0;
6168   IADDR UNUSED pc = abuf->addr;
6169   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6170
6171 {
6172   SI tmp_tmpopd;
6173   SI tmp_tmpops;
6174   BI tmp_carry;
6175   SI tmp_newval;
6176   tmp_tmpops = EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
6177   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6178   tmp_carry = CPU (h_cbit);
6179   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6180   {
6181     SI opval = tmp_newval;
6182     SET_H_GR (FLD (f_operand2), opval);
6183     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6184   }
6185 {
6186   {
6187     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6188     CPU (h_cbit) = opval;
6189     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6190   }
6191   {
6192     BI opval = LTSI (tmp_newval, 0);
6193     CPU (h_nbit) = opval;
6194     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6195   }
6196   {
6197     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6198     CPU (h_zbit) = opval;
6199     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6200   }
6201   {
6202     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6203     CPU (h_vbit) = opval;
6204     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6205   }
6206 {
6207   {
6208     BI opval = 0;
6209     CPU (h_xbit) = opval;
6210     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6211   }
6212   {
6213     BI opval = 0;
6214     SET_H_INSN_PREFIXED_P (opval);
6215     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6216   }
6217 }
6218 }
6219 }
6220
6221 #undef FLD
6222 }
6223   NEXT (vpc);
6224
6225   CASE (sem, INSN_ADDS_M_B_M) : /* adds-m.b [${Rs}${inc}],$Rd */
6226 {
6227   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6228   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6229 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6230   int UNUSED written = 0;
6231   IADDR UNUSED pc = abuf->addr;
6232   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6233
6234 {
6235   SI tmp_tmpopd;
6236   SI tmp_tmpops;
6237   BI tmp_carry;
6238   SI tmp_newval;
6239   tmp_tmpops = EXTQISI (({   SI tmp_addr;
6240   QI tmp_tmp_mem;
6241   BI tmp_postinc;
6242   tmp_postinc = FLD (f_memmode);
6243 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
6244 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
6245 ; if (NEBI (tmp_postinc, 0)) {
6246 {
6247 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6248   tmp_addr = ADDSI (tmp_addr, 1);
6249 }
6250   {
6251     SI opval = tmp_addr;
6252     SET_H_GR (FLD (f_operand1), opval);
6253     written |= (1 << 11);
6254     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6255   }
6256 }
6257 }
6258 ; tmp_tmp_mem; }));
6259   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6260   tmp_carry = CPU (h_cbit);
6261   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6262   {
6263     SI opval = tmp_newval;
6264     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6265     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6266   }
6267 {
6268   {
6269     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6270     CPU (h_cbit) = opval;
6271     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6272   }
6273   {
6274     BI opval = LTSI (tmp_newval, 0);
6275     CPU (h_nbit) = opval;
6276     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6277   }
6278   {
6279     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6280     CPU (h_zbit) = opval;
6281     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6282   }
6283   {
6284     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6285     CPU (h_vbit) = opval;
6286     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6287   }
6288 {
6289   {
6290     BI opval = 0;
6291     CPU (h_xbit) = opval;
6292     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6293   }
6294   {
6295     BI opval = 0;
6296     SET_H_INSN_PREFIXED_P (opval);
6297     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6298   }
6299 }
6300 }
6301 }
6302
6303   abuf->written = written;
6304 #undef FLD
6305 }
6306   NEXT (vpc);
6307
6308   CASE (sem, INSN_ADDS_M_W_M) : /* adds-m.w [${Rs}${inc}],$Rd */
6309 {
6310   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6311   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6312 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6313   int UNUSED written = 0;
6314   IADDR UNUSED pc = abuf->addr;
6315   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6316
6317 {
6318   SI tmp_tmpopd;
6319   SI tmp_tmpops;
6320   BI tmp_carry;
6321   SI tmp_newval;
6322   tmp_tmpops = EXTHISI (({   SI tmp_addr;
6323   HI tmp_tmp_mem;
6324   BI tmp_postinc;
6325   tmp_postinc = FLD (f_memmode);
6326 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
6327 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
6328 ; if (NEBI (tmp_postinc, 0)) {
6329 {
6330 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6331   tmp_addr = ADDSI (tmp_addr, 2);
6332 }
6333   {
6334     SI opval = tmp_addr;
6335     SET_H_GR (FLD (f_operand1), opval);
6336     written |= (1 << 11);
6337     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6338   }
6339 }
6340 }
6341 ; tmp_tmp_mem; }));
6342   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6343   tmp_carry = CPU (h_cbit);
6344   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6345   {
6346     SI opval = tmp_newval;
6347     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6348     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6349   }
6350 {
6351   {
6352     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6353     CPU (h_cbit) = opval;
6354     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6355   }
6356   {
6357     BI opval = LTSI (tmp_newval, 0);
6358     CPU (h_nbit) = opval;
6359     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6360   }
6361   {
6362     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6363     CPU (h_zbit) = opval;
6364     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6365   }
6366   {
6367     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6368     CPU (h_vbit) = opval;
6369     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6370   }
6371 {
6372   {
6373     BI opval = 0;
6374     CPU (h_xbit) = opval;
6375     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6376   }
6377   {
6378     BI opval = 0;
6379     SET_H_INSN_PREFIXED_P (opval);
6380     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6381   }
6382 }
6383 }
6384 }
6385
6386   abuf->written = written;
6387 #undef FLD
6388 }
6389   NEXT (vpc);
6390
6391   CASE (sem, INSN_ADDSCBR) : /* [${Rs}${inc}],$Rd */
6392 {
6393   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6394   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6395 #define FLD(f) abuf->fields.sfmt_addcbr.f
6396   int UNUSED written = 0;
6397   IADDR UNUSED pc = abuf->addr;
6398   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6399
6400 {
6401   SI tmp_tmpopd;
6402   SI tmp_tmpops;
6403   BI tmp_carry;
6404   SI tmp_newval;
6405   tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
6406   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6407   tmp_carry = CPU (h_cbit);
6408   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6409   {
6410     SI opval = tmp_newval;
6411     SET_H_GR (FLD (f_operand2), opval);
6412     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6413   }
6414 {
6415   {
6416     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6417     CPU (h_cbit) = opval;
6418     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6419   }
6420   {
6421     BI opval = LTSI (tmp_newval, 0);
6422     CPU (h_nbit) = opval;
6423     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6424   }
6425   {
6426     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6427     CPU (h_zbit) = opval;
6428     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6429   }
6430   {
6431     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6432     CPU (h_vbit) = opval;
6433     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6434   }
6435 {
6436   {
6437     BI opval = 0;
6438     CPU (h_xbit) = opval;
6439     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6440   }
6441   {
6442     BI opval = 0;
6443     SET_H_INSN_PREFIXED_P (opval);
6444     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6445   }
6446 }
6447 }
6448 }
6449
6450 #undef FLD
6451 }
6452   NEXT (vpc);
6453
6454   CASE (sem, INSN_ADDSCWR) : /* [${Rs}${inc}],$Rd */
6455 {
6456   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6457   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6458 #define FLD(f) abuf->fields.sfmt_addcwr.f
6459   int UNUSED written = 0;
6460   IADDR UNUSED pc = abuf->addr;
6461   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6462
6463 {
6464   SI tmp_tmpopd;
6465   SI tmp_tmpops;
6466   BI tmp_carry;
6467   SI tmp_newval;
6468   tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
6469   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6470   tmp_carry = CPU (h_cbit);
6471   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6472   {
6473     SI opval = tmp_newval;
6474     SET_H_GR (FLD (f_operand2), opval);
6475     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6476   }
6477 {
6478   {
6479     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6480     CPU (h_cbit) = opval;
6481     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6482   }
6483   {
6484     BI opval = LTSI (tmp_newval, 0);
6485     CPU (h_nbit) = opval;
6486     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6487   }
6488   {
6489     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6490     CPU (h_zbit) = opval;
6491     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6492   }
6493   {
6494     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6495     CPU (h_vbit) = opval;
6496     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6497   }
6498 {
6499   {
6500     BI opval = 0;
6501     CPU (h_xbit) = opval;
6502     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6503   }
6504   {
6505     BI opval = 0;
6506     SET_H_INSN_PREFIXED_P (opval);
6507     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6508   }
6509 }
6510 }
6511 }
6512
6513 #undef FLD
6514 }
6515   NEXT (vpc);
6516
6517   CASE (sem, INSN_ADDU_B_R) : /* addu.b $Rs,$Rd */
6518 {
6519   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6520   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6521 #define FLD(f) abuf->fields.sfmt_addc_m.f
6522   int UNUSED written = 0;
6523   IADDR UNUSED pc = abuf->addr;
6524   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6525
6526 {
6527   SI tmp_tmpopd;
6528   SI tmp_tmpops;
6529   BI tmp_carry;
6530   SI tmp_newval;
6531   tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
6532   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6533   tmp_carry = CPU (h_cbit);
6534   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6535   {
6536     SI opval = tmp_newval;
6537     SET_H_GR (FLD (f_operand2), opval);
6538     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6539   }
6540 {
6541   {
6542     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6543     CPU (h_cbit) = opval;
6544     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6545   }
6546   {
6547     BI opval = LTSI (tmp_newval, 0);
6548     CPU (h_nbit) = opval;
6549     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6550   }
6551   {
6552     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6553     CPU (h_zbit) = opval;
6554     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6555   }
6556   {
6557     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6558     CPU (h_vbit) = opval;
6559     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6560   }
6561 {
6562   {
6563     BI opval = 0;
6564     CPU (h_xbit) = opval;
6565     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6566   }
6567   {
6568     BI opval = 0;
6569     SET_H_INSN_PREFIXED_P (opval);
6570     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6571   }
6572 }
6573 }
6574 }
6575
6576 #undef FLD
6577 }
6578   NEXT (vpc);
6579
6580   CASE (sem, INSN_ADDU_W_R) : /* addu.w $Rs,$Rd */
6581 {
6582   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6583   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6584 #define FLD(f) abuf->fields.sfmt_addc_m.f
6585   int UNUSED written = 0;
6586   IADDR UNUSED pc = abuf->addr;
6587   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6588
6589 {
6590   SI tmp_tmpopd;
6591   SI tmp_tmpops;
6592   BI tmp_carry;
6593   SI tmp_newval;
6594   tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
6595   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6596   tmp_carry = CPU (h_cbit);
6597   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6598   {
6599     SI opval = tmp_newval;
6600     SET_H_GR (FLD (f_operand2), opval);
6601     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6602   }
6603 {
6604   {
6605     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6606     CPU (h_cbit) = opval;
6607     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6608   }
6609   {
6610     BI opval = LTSI (tmp_newval, 0);
6611     CPU (h_nbit) = opval;
6612     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6613   }
6614   {
6615     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6616     CPU (h_zbit) = opval;
6617     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6618   }
6619   {
6620     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6621     CPU (h_vbit) = opval;
6622     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6623   }
6624 {
6625   {
6626     BI opval = 0;
6627     CPU (h_xbit) = opval;
6628     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6629   }
6630   {
6631     BI opval = 0;
6632     SET_H_INSN_PREFIXED_P (opval);
6633     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6634   }
6635 }
6636 }
6637 }
6638
6639 #undef FLD
6640 }
6641   NEXT (vpc);
6642
6643   CASE (sem, INSN_ADDU_M_B_M) : /* addu-m.b [${Rs}${inc}],$Rd */
6644 {
6645   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6646   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6647 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6648   int UNUSED written = 0;
6649   IADDR UNUSED pc = abuf->addr;
6650   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6651
6652 {
6653   SI tmp_tmpopd;
6654   SI tmp_tmpops;
6655   BI tmp_carry;
6656   SI tmp_newval;
6657   tmp_tmpops = ZEXTQISI (({   SI tmp_addr;
6658   QI tmp_tmp_mem;
6659   BI tmp_postinc;
6660   tmp_postinc = FLD (f_memmode);
6661 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
6662 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
6663 ; if (NEBI (tmp_postinc, 0)) {
6664 {
6665 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6666   tmp_addr = ADDSI (tmp_addr, 1);
6667 }
6668   {
6669     SI opval = tmp_addr;
6670     SET_H_GR (FLD (f_operand1), opval);
6671     written |= (1 << 11);
6672     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6673   }
6674 }
6675 }
6676 ; tmp_tmp_mem; }));
6677   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6678   tmp_carry = CPU (h_cbit);
6679   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6680   {
6681     SI opval = tmp_newval;
6682     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6683     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6684   }
6685 {
6686   {
6687     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6688     CPU (h_cbit) = opval;
6689     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6690   }
6691   {
6692     BI opval = LTSI (tmp_newval, 0);
6693     CPU (h_nbit) = opval;
6694     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6695   }
6696   {
6697     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6698     CPU (h_zbit) = opval;
6699     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6700   }
6701   {
6702     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6703     CPU (h_vbit) = opval;
6704     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6705   }
6706 {
6707   {
6708     BI opval = 0;
6709     CPU (h_xbit) = opval;
6710     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6711   }
6712   {
6713     BI opval = 0;
6714     SET_H_INSN_PREFIXED_P (opval);
6715     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6716   }
6717 }
6718 }
6719 }
6720
6721   abuf->written = written;
6722 #undef FLD
6723 }
6724   NEXT (vpc);
6725
6726   CASE (sem, INSN_ADDU_M_W_M) : /* addu-m.w [${Rs}${inc}],$Rd */
6727 {
6728   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6729   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6730 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
6731   int UNUSED written = 0;
6732   IADDR UNUSED pc = abuf->addr;
6733   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6734
6735 {
6736   SI tmp_tmpopd;
6737   SI tmp_tmpops;
6738   BI tmp_carry;
6739   SI tmp_newval;
6740   tmp_tmpops = ZEXTHISI (({   SI tmp_addr;
6741   HI tmp_tmp_mem;
6742   BI tmp_postinc;
6743   tmp_postinc = FLD (f_memmode);
6744 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
6745 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
6746 ; if (NEBI (tmp_postinc, 0)) {
6747 {
6748 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
6749   tmp_addr = ADDSI (tmp_addr, 2);
6750 }
6751   {
6752     SI opval = tmp_addr;
6753     SET_H_GR (FLD (f_operand1), opval);
6754     written |= (1 << 11);
6755     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6756   }
6757 }
6758 }
6759 ; tmp_tmp_mem; }));
6760   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6761   tmp_carry = CPU (h_cbit);
6762   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6763   {
6764     SI opval = tmp_newval;
6765     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
6766     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6767   }
6768 {
6769   {
6770     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6771     CPU (h_cbit) = opval;
6772     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6773   }
6774   {
6775     BI opval = LTSI (tmp_newval, 0);
6776     CPU (h_nbit) = opval;
6777     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6778   }
6779   {
6780     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6781     CPU (h_zbit) = opval;
6782     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6783   }
6784   {
6785     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6786     CPU (h_vbit) = opval;
6787     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6788   }
6789 {
6790   {
6791     BI opval = 0;
6792     CPU (h_xbit) = opval;
6793     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6794   }
6795   {
6796     BI opval = 0;
6797     SET_H_INSN_PREFIXED_P (opval);
6798     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6799   }
6800 }
6801 }
6802 }
6803
6804   abuf->written = written;
6805 #undef FLD
6806 }
6807   NEXT (vpc);
6808
6809   CASE (sem, INSN_ADDUCBR) : /* [${Rs}${inc}],$Rd */
6810 {
6811   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6812   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6813 #define FLD(f) abuf->fields.sfmt_addcbr.f
6814   int UNUSED written = 0;
6815   IADDR UNUSED pc = abuf->addr;
6816   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6817
6818 {
6819   SI tmp_tmpopd;
6820   SI tmp_tmpops;
6821   BI tmp_carry;
6822   SI tmp_newval;
6823   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
6824   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6825   tmp_carry = CPU (h_cbit);
6826   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6827   {
6828     SI opval = tmp_newval;
6829     SET_H_GR (FLD (f_operand2), opval);
6830     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6831   }
6832 {
6833   {
6834     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6835     CPU (h_cbit) = opval;
6836     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6837   }
6838   {
6839     BI opval = LTSI (tmp_newval, 0);
6840     CPU (h_nbit) = opval;
6841     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6842   }
6843   {
6844     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6845     CPU (h_zbit) = opval;
6846     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6847   }
6848   {
6849     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6850     CPU (h_vbit) = opval;
6851     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6852   }
6853 {
6854   {
6855     BI opval = 0;
6856     CPU (h_xbit) = opval;
6857     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6858   }
6859   {
6860     BI opval = 0;
6861     SET_H_INSN_PREFIXED_P (opval);
6862     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6863   }
6864 }
6865 }
6866 }
6867
6868 #undef FLD
6869 }
6870   NEXT (vpc);
6871
6872   CASE (sem, INSN_ADDUCWR) : /* [${Rs}${inc}],$Rd */
6873 {
6874   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6875   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6876 #define FLD(f) abuf->fields.sfmt_addcwr.f
6877   int UNUSED written = 0;
6878   IADDR UNUSED pc = abuf->addr;
6879   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
6880
6881 {
6882   SI tmp_tmpopd;
6883   SI tmp_tmpops;
6884   BI tmp_carry;
6885   SI tmp_newval;
6886   tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
6887   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6888   tmp_carry = CPU (h_cbit);
6889   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6890   {
6891     SI opval = tmp_newval;
6892     SET_H_GR (FLD (f_operand2), opval);
6893     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6894   }
6895 {
6896   {
6897     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
6898     CPU (h_cbit) = opval;
6899     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6900   }
6901   {
6902     BI opval = LTSI (tmp_newval, 0);
6903     CPU (h_nbit) = opval;
6904     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6905   }
6906   {
6907     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6908     CPU (h_zbit) = opval;
6909     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6910   }
6911   {
6912     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
6913     CPU (h_vbit) = opval;
6914     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6915   }
6916 {
6917   {
6918     BI opval = 0;
6919     CPU (h_xbit) = opval;
6920     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6921   }
6922   {
6923     BI opval = 0;
6924     SET_H_INSN_PREFIXED_P (opval);
6925     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6926   }
6927 }
6928 }
6929 }
6930
6931 #undef FLD
6932 }
6933   NEXT (vpc);
6934
6935   CASE (sem, INSN_SUB_B_R) : /* sub.b $Rs,$Rd */
6936 {
6937   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
6938   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
6939 #define FLD(f) abuf->fields.sfmt_addc_m.f
6940   int UNUSED written = 0;
6941   IADDR UNUSED pc = abuf->addr;
6942   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
6943
6944 {
6945   QI tmp_tmpopd;
6946   QI tmp_tmpops;
6947   BI tmp_carry;
6948   QI tmp_newval;
6949   tmp_tmpops = GET_H_GR (FLD (f_operand1));
6950   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
6951   tmp_carry = CPU (h_cbit);
6952   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
6953 {
6954   SI tmp_oldregval;
6955   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
6956   {
6957     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
6958     SET_H_GR (FLD (f_operand2), opval);
6959     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
6960   }
6961 }
6962 {
6963   {
6964     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
6965     CPU (h_cbit) = opval;
6966     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
6967   }
6968   {
6969     BI opval = LTQI (tmp_newval, 0);
6970     CPU (h_nbit) = opval;
6971     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
6972   }
6973   {
6974     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
6975     CPU (h_zbit) = opval;
6976     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
6977   }
6978   {
6979     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
6980     CPU (h_vbit) = opval;
6981     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
6982   }
6983 {
6984   {
6985     BI opval = 0;
6986     CPU (h_xbit) = opval;
6987     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
6988   }
6989   {
6990     BI opval = 0;
6991     SET_H_INSN_PREFIXED_P (opval);
6992     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
6993   }
6994 }
6995 }
6996 }
6997
6998 #undef FLD
6999 }
7000   NEXT (vpc);
7001
7002   CASE (sem, INSN_SUB_W_R) : /* sub.w $Rs,$Rd */
7003 {
7004   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7005   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7006 #define FLD(f) abuf->fields.sfmt_addc_m.f
7007   int UNUSED written = 0;
7008   IADDR UNUSED pc = abuf->addr;
7009   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7010
7011 {
7012   HI tmp_tmpopd;
7013   HI tmp_tmpops;
7014   BI tmp_carry;
7015   HI tmp_newval;
7016   tmp_tmpops = GET_H_GR (FLD (f_operand1));
7017   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7018   tmp_carry = CPU (h_cbit);
7019   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7020 {
7021   SI tmp_oldregval;
7022   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
7023   {
7024     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
7025     SET_H_GR (FLD (f_operand2), opval);
7026     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7027   }
7028 }
7029 {
7030   {
7031     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
7032     CPU (h_cbit) = opval;
7033     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7034   }
7035   {
7036     BI opval = LTHI (tmp_newval, 0);
7037     CPU (h_nbit) = opval;
7038     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7039   }
7040   {
7041     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7042     CPU (h_zbit) = opval;
7043     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7044   }
7045   {
7046     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
7047     CPU (h_vbit) = opval;
7048     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7049   }
7050 {
7051   {
7052     BI opval = 0;
7053     CPU (h_xbit) = opval;
7054     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7055   }
7056   {
7057     BI opval = 0;
7058     SET_H_INSN_PREFIXED_P (opval);
7059     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7060   }
7061 }
7062 }
7063 }
7064
7065 #undef FLD
7066 }
7067   NEXT (vpc);
7068
7069   CASE (sem, INSN_SUB_D_R) : /* sub.d $Rs,$Rd */
7070 {
7071   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7072   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7073 #define FLD(f) abuf->fields.sfmt_addc_m.f
7074   int UNUSED written = 0;
7075   IADDR UNUSED pc = abuf->addr;
7076   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7077
7078 {
7079   SI tmp_tmpopd;
7080   SI tmp_tmpops;
7081   BI tmp_carry;
7082   SI tmp_newval;
7083   tmp_tmpops = GET_H_GR (FLD (f_operand1));
7084   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7085   tmp_carry = CPU (h_cbit);
7086   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7087   {
7088     SI opval = tmp_newval;
7089     SET_H_GR (FLD (f_operand2), opval);
7090     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7091   }
7092 {
7093   {
7094     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7095     CPU (h_cbit) = opval;
7096     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7097   }
7098   {
7099     BI opval = LTSI (tmp_newval, 0);
7100     CPU (h_nbit) = opval;
7101     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7102   }
7103   {
7104     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7105     CPU (h_zbit) = opval;
7106     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7107   }
7108   {
7109     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7110     CPU (h_vbit) = opval;
7111     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7112   }
7113 {
7114   {
7115     BI opval = 0;
7116     CPU (h_xbit) = opval;
7117     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7118   }
7119   {
7120     BI opval = 0;
7121     SET_H_INSN_PREFIXED_P (opval);
7122     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7123   }
7124 }
7125 }
7126 }
7127
7128 #undef FLD
7129 }
7130   NEXT (vpc);
7131
7132   CASE (sem, INSN_SUB_M_B_M) : /* sub-m.b [${Rs}${inc}],${Rd} */
7133 {
7134   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7135   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7136 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7137   int UNUSED written = 0;
7138   IADDR UNUSED pc = abuf->addr;
7139   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7140
7141 {
7142   QI tmp_tmpopd;
7143   QI tmp_tmpops;
7144   BI tmp_carry;
7145   QI tmp_newval;
7146   tmp_tmpops = ({   SI tmp_addr;
7147   QI tmp_tmp_mem;
7148   BI tmp_postinc;
7149   tmp_postinc = FLD (f_memmode);
7150 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
7151 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
7152 ; if (NEBI (tmp_postinc, 0)) {
7153 {
7154 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7155   tmp_addr = ADDSI (tmp_addr, 1);
7156 }
7157   {
7158     SI opval = tmp_addr;
7159     SET_H_GR (FLD (f_operand1), opval);
7160     written |= (1 << 12);
7161     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7162   }
7163 }
7164 }
7165 ; tmp_tmp_mem; });
7166   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7167   tmp_carry = CPU (h_cbit);
7168   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7169 {
7170   SI tmp_oldregval;
7171   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
7172   {
7173     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
7174     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7175     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7176   }
7177 }
7178 {
7179   {
7180     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
7181     CPU (h_cbit) = opval;
7182     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7183   }
7184   {
7185     BI opval = LTQI (tmp_newval, 0);
7186     CPU (h_nbit) = opval;
7187     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7188   }
7189   {
7190     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7191     CPU (h_zbit) = opval;
7192     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7193   }
7194   {
7195     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
7196     CPU (h_vbit) = opval;
7197     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7198   }
7199 {
7200   {
7201     BI opval = 0;
7202     CPU (h_xbit) = opval;
7203     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7204   }
7205   {
7206     BI opval = 0;
7207     SET_H_INSN_PREFIXED_P (opval);
7208     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7209   }
7210 }
7211 }
7212 }
7213
7214   abuf->written = written;
7215 #undef FLD
7216 }
7217   NEXT (vpc);
7218
7219   CASE (sem, INSN_SUB_M_W_M) : /* sub-m.w [${Rs}${inc}],${Rd} */
7220 {
7221   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7222   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7223 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7224   int UNUSED written = 0;
7225   IADDR UNUSED pc = abuf->addr;
7226   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7227
7228 {
7229   HI tmp_tmpopd;
7230   HI tmp_tmpops;
7231   BI tmp_carry;
7232   HI tmp_newval;
7233   tmp_tmpops = ({   SI tmp_addr;
7234   HI tmp_tmp_mem;
7235   BI tmp_postinc;
7236   tmp_postinc = FLD (f_memmode);
7237 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
7238 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
7239 ; if (NEBI (tmp_postinc, 0)) {
7240 {
7241 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7242   tmp_addr = ADDSI (tmp_addr, 2);
7243 }
7244   {
7245     SI opval = tmp_addr;
7246     SET_H_GR (FLD (f_operand1), opval);
7247     written |= (1 << 12);
7248     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7249   }
7250 }
7251 }
7252 ; tmp_tmp_mem; });
7253   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7254   tmp_carry = CPU (h_cbit);
7255   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7256 {
7257   SI tmp_oldregval;
7258   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
7259   {
7260     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
7261     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7262     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7263   }
7264 }
7265 {
7266   {
7267     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
7268     CPU (h_cbit) = opval;
7269     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7270   }
7271   {
7272     BI opval = LTHI (tmp_newval, 0);
7273     CPU (h_nbit) = opval;
7274     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7275   }
7276   {
7277     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7278     CPU (h_zbit) = opval;
7279     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7280   }
7281   {
7282     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
7283     CPU (h_vbit) = opval;
7284     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7285   }
7286 {
7287   {
7288     BI opval = 0;
7289     CPU (h_xbit) = opval;
7290     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7291   }
7292   {
7293     BI opval = 0;
7294     SET_H_INSN_PREFIXED_P (opval);
7295     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7296   }
7297 }
7298 }
7299 }
7300
7301   abuf->written = written;
7302 #undef FLD
7303 }
7304   NEXT (vpc);
7305
7306   CASE (sem, INSN_SUB_M_D_M) : /* sub-m.d [${Rs}${inc}],${Rd} */
7307 {
7308   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7309   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7310 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7311   int UNUSED written = 0;
7312   IADDR UNUSED pc = abuf->addr;
7313   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7314
7315 {
7316   SI tmp_tmpopd;
7317   SI tmp_tmpops;
7318   BI tmp_carry;
7319   SI tmp_newval;
7320   tmp_tmpops = ({   SI tmp_addr;
7321   SI tmp_tmp_mem;
7322   BI tmp_postinc;
7323   tmp_postinc = FLD (f_memmode);
7324 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
7325 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
7326 ; if (NEBI (tmp_postinc, 0)) {
7327 {
7328 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7329   tmp_addr = ADDSI (tmp_addr, 4);
7330 }
7331   {
7332     SI opval = tmp_addr;
7333     SET_H_GR (FLD (f_operand1), opval);
7334     written |= (1 << 11);
7335     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7336   }
7337 }
7338 }
7339 ; tmp_tmp_mem; });
7340   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7341   tmp_carry = CPU (h_cbit);
7342   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7343   {
7344     SI opval = tmp_newval;
7345     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7346     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7347   }
7348 {
7349   {
7350     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7351     CPU (h_cbit) = opval;
7352     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7353   }
7354   {
7355     BI opval = LTSI (tmp_newval, 0);
7356     CPU (h_nbit) = opval;
7357     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7358   }
7359   {
7360     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7361     CPU (h_zbit) = opval;
7362     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7363   }
7364   {
7365     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7366     CPU (h_vbit) = opval;
7367     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7368   }
7369 {
7370   {
7371     BI opval = 0;
7372     CPU (h_xbit) = opval;
7373     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7374   }
7375   {
7376     BI opval = 0;
7377     SET_H_INSN_PREFIXED_P (opval);
7378     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7379   }
7380 }
7381 }
7382 }
7383
7384   abuf->written = written;
7385 #undef FLD
7386 }
7387   NEXT (vpc);
7388
7389   CASE (sem, INSN_SUBCBR) : /* sub.b ${sconst8}],${Rd} */
7390 {
7391   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7392   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7393 #define FLD(f) abuf->fields.sfmt_addcbr.f
7394   int UNUSED written = 0;
7395   IADDR UNUSED pc = abuf->addr;
7396   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7397
7398 {
7399   QI tmp_tmpopd;
7400   QI tmp_tmpops;
7401   BI tmp_carry;
7402   QI tmp_newval;
7403   tmp_tmpops = FLD (f_indir_pc__byte);
7404   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7405   tmp_carry = CPU (h_cbit);
7406   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7407 {
7408   SI tmp_oldregval;
7409   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
7410   {
7411     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
7412     SET_H_GR (FLD (f_operand2), opval);
7413     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7414   }
7415 }
7416 {
7417   {
7418     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
7419     CPU (h_cbit) = opval;
7420     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7421   }
7422   {
7423     BI opval = LTQI (tmp_newval, 0);
7424     CPU (h_nbit) = opval;
7425     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7426   }
7427   {
7428     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7429     CPU (h_zbit) = opval;
7430     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7431   }
7432   {
7433     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
7434     CPU (h_vbit) = opval;
7435     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7436   }
7437 {
7438   {
7439     BI opval = 0;
7440     CPU (h_xbit) = opval;
7441     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7442   }
7443   {
7444     BI opval = 0;
7445     SET_H_INSN_PREFIXED_P (opval);
7446     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7447   }
7448 }
7449 }
7450 }
7451
7452 #undef FLD
7453 }
7454   NEXT (vpc);
7455
7456   CASE (sem, INSN_SUBCWR) : /* sub.w ${sconst16}],${Rd} */
7457 {
7458   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7459   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7460 #define FLD(f) abuf->fields.sfmt_addcwr.f
7461   int UNUSED written = 0;
7462   IADDR UNUSED pc = abuf->addr;
7463   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7464
7465 {
7466   HI tmp_tmpopd;
7467   HI tmp_tmpops;
7468   BI tmp_carry;
7469   HI tmp_newval;
7470   tmp_tmpops = FLD (f_indir_pc__word);
7471   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7472   tmp_carry = CPU (h_cbit);
7473   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7474 {
7475   SI tmp_oldregval;
7476   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
7477   {
7478     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
7479     SET_H_GR (FLD (f_operand2), opval);
7480     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7481   }
7482 }
7483 {
7484   {
7485     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
7486     CPU (h_cbit) = opval;
7487     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7488   }
7489   {
7490     BI opval = LTHI (tmp_newval, 0);
7491     CPU (h_nbit) = opval;
7492     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7493   }
7494   {
7495     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7496     CPU (h_zbit) = opval;
7497     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7498   }
7499   {
7500     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
7501     CPU (h_vbit) = opval;
7502     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7503   }
7504 {
7505   {
7506     BI opval = 0;
7507     CPU (h_xbit) = opval;
7508     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7509   }
7510   {
7511     BI opval = 0;
7512     SET_H_INSN_PREFIXED_P (opval);
7513     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7514   }
7515 }
7516 }
7517 }
7518
7519 #undef FLD
7520 }
7521   NEXT (vpc);
7522
7523   CASE (sem, INSN_SUBCDR) : /* sub.d ${const32}],${Rd} */
7524 {
7525   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7526   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7527 #define FLD(f) abuf->fields.sfmt_addcdr.f
7528   int UNUSED written = 0;
7529   IADDR UNUSED pc = abuf->addr;
7530   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
7531
7532 {
7533   SI tmp_tmpopd;
7534   SI tmp_tmpops;
7535   BI tmp_carry;
7536   SI tmp_newval;
7537   tmp_tmpops = FLD (f_indir_pc__dword);
7538   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7539   tmp_carry = CPU (h_cbit);
7540   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7541   {
7542     SI opval = tmp_newval;
7543     SET_H_GR (FLD (f_operand2), opval);
7544     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7545   }
7546 {
7547   {
7548     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7549     CPU (h_cbit) = opval;
7550     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7551   }
7552   {
7553     BI opval = LTSI (tmp_newval, 0);
7554     CPU (h_nbit) = opval;
7555     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7556   }
7557   {
7558     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7559     CPU (h_zbit) = opval;
7560     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7561   }
7562   {
7563     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7564     CPU (h_vbit) = opval;
7565     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7566   }
7567 {
7568   {
7569     BI opval = 0;
7570     CPU (h_xbit) = opval;
7571     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7572   }
7573   {
7574     BI opval = 0;
7575     SET_H_INSN_PREFIXED_P (opval);
7576     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7577   }
7578 }
7579 }
7580 }
7581
7582 #undef FLD
7583 }
7584   NEXT (vpc);
7585
7586   CASE (sem, INSN_SUBS_B_R) : /* subs.b $Rs,$Rd */
7587 {
7588   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7589   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7590 #define FLD(f) abuf->fields.sfmt_addc_m.f
7591   int UNUSED written = 0;
7592   IADDR UNUSED pc = abuf->addr;
7593   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7594
7595 {
7596   SI tmp_tmpopd;
7597   SI tmp_tmpops;
7598   BI tmp_carry;
7599   SI tmp_newval;
7600   tmp_tmpops = EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
7601   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7602   tmp_carry = CPU (h_cbit);
7603   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7604   {
7605     SI opval = tmp_newval;
7606     SET_H_GR (FLD (f_operand2), opval);
7607     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7608   }
7609 {
7610   {
7611     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7612     CPU (h_cbit) = opval;
7613     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7614   }
7615   {
7616     BI opval = LTSI (tmp_newval, 0);
7617     CPU (h_nbit) = opval;
7618     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7619   }
7620   {
7621     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7622     CPU (h_zbit) = opval;
7623     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7624   }
7625   {
7626     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7627     CPU (h_vbit) = opval;
7628     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7629   }
7630 {
7631   {
7632     BI opval = 0;
7633     CPU (h_xbit) = opval;
7634     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7635   }
7636   {
7637     BI opval = 0;
7638     SET_H_INSN_PREFIXED_P (opval);
7639     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7640   }
7641 }
7642 }
7643 }
7644
7645 #undef FLD
7646 }
7647   NEXT (vpc);
7648
7649   CASE (sem, INSN_SUBS_W_R) : /* subs.w $Rs,$Rd */
7650 {
7651   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7652   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7653 #define FLD(f) abuf->fields.sfmt_addc_m.f
7654   int UNUSED written = 0;
7655   IADDR UNUSED pc = abuf->addr;
7656   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7657
7658 {
7659   SI tmp_tmpopd;
7660   SI tmp_tmpops;
7661   BI tmp_carry;
7662   SI tmp_newval;
7663   tmp_tmpops = EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
7664   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7665   tmp_carry = CPU (h_cbit);
7666   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7667   {
7668     SI opval = tmp_newval;
7669     SET_H_GR (FLD (f_operand2), opval);
7670     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7671   }
7672 {
7673   {
7674     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7675     CPU (h_cbit) = opval;
7676     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7677   }
7678   {
7679     BI opval = LTSI (tmp_newval, 0);
7680     CPU (h_nbit) = opval;
7681     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7682   }
7683   {
7684     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7685     CPU (h_zbit) = opval;
7686     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7687   }
7688   {
7689     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7690     CPU (h_vbit) = opval;
7691     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7692   }
7693 {
7694   {
7695     BI opval = 0;
7696     CPU (h_xbit) = opval;
7697     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7698   }
7699   {
7700     BI opval = 0;
7701     SET_H_INSN_PREFIXED_P (opval);
7702     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7703   }
7704 }
7705 }
7706 }
7707
7708 #undef FLD
7709 }
7710   NEXT (vpc);
7711
7712   CASE (sem, INSN_SUBS_M_B_M) : /* subs-m.b [${Rs}${inc}],$Rd */
7713 {
7714   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7715   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7716 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7717   int UNUSED written = 0;
7718   IADDR UNUSED pc = abuf->addr;
7719   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7720
7721 {
7722   SI tmp_tmpopd;
7723   SI tmp_tmpops;
7724   BI tmp_carry;
7725   SI tmp_newval;
7726   tmp_tmpops = EXTQISI (({   SI tmp_addr;
7727   QI tmp_tmp_mem;
7728   BI tmp_postinc;
7729   tmp_postinc = FLD (f_memmode);
7730 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
7731 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
7732 ; if (NEBI (tmp_postinc, 0)) {
7733 {
7734 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7735   tmp_addr = ADDSI (tmp_addr, 1);
7736 }
7737   {
7738     SI opval = tmp_addr;
7739     SET_H_GR (FLD (f_operand1), opval);
7740     written |= (1 << 11);
7741     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7742   }
7743 }
7744 }
7745 ; tmp_tmp_mem; }));
7746   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7747   tmp_carry = CPU (h_cbit);
7748   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7749   {
7750     SI opval = tmp_newval;
7751     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7752     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7753   }
7754 {
7755   {
7756     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7757     CPU (h_cbit) = opval;
7758     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7759   }
7760   {
7761     BI opval = LTSI (tmp_newval, 0);
7762     CPU (h_nbit) = opval;
7763     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7764   }
7765   {
7766     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7767     CPU (h_zbit) = opval;
7768     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7769   }
7770   {
7771     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7772     CPU (h_vbit) = opval;
7773     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7774   }
7775 {
7776   {
7777     BI opval = 0;
7778     CPU (h_xbit) = opval;
7779     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7780   }
7781   {
7782     BI opval = 0;
7783     SET_H_INSN_PREFIXED_P (opval);
7784     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7785   }
7786 }
7787 }
7788 }
7789
7790   abuf->written = written;
7791 #undef FLD
7792 }
7793   NEXT (vpc);
7794
7795   CASE (sem, INSN_SUBS_M_W_M) : /* subs-m.w [${Rs}${inc}],$Rd */
7796 {
7797   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7798   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7799 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
7800   int UNUSED written = 0;
7801   IADDR UNUSED pc = abuf->addr;
7802   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
7803
7804 {
7805   SI tmp_tmpopd;
7806   SI tmp_tmpops;
7807   BI tmp_carry;
7808   SI tmp_newval;
7809   tmp_tmpops = EXTHISI (({   SI tmp_addr;
7810   HI tmp_tmp_mem;
7811   BI tmp_postinc;
7812   tmp_postinc = FLD (f_memmode);
7813 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
7814 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
7815 ; if (NEBI (tmp_postinc, 0)) {
7816 {
7817 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
7818   tmp_addr = ADDSI (tmp_addr, 2);
7819 }
7820   {
7821     SI opval = tmp_addr;
7822     SET_H_GR (FLD (f_operand1), opval);
7823     written |= (1 << 11);
7824     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7825   }
7826 }
7827 }
7828 ; tmp_tmp_mem; }));
7829   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7830   tmp_carry = CPU (h_cbit);
7831   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7832   {
7833     SI opval = tmp_newval;
7834     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
7835     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7836   }
7837 {
7838   {
7839     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7840     CPU (h_cbit) = opval;
7841     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7842   }
7843   {
7844     BI opval = LTSI (tmp_newval, 0);
7845     CPU (h_nbit) = opval;
7846     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7847   }
7848   {
7849     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7850     CPU (h_zbit) = opval;
7851     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7852   }
7853   {
7854     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7855     CPU (h_vbit) = opval;
7856     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7857   }
7858 {
7859   {
7860     BI opval = 0;
7861     CPU (h_xbit) = opval;
7862     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7863   }
7864   {
7865     BI opval = 0;
7866     SET_H_INSN_PREFIXED_P (opval);
7867     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7868   }
7869 }
7870 }
7871 }
7872
7873   abuf->written = written;
7874 #undef FLD
7875 }
7876   NEXT (vpc);
7877
7878   CASE (sem, INSN_SUBSCBR) : /* [${Rs}${inc}],$Rd */
7879 {
7880   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7881   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7882 #define FLD(f) abuf->fields.sfmt_addcbr.f
7883   int UNUSED written = 0;
7884   IADDR UNUSED pc = abuf->addr;
7885   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7886
7887 {
7888   SI tmp_tmpopd;
7889   SI tmp_tmpops;
7890   BI tmp_carry;
7891   SI tmp_newval;
7892   tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
7893   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7894   tmp_carry = CPU (h_cbit);
7895   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7896   {
7897     SI opval = tmp_newval;
7898     SET_H_GR (FLD (f_operand2), opval);
7899     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7900   }
7901 {
7902   {
7903     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7904     CPU (h_cbit) = opval;
7905     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7906   }
7907   {
7908     BI opval = LTSI (tmp_newval, 0);
7909     CPU (h_nbit) = opval;
7910     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7911   }
7912   {
7913     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7914     CPU (h_zbit) = opval;
7915     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7916   }
7917   {
7918     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7919     CPU (h_vbit) = opval;
7920     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7921   }
7922 {
7923   {
7924     BI opval = 0;
7925     CPU (h_xbit) = opval;
7926     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7927   }
7928   {
7929     BI opval = 0;
7930     SET_H_INSN_PREFIXED_P (opval);
7931     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7932   }
7933 }
7934 }
7935 }
7936
7937 #undef FLD
7938 }
7939   NEXT (vpc);
7940
7941   CASE (sem, INSN_SUBSCWR) : /* [${Rs}${inc}],$Rd */
7942 {
7943   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
7944   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
7945 #define FLD(f) abuf->fields.sfmt_addcwr.f
7946   int UNUSED written = 0;
7947   IADDR UNUSED pc = abuf->addr;
7948   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
7949
7950 {
7951   SI tmp_tmpopd;
7952   SI tmp_tmpops;
7953   BI tmp_carry;
7954   SI tmp_newval;
7955   tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
7956   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
7957   tmp_carry = CPU (h_cbit);
7958   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
7959   {
7960     SI opval = tmp_newval;
7961     SET_H_GR (FLD (f_operand2), opval);
7962     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
7963   }
7964 {
7965   {
7966     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
7967     CPU (h_cbit) = opval;
7968     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
7969   }
7970   {
7971     BI opval = LTSI (tmp_newval, 0);
7972     CPU (h_nbit) = opval;
7973     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
7974   }
7975   {
7976     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
7977     CPU (h_zbit) = opval;
7978     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
7979   }
7980   {
7981     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
7982     CPU (h_vbit) = opval;
7983     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
7984   }
7985 {
7986   {
7987     BI opval = 0;
7988     CPU (h_xbit) = opval;
7989     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
7990   }
7991   {
7992     BI opval = 0;
7993     SET_H_INSN_PREFIXED_P (opval);
7994     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
7995   }
7996 }
7997 }
7998 }
7999
8000 #undef FLD
8001 }
8002   NEXT (vpc);
8003
8004   CASE (sem, INSN_SUBU_B_R) : /* subu.b $Rs,$Rd */
8005 {
8006   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8007   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8008 #define FLD(f) abuf->fields.sfmt_addc_m.f
8009   int UNUSED written = 0;
8010   IADDR UNUSED pc = abuf->addr;
8011   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8012
8013 {
8014   SI tmp_tmpopd;
8015   SI tmp_tmpops;
8016   BI tmp_carry;
8017   SI tmp_newval;
8018   tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
8019   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8020   tmp_carry = CPU (h_cbit);
8021   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8022   {
8023     SI opval = tmp_newval;
8024     SET_H_GR (FLD (f_operand2), opval);
8025     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8026   }
8027 {
8028   {
8029     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8030     CPU (h_cbit) = opval;
8031     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8032   }
8033   {
8034     BI opval = LTSI (tmp_newval, 0);
8035     CPU (h_nbit) = opval;
8036     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8037   }
8038   {
8039     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8040     CPU (h_zbit) = opval;
8041     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8042   }
8043   {
8044     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8045     CPU (h_vbit) = opval;
8046     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8047   }
8048 {
8049   {
8050     BI opval = 0;
8051     CPU (h_xbit) = opval;
8052     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8053   }
8054   {
8055     BI opval = 0;
8056     SET_H_INSN_PREFIXED_P (opval);
8057     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8058   }
8059 }
8060 }
8061 }
8062
8063 #undef FLD
8064 }
8065   NEXT (vpc);
8066
8067   CASE (sem, INSN_SUBU_W_R) : /* subu.w $Rs,$Rd */
8068 {
8069   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8070   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8071 #define FLD(f) abuf->fields.sfmt_addc_m.f
8072   int UNUSED written = 0;
8073   IADDR UNUSED pc = abuf->addr;
8074   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8075
8076 {
8077   SI tmp_tmpopd;
8078   SI tmp_tmpops;
8079   BI tmp_carry;
8080   SI tmp_newval;
8081   tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
8082   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8083   tmp_carry = CPU (h_cbit);
8084   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8085   {
8086     SI opval = tmp_newval;
8087     SET_H_GR (FLD (f_operand2), opval);
8088     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8089   }
8090 {
8091   {
8092     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8093     CPU (h_cbit) = opval;
8094     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8095   }
8096   {
8097     BI opval = LTSI (tmp_newval, 0);
8098     CPU (h_nbit) = opval;
8099     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8100   }
8101   {
8102     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8103     CPU (h_zbit) = opval;
8104     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8105   }
8106   {
8107     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8108     CPU (h_vbit) = opval;
8109     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8110   }
8111 {
8112   {
8113     BI opval = 0;
8114     CPU (h_xbit) = opval;
8115     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8116   }
8117   {
8118     BI opval = 0;
8119     SET_H_INSN_PREFIXED_P (opval);
8120     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8121   }
8122 }
8123 }
8124 }
8125
8126 #undef FLD
8127 }
8128   NEXT (vpc);
8129
8130   CASE (sem, INSN_SUBU_M_B_M) : /* subu-m.b [${Rs}${inc}],$Rd */
8131 {
8132   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8133   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8134 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
8135   int UNUSED written = 0;
8136   IADDR UNUSED pc = abuf->addr;
8137   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8138
8139 {
8140   SI tmp_tmpopd;
8141   SI tmp_tmpops;
8142   BI tmp_carry;
8143   SI tmp_newval;
8144   tmp_tmpops = ZEXTQISI (({   SI tmp_addr;
8145   QI tmp_tmp_mem;
8146   BI tmp_postinc;
8147   tmp_postinc = FLD (f_memmode);
8148 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
8149 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
8150 ; if (NEBI (tmp_postinc, 0)) {
8151 {
8152 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8153   tmp_addr = ADDSI (tmp_addr, 1);
8154 }
8155   {
8156     SI opval = tmp_addr;
8157     SET_H_GR (FLD (f_operand1), opval);
8158     written |= (1 << 11);
8159     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8160   }
8161 }
8162 }
8163 ; tmp_tmp_mem; }));
8164   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8165   tmp_carry = CPU (h_cbit);
8166   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8167   {
8168     SI opval = tmp_newval;
8169     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
8170     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8171   }
8172 {
8173   {
8174     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8175     CPU (h_cbit) = opval;
8176     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8177   }
8178   {
8179     BI opval = LTSI (tmp_newval, 0);
8180     CPU (h_nbit) = opval;
8181     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8182   }
8183   {
8184     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8185     CPU (h_zbit) = opval;
8186     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8187   }
8188   {
8189     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8190     CPU (h_vbit) = opval;
8191     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8192   }
8193 {
8194   {
8195     BI opval = 0;
8196     CPU (h_xbit) = opval;
8197     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8198   }
8199   {
8200     BI opval = 0;
8201     SET_H_INSN_PREFIXED_P (opval);
8202     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8203   }
8204 }
8205 }
8206 }
8207
8208   abuf->written = written;
8209 #undef FLD
8210 }
8211   NEXT (vpc);
8212
8213   CASE (sem, INSN_SUBU_M_W_M) : /* subu-m.w [${Rs}${inc}],$Rd */
8214 {
8215   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8216   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8217 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
8218   int UNUSED written = 0;
8219   IADDR UNUSED pc = abuf->addr;
8220   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8221
8222 {
8223   SI tmp_tmpopd;
8224   SI tmp_tmpops;
8225   BI tmp_carry;
8226   SI tmp_newval;
8227   tmp_tmpops = ZEXTHISI (({   SI tmp_addr;
8228   HI tmp_tmp_mem;
8229   BI tmp_postinc;
8230   tmp_postinc = FLD (f_memmode);
8231 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
8232 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
8233 ; if (NEBI (tmp_postinc, 0)) {
8234 {
8235 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8236   tmp_addr = ADDSI (tmp_addr, 2);
8237 }
8238   {
8239     SI opval = tmp_addr;
8240     SET_H_GR (FLD (f_operand1), opval);
8241     written |= (1 << 11);
8242     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8243   }
8244 }
8245 }
8246 ; tmp_tmp_mem; }));
8247   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8248   tmp_carry = CPU (h_cbit);
8249   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8250   {
8251     SI opval = tmp_newval;
8252     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
8253     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8254   }
8255 {
8256   {
8257     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8258     CPU (h_cbit) = opval;
8259     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8260   }
8261   {
8262     BI opval = LTSI (tmp_newval, 0);
8263     CPU (h_nbit) = opval;
8264     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8265   }
8266   {
8267     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8268     CPU (h_zbit) = opval;
8269     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8270   }
8271   {
8272     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8273     CPU (h_vbit) = opval;
8274     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8275   }
8276 {
8277   {
8278     BI opval = 0;
8279     CPU (h_xbit) = opval;
8280     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8281   }
8282   {
8283     BI opval = 0;
8284     SET_H_INSN_PREFIXED_P (opval);
8285     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8286   }
8287 }
8288 }
8289 }
8290
8291   abuf->written = written;
8292 #undef FLD
8293 }
8294   NEXT (vpc);
8295
8296   CASE (sem, INSN_SUBUCBR) : /* [${Rs}${inc}],$Rd */
8297 {
8298   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8299   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8300 #define FLD(f) abuf->fields.sfmt_addcbr.f
8301   int UNUSED written = 0;
8302   IADDR UNUSED pc = abuf->addr;
8303   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
8304
8305 {
8306   SI tmp_tmpopd;
8307   SI tmp_tmpops;
8308   BI tmp_carry;
8309   SI tmp_newval;
8310   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
8311   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8312   tmp_carry = CPU (h_cbit);
8313   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8314   {
8315     SI opval = tmp_newval;
8316     SET_H_GR (FLD (f_operand2), opval);
8317     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8318   }
8319 {
8320   {
8321     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8322     CPU (h_cbit) = opval;
8323     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8324   }
8325   {
8326     BI opval = LTSI (tmp_newval, 0);
8327     CPU (h_nbit) = opval;
8328     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8329   }
8330   {
8331     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8332     CPU (h_zbit) = opval;
8333     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8334   }
8335   {
8336     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8337     CPU (h_vbit) = opval;
8338     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8339   }
8340 {
8341   {
8342     BI opval = 0;
8343     CPU (h_xbit) = opval;
8344     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8345   }
8346   {
8347     BI opval = 0;
8348     SET_H_INSN_PREFIXED_P (opval);
8349     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8350   }
8351 }
8352 }
8353 }
8354
8355 #undef FLD
8356 }
8357   NEXT (vpc);
8358
8359   CASE (sem, INSN_SUBUCWR) : /* [${Rs}${inc}],$Rd */
8360 {
8361   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8362   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8363 #define FLD(f) abuf->fields.sfmt_addcwr.f
8364   int UNUSED written = 0;
8365   IADDR UNUSED pc = abuf->addr;
8366   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
8367
8368 {
8369   SI tmp_tmpopd;
8370   SI tmp_tmpops;
8371   BI tmp_carry;
8372   SI tmp_newval;
8373   tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
8374   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8375   tmp_carry = CPU (h_cbit);
8376   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8377   {
8378     SI opval = tmp_newval;
8379     SET_H_GR (FLD (f_operand2), opval);
8380     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8381   }
8382 {
8383   {
8384     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8385     CPU (h_cbit) = opval;
8386     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8387   }
8388   {
8389     BI opval = LTSI (tmp_newval, 0);
8390     CPU (h_nbit) = opval;
8391     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8392   }
8393   {
8394     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8395     CPU (h_zbit) = opval;
8396     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8397   }
8398   {
8399     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8400     CPU (h_vbit) = opval;
8401     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8402   }
8403 {
8404   {
8405     BI opval = 0;
8406     CPU (h_xbit) = opval;
8407     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8408   }
8409   {
8410     BI opval = 0;
8411     SET_H_INSN_PREFIXED_P (opval);
8412     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8413   }
8414 }
8415 }
8416 }
8417
8418 #undef FLD
8419 }
8420   NEXT (vpc);
8421
8422   CASE (sem, INSN_ADDC_R) : /* addc $Rs,$Rd */
8423 {
8424   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8425   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8426 #define FLD(f) abuf->fields.sfmt_addc_m.f
8427   int UNUSED written = 0;
8428   IADDR UNUSED pc = abuf->addr;
8429   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8430
8431 {
8432 CPU (h_xbit) = 1;
8433 {
8434   SI tmp_tmpopd;
8435   SI tmp_tmpops;
8436   BI tmp_carry;
8437   SI tmp_newval;
8438   tmp_tmpops = GET_H_GR (FLD (f_operand1));
8439   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8440   tmp_carry = CPU (h_cbit);
8441   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8442   {
8443     SI opval = tmp_newval;
8444     SET_H_GR (FLD (f_operand2), opval);
8445     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8446   }
8447 {
8448   {
8449     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
8450     CPU (h_cbit) = opval;
8451     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8452   }
8453   {
8454     BI opval = LTSI (tmp_newval, 0);
8455     CPU (h_nbit) = opval;
8456     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8457   }
8458   {
8459     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8460     CPU (h_zbit) = opval;
8461     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8462   }
8463   {
8464     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8465     CPU (h_vbit) = opval;
8466     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8467   }
8468 {
8469   {
8470     BI opval = 0;
8471     CPU (h_xbit) = opval;
8472     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8473   }
8474   {
8475     BI opval = 0;
8476     SET_H_INSN_PREFIXED_P (opval);
8477     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8478   }
8479 }
8480 }
8481 }
8482 }
8483
8484 #undef FLD
8485 }
8486   NEXT (vpc);
8487
8488   CASE (sem, INSN_ADDC_M) : /* addc [${Rs}${inc}],${Rd} */
8489 {
8490   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8491   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8492 #define FLD(f) abuf->fields.sfmt_addc_m.f
8493   int UNUSED written = 0;
8494   IADDR UNUSED pc = abuf->addr;
8495   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8496
8497 {
8498 CPU (h_xbit) = 1;
8499 {
8500   SI tmp_tmpopd;
8501   SI tmp_tmpops;
8502   BI tmp_carry;
8503   SI tmp_newval;
8504   tmp_tmpops = ({   SI tmp_addr;
8505   SI tmp_tmp_mem;
8506   BI tmp_postinc;
8507   tmp_postinc = FLD (f_memmode);
8508 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
8509 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
8510 ; if (NEBI (tmp_postinc, 0)) {
8511 {
8512 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
8513   tmp_addr = ADDSI (tmp_addr, 4);
8514 }
8515   {
8516     SI opval = tmp_addr;
8517     SET_H_GR (FLD (f_operand1), opval);
8518     written |= (1 << 10);
8519     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8520   }
8521 }
8522 }
8523 ; tmp_tmp_mem; });
8524   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8525   tmp_carry = CPU (h_cbit);
8526   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8527   {
8528     SI opval = tmp_newval;
8529     SET_H_GR (FLD (f_operand2), opval);
8530     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8531   }
8532 {
8533   {
8534     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
8535     CPU (h_cbit) = opval;
8536     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8537   }
8538   {
8539     BI opval = LTSI (tmp_newval, 0);
8540     CPU (h_nbit) = opval;
8541     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8542   }
8543   {
8544     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8545     CPU (h_zbit) = opval;
8546     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8547   }
8548   {
8549     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8550     CPU (h_vbit) = opval;
8551     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8552   }
8553 {
8554   {
8555     BI opval = 0;
8556     CPU (h_xbit) = opval;
8557     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8558   }
8559   {
8560     BI opval = 0;
8561     SET_H_INSN_PREFIXED_P (opval);
8562     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8563   }
8564 }
8565 }
8566 }
8567 }
8568
8569   abuf->written = written;
8570 #undef FLD
8571 }
8572   NEXT (vpc);
8573
8574   CASE (sem, INSN_ADDC_C) : /* addc ${const32},${Rd} */
8575 {
8576   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8577   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8578 #define FLD(f) abuf->fields.sfmt_addcdr.f
8579   int UNUSED written = 0;
8580   IADDR UNUSED pc = abuf->addr;
8581   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
8582
8583 {
8584 CPU (h_xbit) = 1;
8585 {
8586   SI tmp_tmpopd;
8587   SI tmp_tmpops;
8588   BI tmp_carry;
8589   SI tmp_newval;
8590   tmp_tmpops = FLD (f_indir_pc__dword);
8591   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
8592   tmp_carry = CPU (h_cbit);
8593   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8594   {
8595     SI opval = tmp_newval;
8596     SET_H_GR (FLD (f_operand2), opval);
8597     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8598   }
8599 {
8600   {
8601     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
8602     CPU (h_cbit) = opval;
8603     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8604   }
8605   {
8606     BI opval = LTSI (tmp_newval, 0);
8607     CPU (h_nbit) = opval;
8608     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8609   }
8610   {
8611     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8612     CPU (h_zbit) = opval;
8613     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8614   }
8615   {
8616     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8617     CPU (h_vbit) = opval;
8618     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8619   }
8620 {
8621   {
8622     BI opval = 0;
8623     CPU (h_xbit) = opval;
8624     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8625   }
8626   {
8627     BI opval = 0;
8628     SET_H_INSN_PREFIXED_P (opval);
8629     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8630   }
8631 }
8632 }
8633 }
8634 }
8635
8636 #undef FLD
8637 }
8638   NEXT (vpc);
8639
8640   CASE (sem, INSN_LAPC_D) : /* lapc.d ${const32-pcrel},${Rd} */
8641 {
8642   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8643   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8644 #define FLD(f) abuf->fields.sfmt_lapc_d.f
8645   int UNUSED written = 0;
8646   IADDR UNUSED pc = abuf->addr;
8647   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
8648
8649 {
8650   {
8651     SI opval = FLD (i_const32_pcrel);
8652     SET_H_GR (FLD (f_operand2), opval);
8653     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8654   }
8655 {
8656   {
8657     BI opval = 0;
8658     CPU (h_xbit) = opval;
8659     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8660   }
8661   {
8662     BI opval = 0;
8663     SET_H_INSN_PREFIXED_P (opval);
8664     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8665   }
8666 }
8667 }
8668
8669 #undef FLD
8670 }
8671   NEXT (vpc);
8672
8673   CASE (sem, INSN_LAPCQ) : /* lapcq ${qo},${Rd} */
8674 {
8675   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8676   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8677 #define FLD(f) abuf->fields.sfmt_lapcq.f
8678   int UNUSED written = 0;
8679   IADDR UNUSED pc = abuf->addr;
8680   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8681
8682 {
8683   {
8684     SI opval = FLD (i_qo);
8685     SET_H_GR (FLD (f_operand2), opval);
8686     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8687   }
8688 {
8689   {
8690     BI opval = 0;
8691     CPU (h_xbit) = opval;
8692     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8693   }
8694   {
8695     BI opval = 0;
8696     SET_H_INSN_PREFIXED_P (opval);
8697     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8698   }
8699 }
8700 }
8701
8702 #undef FLD
8703 }
8704   NEXT (vpc);
8705
8706   CASE (sem, INSN_ADDI_B_R) : /* addi.b ${Rs-dfield}.m,${Rd-sfield} */
8707 {
8708   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8709   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8710 #define FLD(f) abuf->fields.sfmt_addc_m.f
8711   int UNUSED written = 0;
8712   IADDR UNUSED pc = abuf->addr;
8713   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8714
8715 {
8716   {
8717     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 1));
8718     SET_H_GR (FLD (f_operand1), opval);
8719     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8720   }
8721 {
8722   {
8723     BI opval = 0;
8724     CPU (h_xbit) = opval;
8725     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8726   }
8727   {
8728     BI opval = 0;
8729     SET_H_INSN_PREFIXED_P (opval);
8730     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8731   }
8732 }
8733 }
8734
8735 #undef FLD
8736 }
8737   NEXT (vpc);
8738
8739   CASE (sem, INSN_ADDI_W_R) : /* addi.w ${Rs-dfield}.m,${Rd-sfield} */
8740 {
8741   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8742   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8743 #define FLD(f) abuf->fields.sfmt_addc_m.f
8744   int UNUSED written = 0;
8745   IADDR UNUSED pc = abuf->addr;
8746   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8747
8748 {
8749   {
8750     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 2));
8751     SET_H_GR (FLD (f_operand1), opval);
8752     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8753   }
8754 {
8755   {
8756     BI opval = 0;
8757     CPU (h_xbit) = opval;
8758     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8759   }
8760   {
8761     BI opval = 0;
8762     SET_H_INSN_PREFIXED_P (opval);
8763     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8764   }
8765 }
8766 }
8767
8768 #undef FLD
8769 }
8770   NEXT (vpc);
8771
8772   CASE (sem, INSN_ADDI_D_R) : /* addi.d ${Rs-dfield}.m,${Rd-sfield} */
8773 {
8774   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8775   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8776 #define FLD(f) abuf->fields.sfmt_addc_m.f
8777   int UNUSED written = 0;
8778   IADDR UNUSED pc = abuf->addr;
8779   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8780
8781 {
8782   {
8783     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 4));
8784     SET_H_GR (FLD (f_operand1), opval);
8785     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8786   }
8787 {
8788   {
8789     BI opval = 0;
8790     CPU (h_xbit) = opval;
8791     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8792   }
8793   {
8794     BI opval = 0;
8795     SET_H_INSN_PREFIXED_P (opval);
8796     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8797   }
8798 }
8799 }
8800
8801 #undef FLD
8802 }
8803   NEXT (vpc);
8804
8805   CASE (sem, INSN_NEG_B_R) : /* neg.b $Rs,$Rd */
8806 {
8807   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8808   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8809 #define FLD(f) abuf->fields.sfmt_addc_m.f
8810   int UNUSED written = 0;
8811   IADDR UNUSED pc = abuf->addr;
8812   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8813
8814 {
8815   QI tmp_tmpopd;
8816   QI tmp_tmpops;
8817   BI tmp_carry;
8818   QI tmp_newval;
8819   tmp_tmpops = GET_H_GR (FLD (f_operand1));
8820   tmp_tmpopd = 0;
8821   tmp_carry = CPU (h_cbit);
8822   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8823 {
8824   SI tmp_oldregval;
8825   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
8826   {
8827     SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
8828     SET_H_GR (FLD (f_operand2), opval);
8829     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8830   }
8831 }
8832 {
8833   {
8834     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
8835     CPU (h_cbit) = opval;
8836     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8837   }
8838   {
8839     BI opval = LTQI (tmp_newval, 0);
8840     CPU (h_nbit) = opval;
8841     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8842   }
8843   {
8844     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8845     CPU (h_zbit) = opval;
8846     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8847   }
8848   {
8849     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
8850     CPU (h_vbit) = opval;
8851     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8852   }
8853 {
8854   {
8855     BI opval = 0;
8856     CPU (h_xbit) = opval;
8857     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8858   }
8859   {
8860     BI opval = 0;
8861     SET_H_INSN_PREFIXED_P (opval);
8862     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8863   }
8864 }
8865 }
8866 }
8867
8868 #undef FLD
8869 }
8870   NEXT (vpc);
8871
8872   CASE (sem, INSN_NEG_W_R) : /* neg.w $Rs,$Rd */
8873 {
8874   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8875   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8876 #define FLD(f) abuf->fields.sfmt_addc_m.f
8877   int UNUSED written = 0;
8878   IADDR UNUSED pc = abuf->addr;
8879   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8880
8881 {
8882   HI tmp_tmpopd;
8883   HI tmp_tmpops;
8884   BI tmp_carry;
8885   HI tmp_newval;
8886   tmp_tmpops = GET_H_GR (FLD (f_operand1));
8887   tmp_tmpopd = 0;
8888   tmp_carry = CPU (h_cbit);
8889   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8890 {
8891   SI tmp_oldregval;
8892   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
8893   {
8894     SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
8895     SET_H_GR (FLD (f_operand2), opval);
8896     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8897   }
8898 }
8899 {
8900   {
8901     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
8902     CPU (h_cbit) = opval;
8903     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8904   }
8905   {
8906     BI opval = LTHI (tmp_newval, 0);
8907     CPU (h_nbit) = opval;
8908     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8909   }
8910   {
8911     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8912     CPU (h_zbit) = opval;
8913     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8914   }
8915   {
8916     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
8917     CPU (h_vbit) = opval;
8918     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8919   }
8920 {
8921   {
8922     BI opval = 0;
8923     CPU (h_xbit) = opval;
8924     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8925   }
8926   {
8927     BI opval = 0;
8928     SET_H_INSN_PREFIXED_P (opval);
8929     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8930   }
8931 }
8932 }
8933 }
8934
8935 #undef FLD
8936 }
8937   NEXT (vpc);
8938
8939   CASE (sem, INSN_NEG_D_R) : /* neg.d $Rs,$Rd */
8940 {
8941   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
8942   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
8943 #define FLD(f) abuf->fields.sfmt_addc_m.f
8944   int UNUSED written = 0;
8945   IADDR UNUSED pc = abuf->addr;
8946   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
8947
8948 {
8949   SI tmp_tmpopd;
8950   SI tmp_tmpops;
8951   BI tmp_carry;
8952   SI tmp_newval;
8953   tmp_tmpops = GET_H_GR (FLD (f_operand1));
8954   tmp_tmpopd = 0;
8955   tmp_carry = CPU (h_cbit);
8956   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
8957   {
8958     SI opval = tmp_newval;
8959     SET_H_GR (FLD (f_operand2), opval);
8960     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
8961   }
8962 {
8963   {
8964     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
8965     CPU (h_cbit) = opval;
8966     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
8967   }
8968   {
8969     BI opval = LTSI (tmp_newval, 0);
8970     CPU (h_nbit) = opval;
8971     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
8972   }
8973   {
8974     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
8975     CPU (h_zbit) = opval;
8976     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
8977   }
8978   {
8979     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
8980     CPU (h_vbit) = opval;
8981     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
8982   }
8983 {
8984   {
8985     BI opval = 0;
8986     CPU (h_xbit) = opval;
8987     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
8988   }
8989   {
8990     BI opval = 0;
8991     SET_H_INSN_PREFIXED_P (opval);
8992     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
8993   }
8994 }
8995 }
8996 }
8997
8998 #undef FLD
8999 }
9000   NEXT (vpc);
9001
9002   CASE (sem, INSN_TEST_M_B_M) : /* test-m.b [${Rs}${inc}] */
9003 {
9004   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9005   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9006 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
9007   int UNUSED written = 0;
9008   IADDR UNUSED pc = abuf->addr;
9009   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9010
9011 {
9012   QI tmp_tmpd;
9013   tmp_tmpd = ({   SI tmp_addr;
9014   QI tmp_tmp_mem;
9015   BI tmp_postinc;
9016   tmp_postinc = FLD (f_memmode);
9017 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
9018 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
9019 ; if (NEBI (tmp_postinc, 0)) {
9020 {
9021 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9022   tmp_addr = ADDSI (tmp_addr, 1);
9023 }
9024   {
9025     SI opval = tmp_addr;
9026     SET_H_GR (FLD (f_operand1), opval);
9027     written |= (1 << 8);
9028     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9029   }
9030 }
9031 }
9032 ; tmp_tmp_mem; });
9033 {
9034   QI tmp_tmpopd;
9035   QI tmp_tmpops;
9036   BI tmp_carry;
9037   QI tmp_newval;
9038   tmp_tmpops = 0;
9039   tmp_tmpopd = tmp_tmpd;
9040   tmp_carry = CPU (h_cbit);
9041   tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
9042 ((void) 0); /*nop*/
9043 {
9044   {
9045     BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
9046     CPU (h_cbit) = opval;
9047     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9048   }
9049   {
9050     BI opval = LTQI (tmp_newval, 0);
9051     CPU (h_nbit) = opval;
9052     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9053   }
9054   {
9055     BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9056     CPU (h_zbit) = opval;
9057     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9058   }
9059   {
9060     BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
9061     CPU (h_vbit) = opval;
9062     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9063   }
9064 {
9065   {
9066     BI opval = 0;
9067     CPU (h_xbit) = opval;
9068     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9069   }
9070   {
9071     BI opval = 0;
9072     SET_H_INSN_PREFIXED_P (opval);
9073     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9074   }
9075 }
9076 }
9077 }
9078 }
9079
9080   abuf->written = written;
9081 #undef FLD
9082 }
9083   NEXT (vpc);
9084
9085   CASE (sem, INSN_TEST_M_W_M) : /* test-m.w [${Rs}${inc}] */
9086 {
9087   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9088   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9089 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
9090   int UNUSED written = 0;
9091   IADDR UNUSED pc = abuf->addr;
9092   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9093
9094 {
9095   HI tmp_tmpd;
9096   tmp_tmpd = ({   SI tmp_addr;
9097   HI tmp_tmp_mem;
9098   BI tmp_postinc;
9099   tmp_postinc = FLD (f_memmode);
9100 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
9101 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
9102 ; if (NEBI (tmp_postinc, 0)) {
9103 {
9104 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9105   tmp_addr = ADDSI (tmp_addr, 2);
9106 }
9107   {
9108     SI opval = tmp_addr;
9109     SET_H_GR (FLD (f_operand1), opval);
9110     written |= (1 << 8);
9111     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9112   }
9113 }
9114 }
9115 ; tmp_tmp_mem; });
9116 {
9117   HI tmp_tmpopd;
9118   HI tmp_tmpops;
9119   BI tmp_carry;
9120   HI tmp_newval;
9121   tmp_tmpops = 0;
9122   tmp_tmpopd = tmp_tmpd;
9123   tmp_carry = CPU (h_cbit);
9124   tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
9125 ((void) 0); /*nop*/
9126 {
9127   {
9128     BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
9129     CPU (h_cbit) = opval;
9130     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9131   }
9132   {
9133     BI opval = LTHI (tmp_newval, 0);
9134     CPU (h_nbit) = opval;
9135     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9136   }
9137   {
9138     BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9139     CPU (h_zbit) = opval;
9140     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9141   }
9142   {
9143     BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
9144     CPU (h_vbit) = opval;
9145     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9146   }
9147 {
9148   {
9149     BI opval = 0;
9150     CPU (h_xbit) = opval;
9151     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9152   }
9153   {
9154     BI opval = 0;
9155     SET_H_INSN_PREFIXED_P (opval);
9156     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9157   }
9158 }
9159 }
9160 }
9161 }
9162
9163   abuf->written = written;
9164 #undef FLD
9165 }
9166   NEXT (vpc);
9167
9168   CASE (sem, INSN_TEST_M_D_M) : /* test-m.d [${Rs}${inc}] */
9169 {
9170   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9171   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9172 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
9173   int UNUSED written = 0;
9174   IADDR UNUSED pc = abuf->addr;
9175   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9176
9177 {
9178   SI tmp_tmpd;
9179   tmp_tmpd = ({   SI tmp_addr;
9180   SI tmp_tmp_mem;
9181   BI tmp_postinc;
9182   tmp_postinc = FLD (f_memmode);
9183 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
9184 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
9185 ; if (NEBI (tmp_postinc, 0)) {
9186 {
9187 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9188   tmp_addr = ADDSI (tmp_addr, 4);
9189 }
9190   {
9191     SI opval = tmp_addr;
9192     SET_H_GR (FLD (f_operand1), opval);
9193     written |= (1 << 8);
9194     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9195   }
9196 }
9197 }
9198 ; tmp_tmp_mem; });
9199 {
9200   SI tmp_tmpopd;
9201   SI tmp_tmpops;
9202   BI tmp_carry;
9203   SI tmp_newval;
9204   tmp_tmpops = 0;
9205   tmp_tmpopd = tmp_tmpd;
9206   tmp_carry = CPU (h_cbit);
9207   tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
9208 ((void) 0); /*nop*/
9209 {
9210   {
9211     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
9212     CPU (h_cbit) = opval;
9213     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9214   }
9215   {
9216     BI opval = LTSI (tmp_newval, 0);
9217     CPU (h_nbit) = opval;
9218     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9219   }
9220   {
9221     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9222     CPU (h_zbit) = opval;
9223     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9224   }
9225   {
9226     BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
9227     CPU (h_vbit) = opval;
9228     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9229   }
9230 {
9231   {
9232     BI opval = 0;
9233     CPU (h_xbit) = opval;
9234     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9235   }
9236   {
9237     BI opval = 0;
9238     SET_H_INSN_PREFIXED_P (opval);
9239     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9240   }
9241 }
9242 }
9243 }
9244 }
9245
9246   abuf->written = written;
9247 #undef FLD
9248 }
9249   NEXT (vpc);
9250
9251   CASE (sem, INSN_MOVE_R_M_B_M) : /* move-r-m.b ${Rs-dfield},[${Rd-sfield}${inc}] */
9252 {
9253   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9254   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9255 #define FLD(f) abuf->fields.sfmt_addc_m.f
9256   int UNUSED written = 0;
9257   IADDR UNUSED pc = abuf->addr;
9258   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9259
9260 {
9261   QI tmp_tmpd;
9262   tmp_tmpd = GET_H_GR (FLD (f_operand2));
9263 {
9264   SI tmp_addr;
9265   BI tmp_postinc;
9266   tmp_postinc = FLD (f_memmode);
9267   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
9268 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
9269 if (EQBI (CPU (h_pbit), 0)) {
9270 {
9271   {
9272     QI opval = tmp_tmpd;
9273     SETMEMQI (current_cpu, pc, tmp_addr, opval);
9274     written |= (1 << 10);
9275     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9276   }
9277   {
9278     BI opval = CPU (h_pbit);
9279     CPU (h_cbit) = opval;
9280     written |= (1 << 9);
9281     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9282   }
9283 }
9284 } else {
9285   {
9286     BI opval = 1;
9287     CPU (h_cbit) = opval;
9288     written |= (1 << 9);
9289     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9290   }
9291 }
9292 } else {
9293   {
9294     QI opval = tmp_tmpd;
9295     SETMEMQI (current_cpu, pc, tmp_addr, opval);
9296     written |= (1 << 10);
9297     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9298   }
9299 }
9300 if (NEBI (tmp_postinc, 0)) {
9301 {
9302 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9303   tmp_addr = ADDSI (tmp_addr, 1);
9304 }
9305   {
9306     SI opval = tmp_addr;
9307     SET_H_GR (FLD (f_operand1), opval);
9308     written |= (1 << 8);
9309     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9310   }
9311 }
9312 }
9313 }
9314 {
9315   {
9316     BI opval = 0;
9317     CPU (h_xbit) = opval;
9318     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9319   }
9320   {
9321     BI opval = 0;
9322     SET_H_INSN_PREFIXED_P (opval);
9323     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9324   }
9325 }
9326 }
9327
9328   abuf->written = written;
9329 #undef FLD
9330 }
9331   NEXT (vpc);
9332
9333   CASE (sem, INSN_MOVE_R_M_W_M) : /* move-r-m.w ${Rs-dfield},[${Rd-sfield}${inc}] */
9334 {
9335   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9336   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9337 #define FLD(f) abuf->fields.sfmt_addc_m.f
9338   int UNUSED written = 0;
9339   IADDR UNUSED pc = abuf->addr;
9340   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9341
9342 {
9343   HI tmp_tmpd;
9344   tmp_tmpd = GET_H_GR (FLD (f_operand2));
9345 {
9346   SI tmp_addr;
9347   BI tmp_postinc;
9348   tmp_postinc = FLD (f_memmode);
9349   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
9350 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
9351 if (EQBI (CPU (h_pbit), 0)) {
9352 {
9353   {
9354     HI opval = tmp_tmpd;
9355     SETMEMHI (current_cpu, pc, tmp_addr, opval);
9356     written |= (1 << 10);
9357     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9358   }
9359   {
9360     BI opval = CPU (h_pbit);
9361     CPU (h_cbit) = opval;
9362     written |= (1 << 9);
9363     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9364   }
9365 }
9366 } else {
9367   {
9368     BI opval = 1;
9369     CPU (h_cbit) = opval;
9370     written |= (1 << 9);
9371     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9372   }
9373 }
9374 } else {
9375   {
9376     HI opval = tmp_tmpd;
9377     SETMEMHI (current_cpu, pc, tmp_addr, opval);
9378     written |= (1 << 10);
9379     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9380   }
9381 }
9382 if (NEBI (tmp_postinc, 0)) {
9383 {
9384 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9385   tmp_addr = ADDSI (tmp_addr, 2);
9386 }
9387   {
9388     SI opval = tmp_addr;
9389     SET_H_GR (FLD (f_operand1), opval);
9390     written |= (1 << 8);
9391     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9392   }
9393 }
9394 }
9395 }
9396 {
9397   {
9398     BI opval = 0;
9399     CPU (h_xbit) = opval;
9400     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9401   }
9402   {
9403     BI opval = 0;
9404     SET_H_INSN_PREFIXED_P (opval);
9405     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9406   }
9407 }
9408 }
9409
9410   abuf->written = written;
9411 #undef FLD
9412 }
9413   NEXT (vpc);
9414
9415   CASE (sem, INSN_MOVE_R_M_D_M) : /* move-r-m.d ${Rs-dfield},[${Rd-sfield}${inc}] */
9416 {
9417   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9418   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9419 #define FLD(f) abuf->fields.sfmt_addc_m.f
9420   int UNUSED written = 0;
9421   IADDR UNUSED pc = abuf->addr;
9422   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9423
9424 {
9425   SI tmp_tmpd;
9426   tmp_tmpd = GET_H_GR (FLD (f_operand2));
9427 {
9428   SI tmp_addr;
9429   BI tmp_postinc;
9430   tmp_postinc = FLD (f_memmode);
9431   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
9432 if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
9433 if (EQBI (CPU (h_pbit), 0)) {
9434 {
9435   {
9436     SI opval = tmp_tmpd;
9437     SETMEMSI (current_cpu, pc, tmp_addr, opval);
9438     written |= (1 << 10);
9439     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9440   }
9441   {
9442     BI opval = CPU (h_pbit);
9443     CPU (h_cbit) = opval;
9444     written |= (1 << 9);
9445     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9446   }
9447 }
9448 } else {
9449   {
9450     BI opval = 1;
9451     CPU (h_cbit) = opval;
9452     written |= (1 << 9);
9453     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9454   }
9455 }
9456 } else {
9457   {
9458     SI opval = tmp_tmpd;
9459     SETMEMSI (current_cpu, pc, tmp_addr, opval);
9460     written |= (1 << 10);
9461     TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
9462   }
9463 }
9464 if (NEBI (tmp_postinc, 0)) {
9465 {
9466 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
9467   tmp_addr = ADDSI (tmp_addr, 4);
9468 }
9469   {
9470     SI opval = tmp_addr;
9471     SET_H_GR (FLD (f_operand1), opval);
9472     written |= (1 << 8);
9473     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9474   }
9475 }
9476 }
9477 }
9478 {
9479   {
9480     BI opval = 0;
9481     CPU (h_xbit) = opval;
9482     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9483   }
9484   {
9485     BI opval = 0;
9486     SET_H_INSN_PREFIXED_P (opval);
9487     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9488   }
9489 }
9490 }
9491
9492   abuf->written = written;
9493 #undef FLD
9494 }
9495   NEXT (vpc);
9496
9497   CASE (sem, INSN_MULS_B) : /* muls.b $Rs,$Rd */
9498 {
9499   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9500   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9501 #define FLD(f) abuf->fields.sfmt_muls_b.f
9502   int UNUSED written = 0;
9503   IADDR UNUSED pc = abuf->addr;
9504   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9505
9506 {
9507   DI tmp_src1;
9508   DI tmp_src2;
9509   DI tmp_tmpr;
9510   tmp_src1 = EXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
9511   tmp_src2 = EXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand2))));
9512   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9513   {
9514     SI opval = TRUNCDISI (tmp_tmpr);
9515     SET_H_GR (FLD (f_operand2), opval);
9516     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9517   }
9518   {
9519     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9520     SET_H_SR (((UINT) 7), opval);
9521     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9522   }
9523 {
9524   {
9525     BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
9526     CPU (h_cbit) = opval;
9527     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9528   }
9529   {
9530     BI opval = LTDI (tmp_tmpr, 0);
9531     CPU (h_nbit) = opval;
9532     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9533   }
9534   {
9535     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9536     CPU (h_zbit) = opval;
9537     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9538   }
9539   {
9540     BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
9541     CPU (h_vbit) = opval;
9542     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9543   }
9544 {
9545   {
9546     BI opval = 0;
9547     CPU (h_xbit) = opval;
9548     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9549   }
9550   {
9551     BI opval = 0;
9552     SET_H_INSN_PREFIXED_P (opval);
9553     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9554   }
9555 }
9556 }
9557 }
9558
9559 #undef FLD
9560 }
9561   NEXT (vpc);
9562
9563   CASE (sem, INSN_MULS_W) : /* muls.w $Rs,$Rd */
9564 {
9565   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9566   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9567 #define FLD(f) abuf->fields.sfmt_muls_b.f
9568   int UNUSED written = 0;
9569   IADDR UNUSED pc = abuf->addr;
9570   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9571
9572 {
9573   DI tmp_src1;
9574   DI tmp_src2;
9575   DI tmp_tmpr;
9576   tmp_src1 = EXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
9577   tmp_src2 = EXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand2))));
9578   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9579   {
9580     SI opval = TRUNCDISI (tmp_tmpr);
9581     SET_H_GR (FLD (f_operand2), opval);
9582     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9583   }
9584   {
9585     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9586     SET_H_SR (((UINT) 7), opval);
9587     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9588   }
9589 {
9590   {
9591     BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
9592     CPU (h_cbit) = opval;
9593     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9594   }
9595   {
9596     BI opval = LTDI (tmp_tmpr, 0);
9597     CPU (h_nbit) = opval;
9598     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9599   }
9600   {
9601     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9602     CPU (h_zbit) = opval;
9603     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9604   }
9605   {
9606     BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
9607     CPU (h_vbit) = opval;
9608     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9609   }
9610 {
9611   {
9612     BI opval = 0;
9613     CPU (h_xbit) = opval;
9614     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9615   }
9616   {
9617     BI opval = 0;
9618     SET_H_INSN_PREFIXED_P (opval);
9619     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9620   }
9621 }
9622 }
9623 }
9624
9625 #undef FLD
9626 }
9627   NEXT (vpc);
9628
9629   CASE (sem, INSN_MULS_D) : /* muls.d $Rs,$Rd */
9630 {
9631   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9632   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9633 #define FLD(f) abuf->fields.sfmt_muls_b.f
9634   int UNUSED written = 0;
9635   IADDR UNUSED pc = abuf->addr;
9636   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9637
9638 {
9639   DI tmp_src1;
9640   DI tmp_src2;
9641   DI tmp_tmpr;
9642   tmp_src1 = EXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand1))));
9643   tmp_src2 = EXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand2))));
9644   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9645   {
9646     SI opval = TRUNCDISI (tmp_tmpr);
9647     SET_H_GR (FLD (f_operand2), opval);
9648     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9649   }
9650   {
9651     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9652     SET_H_SR (((UINT) 7), opval);
9653     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9654   }
9655 {
9656   {
9657     BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
9658     CPU (h_cbit) = opval;
9659     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9660   }
9661   {
9662     BI opval = LTDI (tmp_tmpr, 0);
9663     CPU (h_nbit) = opval;
9664     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9665   }
9666   {
9667     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9668     CPU (h_zbit) = opval;
9669     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9670   }
9671   {
9672     BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
9673     CPU (h_vbit) = opval;
9674     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9675   }
9676 {
9677   {
9678     BI opval = 0;
9679     CPU (h_xbit) = opval;
9680     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9681   }
9682   {
9683     BI opval = 0;
9684     SET_H_INSN_PREFIXED_P (opval);
9685     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9686   }
9687 }
9688 }
9689 }
9690
9691 #undef FLD
9692 }
9693   NEXT (vpc);
9694
9695   CASE (sem, INSN_MULU_B) : /* mulu.b $Rs,$Rd */
9696 {
9697   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9698   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9699 #define FLD(f) abuf->fields.sfmt_muls_b.f
9700   int UNUSED written = 0;
9701   IADDR UNUSED pc = abuf->addr;
9702   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9703
9704 {
9705   DI tmp_src1;
9706   DI tmp_src2;
9707   DI tmp_tmpr;
9708   tmp_src1 = ZEXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
9709   tmp_src2 = ZEXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand2))));
9710   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9711   {
9712     SI opval = TRUNCDISI (tmp_tmpr);
9713     SET_H_GR (FLD (f_operand2), opval);
9714     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9715   }
9716   {
9717     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9718     SET_H_SR (((UINT) 7), opval);
9719     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9720   }
9721 {
9722   {
9723     BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
9724     CPU (h_cbit) = opval;
9725     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9726   }
9727   {
9728     BI opval = LTDI (tmp_tmpr, 0);
9729     CPU (h_nbit) = opval;
9730     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9731   }
9732   {
9733     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9734     CPU (h_zbit) = opval;
9735     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9736   }
9737   {
9738     BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
9739     CPU (h_vbit) = opval;
9740     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9741   }
9742 {
9743   {
9744     BI opval = 0;
9745     CPU (h_xbit) = opval;
9746     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9747   }
9748   {
9749     BI opval = 0;
9750     SET_H_INSN_PREFIXED_P (opval);
9751     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9752   }
9753 }
9754 }
9755 }
9756
9757 #undef FLD
9758 }
9759   NEXT (vpc);
9760
9761   CASE (sem, INSN_MULU_W) : /* mulu.w $Rs,$Rd */
9762 {
9763   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9764   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9765 #define FLD(f) abuf->fields.sfmt_muls_b.f
9766   int UNUSED written = 0;
9767   IADDR UNUSED pc = abuf->addr;
9768   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9769
9770 {
9771   DI tmp_src1;
9772   DI tmp_src2;
9773   DI tmp_tmpr;
9774   tmp_src1 = ZEXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
9775   tmp_src2 = ZEXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand2))));
9776   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9777   {
9778     SI opval = TRUNCDISI (tmp_tmpr);
9779     SET_H_GR (FLD (f_operand2), opval);
9780     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9781   }
9782   {
9783     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9784     SET_H_SR (((UINT) 7), opval);
9785     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9786   }
9787 {
9788   {
9789     BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
9790     CPU (h_cbit) = opval;
9791     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9792   }
9793   {
9794     BI opval = LTDI (tmp_tmpr, 0);
9795     CPU (h_nbit) = opval;
9796     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9797   }
9798   {
9799     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9800     CPU (h_zbit) = opval;
9801     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9802   }
9803   {
9804     BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
9805     CPU (h_vbit) = opval;
9806     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9807   }
9808 {
9809   {
9810     BI opval = 0;
9811     CPU (h_xbit) = opval;
9812     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9813   }
9814   {
9815     BI opval = 0;
9816     SET_H_INSN_PREFIXED_P (opval);
9817     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9818   }
9819 }
9820 }
9821 }
9822
9823 #undef FLD
9824 }
9825   NEXT (vpc);
9826
9827   CASE (sem, INSN_MULU_D) : /* mulu.d $Rs,$Rd */
9828 {
9829   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9830   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9831 #define FLD(f) abuf->fields.sfmt_muls_b.f
9832   int UNUSED written = 0;
9833   IADDR UNUSED pc = abuf->addr;
9834   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9835
9836 {
9837   DI tmp_src1;
9838   DI tmp_src2;
9839   DI tmp_tmpr;
9840   tmp_src1 = ZEXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand1))));
9841   tmp_src2 = ZEXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand2))));
9842   tmp_tmpr = MULDI (tmp_src1, tmp_src2);
9843   {
9844     SI opval = TRUNCDISI (tmp_tmpr);
9845     SET_H_GR (FLD (f_operand2), opval);
9846     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9847   }
9848   {
9849     SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
9850     SET_H_SR (((UINT) 7), opval);
9851     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
9852   }
9853 {
9854   {
9855     BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
9856     CPU (h_cbit) = opval;
9857     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
9858   }
9859   {
9860     BI opval = LTDI (tmp_tmpr, 0);
9861     CPU (h_nbit) = opval;
9862     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9863   }
9864   {
9865     BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9866     CPU (h_zbit) = opval;
9867     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9868   }
9869   {
9870     BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
9871     CPU (h_vbit) = opval;
9872     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9873   }
9874 {
9875   {
9876     BI opval = 0;
9877     CPU (h_xbit) = opval;
9878     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9879   }
9880   {
9881     BI opval = 0;
9882     SET_H_INSN_PREFIXED_P (opval);
9883     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9884   }
9885 }
9886 }
9887 }
9888
9889 #undef FLD
9890 }
9891   NEXT (vpc);
9892
9893   CASE (sem, INSN_MCP) : /* mcp $Ps,$Rd */
9894 {
9895   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9896   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9897 #define FLD(f) abuf->fields.sfmt_mcp.f
9898   int UNUSED written = 0;
9899   IADDR UNUSED pc = abuf->addr;
9900   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9901
9902 {
9903 CPU (h_xbit) = 1;
9904 CPU (h_zbit) = 1;
9905 {
9906   SI tmp_tmpopd;
9907   SI tmp_tmpops;
9908   BI tmp_carry;
9909   SI tmp_newval;
9910   tmp_tmpops = GET_H_SR (FLD (f_operand2));
9911   tmp_tmpopd = GET_H_GR (FLD (f_operand1));
9912   tmp_carry = CPU (h_rbit);
9913   tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
9914   {
9915     SI opval = tmp_newval;
9916     SET_H_GR (FLD (f_operand1), opval);
9917     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9918   }
9919 {
9920   {
9921     BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
9922     CPU (h_rbit) = opval;
9923     TRACE_RESULT (current_cpu, abuf, "rbit", 'x', opval);
9924   }
9925   {
9926     BI opval = LTSI (tmp_newval, 0);
9927     CPU (h_nbit) = opval;
9928     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9929   }
9930   {
9931     BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
9932     CPU (h_zbit) = opval;
9933     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9934   }
9935   {
9936     BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
9937     CPU (h_vbit) = opval;
9938     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
9939   }
9940 {
9941   {
9942     BI opval = 0;
9943     CPU (h_xbit) = opval;
9944     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9945   }
9946   {
9947     BI opval = 0;
9948     SET_H_INSN_PREFIXED_P (opval);
9949     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
9950   }
9951 }
9952 }
9953 }
9954 }
9955
9956 #undef FLD
9957 }
9958   NEXT (vpc);
9959
9960   CASE (sem, INSN_DSTEP) : /* dstep $Rs,$Rd */
9961 {
9962   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
9963   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
9964 #define FLD(f) abuf->fields.sfmt_muls_b.f
9965   int UNUSED written = 0;
9966   IADDR UNUSED pc = abuf->addr;
9967   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
9968
9969 {
9970   SI tmp_tmp;
9971   SI tmp_tmps;
9972   SI tmp_tmpd;
9973   tmp_tmps = GET_H_GR (FLD (f_operand1));
9974   tmp_tmp = SLLSI (GET_H_GR (FLD (f_operand2)), 1);
9975   tmp_tmpd = ((GEUSI (tmp_tmp, tmp_tmps)) ? (SUBSI (tmp_tmp, tmp_tmps)) : (tmp_tmp));
9976   {
9977     SI opval = tmp_tmpd;
9978     SET_H_GR (FLD (f_operand2), opval);
9979     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
9980   }
9981 {
9982   {
9983     BI opval = LTSI (tmp_tmpd, 0);
9984     CPU (h_nbit) = opval;
9985     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
9986   }
9987   {
9988     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
9989     CPU (h_zbit) = opval;
9990     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
9991   }
9992 SET_H_CBIT_MOVE (0);
9993 SET_H_VBIT_MOVE (0);
9994 {
9995   {
9996     BI opval = 0;
9997     CPU (h_xbit) = opval;
9998     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
9999   }
10000   {
10001     BI opval = 0;
10002     SET_H_INSN_PREFIXED_P (opval);
10003     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10004   }
10005 }
10006 }
10007 }
10008
10009 #undef FLD
10010 }
10011   NEXT (vpc);
10012
10013   CASE (sem, INSN_ABS) : /* abs $Rs,$Rd */
10014 {
10015   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10016   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10017 #define FLD(f) abuf->fields.sfmt_muls_b.f
10018   int UNUSED written = 0;
10019   IADDR UNUSED pc = abuf->addr;
10020   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10021
10022 {
10023   SI tmp_tmpd;
10024   tmp_tmpd = ABSSI (GET_H_GR (FLD (f_operand1)));
10025   {
10026     SI opval = tmp_tmpd;
10027     SET_H_GR (FLD (f_operand2), opval);
10028     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10029   }
10030 {
10031   {
10032     BI opval = LTSI (tmp_tmpd, 0);
10033     CPU (h_nbit) = opval;
10034     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10035   }
10036   {
10037     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10038     CPU (h_zbit) = opval;
10039     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10040   }
10041 SET_H_CBIT_MOVE (0);
10042 SET_H_VBIT_MOVE (0);
10043 {
10044   {
10045     BI opval = 0;
10046     CPU (h_xbit) = opval;
10047     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10048   }
10049   {
10050     BI opval = 0;
10051     SET_H_INSN_PREFIXED_P (opval);
10052     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10053   }
10054 }
10055 }
10056 }
10057
10058 #undef FLD
10059 }
10060   NEXT (vpc);
10061
10062   CASE (sem, INSN_AND_B_R) : /* and.b $Rs,$Rd */
10063 {
10064   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10065   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10066 #define FLD(f) abuf->fields.sfmt_addc_m.f
10067   int UNUSED written = 0;
10068   IADDR UNUSED pc = abuf->addr;
10069   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10070
10071 {
10072   QI tmp_tmpd;
10073   tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10074 {
10075   SI tmp_oldregval;
10076   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
10077   {
10078     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10079     SET_H_GR (FLD (f_operand2), opval);
10080     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10081   }
10082 }
10083 {
10084   {
10085     BI opval = LTQI (tmp_tmpd, 0);
10086     CPU (h_nbit) = opval;
10087     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10088   }
10089   {
10090     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10091     CPU (h_zbit) = opval;
10092     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10093   }
10094 SET_H_CBIT_MOVE (0);
10095 SET_H_VBIT_MOVE (0);
10096 {
10097   {
10098     BI opval = 0;
10099     CPU (h_xbit) = opval;
10100     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10101   }
10102   {
10103     BI opval = 0;
10104     SET_H_INSN_PREFIXED_P (opval);
10105     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10106   }
10107 }
10108 }
10109 }
10110
10111 #undef FLD
10112 }
10113   NEXT (vpc);
10114
10115   CASE (sem, INSN_AND_W_R) : /* and.w $Rs,$Rd */
10116 {
10117   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10118   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10119 #define FLD(f) abuf->fields.sfmt_addc_m.f
10120   int UNUSED written = 0;
10121   IADDR UNUSED pc = abuf->addr;
10122   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10123
10124 {
10125   HI tmp_tmpd;
10126   tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10127 {
10128   SI tmp_oldregval;
10129   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
10130   {
10131     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10132     SET_H_GR (FLD (f_operand2), opval);
10133     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10134   }
10135 }
10136 {
10137   {
10138     BI opval = LTHI (tmp_tmpd, 0);
10139     CPU (h_nbit) = opval;
10140     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10141   }
10142   {
10143     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10144     CPU (h_zbit) = opval;
10145     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10146   }
10147 SET_H_CBIT_MOVE (0);
10148 SET_H_VBIT_MOVE (0);
10149 {
10150   {
10151     BI opval = 0;
10152     CPU (h_xbit) = opval;
10153     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10154   }
10155   {
10156     BI opval = 0;
10157     SET_H_INSN_PREFIXED_P (opval);
10158     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10159   }
10160 }
10161 }
10162 }
10163
10164 #undef FLD
10165 }
10166   NEXT (vpc);
10167
10168   CASE (sem, INSN_AND_D_R) : /* and.d $Rs,$Rd */
10169 {
10170   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10171   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10172 #define FLD(f) abuf->fields.sfmt_addc_m.f
10173   int UNUSED written = 0;
10174   IADDR UNUSED pc = abuf->addr;
10175   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10176
10177 {
10178   SI tmp_tmpd;
10179   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10180   {
10181     SI opval = tmp_tmpd;
10182     SET_H_GR (FLD (f_operand2), opval);
10183     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10184   }
10185 {
10186   {
10187     BI opval = LTSI (tmp_tmpd, 0);
10188     CPU (h_nbit) = opval;
10189     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10190   }
10191   {
10192     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10193     CPU (h_zbit) = opval;
10194     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10195   }
10196 SET_H_CBIT_MOVE (0);
10197 SET_H_VBIT_MOVE (0);
10198 {
10199   {
10200     BI opval = 0;
10201     CPU (h_xbit) = opval;
10202     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10203   }
10204   {
10205     BI opval = 0;
10206     SET_H_INSN_PREFIXED_P (opval);
10207     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10208   }
10209 }
10210 }
10211 }
10212
10213 #undef FLD
10214 }
10215   NEXT (vpc);
10216
10217   CASE (sem, INSN_AND_M_B_M) : /* and-m.b [${Rs}${inc}],${Rd} */
10218 {
10219   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10220   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10221 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10222   int UNUSED written = 0;
10223   IADDR UNUSED pc = abuf->addr;
10224   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10225
10226 {
10227   QI tmp_tmpd;
10228   tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10229   QI tmp_tmp_mem;
10230   BI tmp_postinc;
10231   tmp_postinc = FLD (f_memmode);
10232 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
10233 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
10234 ; if (NEBI (tmp_postinc, 0)) {
10235 {
10236 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10237   tmp_addr = ADDSI (tmp_addr, 1);
10238 }
10239   {
10240     SI opval = tmp_addr;
10241     SET_H_GR (FLD (f_operand1), opval);
10242     written |= (1 << 11);
10243     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10244   }
10245 }
10246 }
10247 ; tmp_tmp_mem; }));
10248 {
10249   SI tmp_oldregval;
10250   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
10251   {
10252     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10253     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10254     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10255   }
10256 }
10257 {
10258   {
10259     BI opval = LTQI (tmp_tmpd, 0);
10260     CPU (h_nbit) = opval;
10261     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10262   }
10263   {
10264     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10265     CPU (h_zbit) = opval;
10266     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10267   }
10268 SET_H_CBIT_MOVE (0);
10269 SET_H_VBIT_MOVE (0);
10270 {
10271   {
10272     BI opval = 0;
10273     CPU (h_xbit) = opval;
10274     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10275   }
10276   {
10277     BI opval = 0;
10278     SET_H_INSN_PREFIXED_P (opval);
10279     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10280   }
10281 }
10282 }
10283 }
10284
10285   abuf->written = written;
10286 #undef FLD
10287 }
10288   NEXT (vpc);
10289
10290   CASE (sem, INSN_AND_M_W_M) : /* and-m.w [${Rs}${inc}],${Rd} */
10291 {
10292   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10293   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10294 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10295   int UNUSED written = 0;
10296   IADDR UNUSED pc = abuf->addr;
10297   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10298
10299 {
10300   HI tmp_tmpd;
10301   tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10302   HI tmp_tmp_mem;
10303   BI tmp_postinc;
10304   tmp_postinc = FLD (f_memmode);
10305 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
10306 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
10307 ; if (NEBI (tmp_postinc, 0)) {
10308 {
10309 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10310   tmp_addr = ADDSI (tmp_addr, 2);
10311 }
10312   {
10313     SI opval = tmp_addr;
10314     SET_H_GR (FLD (f_operand1), opval);
10315     written |= (1 << 11);
10316     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10317   }
10318 }
10319 }
10320 ; tmp_tmp_mem; }));
10321 {
10322   SI tmp_oldregval;
10323   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
10324   {
10325     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10326     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10327     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10328   }
10329 }
10330 {
10331   {
10332     BI opval = LTHI (tmp_tmpd, 0);
10333     CPU (h_nbit) = opval;
10334     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10335   }
10336   {
10337     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10338     CPU (h_zbit) = opval;
10339     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10340   }
10341 SET_H_CBIT_MOVE (0);
10342 SET_H_VBIT_MOVE (0);
10343 {
10344   {
10345     BI opval = 0;
10346     CPU (h_xbit) = opval;
10347     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10348   }
10349   {
10350     BI opval = 0;
10351     SET_H_INSN_PREFIXED_P (opval);
10352     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10353   }
10354 }
10355 }
10356 }
10357
10358   abuf->written = written;
10359 #undef FLD
10360 }
10361   NEXT (vpc);
10362
10363   CASE (sem, INSN_AND_M_D_M) : /* and-m.d [${Rs}${inc}],${Rd} */
10364 {
10365   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10366   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10367 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10368   int UNUSED written = 0;
10369   IADDR UNUSED pc = abuf->addr;
10370   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10371
10372 {
10373   SI tmp_tmpd;
10374   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10375   SI tmp_tmp_mem;
10376   BI tmp_postinc;
10377   tmp_postinc = FLD (f_memmode);
10378 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
10379 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
10380 ; if (NEBI (tmp_postinc, 0)) {
10381 {
10382 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10383   tmp_addr = ADDSI (tmp_addr, 4);
10384 }
10385   {
10386     SI opval = tmp_addr;
10387     SET_H_GR (FLD (f_operand1), opval);
10388     written |= (1 << 10);
10389     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10390   }
10391 }
10392 }
10393 ; tmp_tmp_mem; }));
10394   {
10395     SI opval = tmp_tmpd;
10396     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10397     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10398   }
10399 {
10400   {
10401     BI opval = LTSI (tmp_tmpd, 0);
10402     CPU (h_nbit) = opval;
10403     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10404   }
10405   {
10406     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10407     CPU (h_zbit) = opval;
10408     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10409   }
10410 SET_H_CBIT_MOVE (0);
10411 SET_H_VBIT_MOVE (0);
10412 {
10413   {
10414     BI opval = 0;
10415     CPU (h_xbit) = opval;
10416     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10417   }
10418   {
10419     BI opval = 0;
10420     SET_H_INSN_PREFIXED_P (opval);
10421     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10422   }
10423 }
10424 }
10425 }
10426
10427   abuf->written = written;
10428 #undef FLD
10429 }
10430   NEXT (vpc);
10431
10432   CASE (sem, INSN_ANDCBR) : /* and.b ${sconst8}],${Rd} */
10433 {
10434   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10435   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10436 #define FLD(f) abuf->fields.sfmt_addcbr.f
10437   int UNUSED written = 0;
10438   IADDR UNUSED pc = abuf->addr;
10439   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
10440
10441 {
10442   QI tmp_tmpd;
10443   tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__byte));
10444 {
10445   SI tmp_oldregval;
10446   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
10447   {
10448     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10449     SET_H_GR (FLD (f_operand2), opval);
10450     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10451   }
10452 }
10453 {
10454   {
10455     BI opval = LTQI (tmp_tmpd, 0);
10456     CPU (h_nbit) = opval;
10457     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10458   }
10459   {
10460     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10461     CPU (h_zbit) = opval;
10462     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10463   }
10464 SET_H_CBIT_MOVE (0);
10465 SET_H_VBIT_MOVE (0);
10466 {
10467   {
10468     BI opval = 0;
10469     CPU (h_xbit) = opval;
10470     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10471   }
10472   {
10473     BI opval = 0;
10474     SET_H_INSN_PREFIXED_P (opval);
10475     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10476   }
10477 }
10478 }
10479 }
10480
10481 #undef FLD
10482 }
10483   NEXT (vpc);
10484
10485   CASE (sem, INSN_ANDCWR) : /* and.w ${sconst16}],${Rd} */
10486 {
10487   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10488   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10489 #define FLD(f) abuf->fields.sfmt_addcwr.f
10490   int UNUSED written = 0;
10491   IADDR UNUSED pc = abuf->addr;
10492   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
10493
10494 {
10495   HI tmp_tmpd;
10496   tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__word));
10497 {
10498   SI tmp_oldregval;
10499   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
10500   {
10501     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10502     SET_H_GR (FLD (f_operand2), opval);
10503     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10504   }
10505 }
10506 {
10507   {
10508     BI opval = LTHI (tmp_tmpd, 0);
10509     CPU (h_nbit) = opval;
10510     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10511   }
10512   {
10513     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10514     CPU (h_zbit) = opval;
10515     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10516   }
10517 SET_H_CBIT_MOVE (0);
10518 SET_H_VBIT_MOVE (0);
10519 {
10520   {
10521     BI opval = 0;
10522     CPU (h_xbit) = opval;
10523     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10524   }
10525   {
10526     BI opval = 0;
10527     SET_H_INSN_PREFIXED_P (opval);
10528     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10529   }
10530 }
10531 }
10532 }
10533
10534 #undef FLD
10535 }
10536   NEXT (vpc);
10537
10538   CASE (sem, INSN_ANDCDR) : /* and.d ${const32}],${Rd} */
10539 {
10540   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10541   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10542 #define FLD(f) abuf->fields.sfmt_addcdr.f
10543   int UNUSED written = 0;
10544   IADDR UNUSED pc = abuf->addr;
10545   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
10546
10547 {
10548   SI tmp_tmpd;
10549   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
10550   {
10551     SI opval = tmp_tmpd;
10552     SET_H_GR (FLD (f_operand2), opval);
10553     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10554   }
10555 {
10556   {
10557     BI opval = LTSI (tmp_tmpd, 0);
10558     CPU (h_nbit) = opval;
10559     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10560   }
10561   {
10562     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10563     CPU (h_zbit) = opval;
10564     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10565   }
10566 SET_H_CBIT_MOVE (0);
10567 SET_H_VBIT_MOVE (0);
10568 {
10569   {
10570     BI opval = 0;
10571     CPU (h_xbit) = opval;
10572     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10573   }
10574   {
10575     BI opval = 0;
10576     SET_H_INSN_PREFIXED_P (opval);
10577     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10578   }
10579 }
10580 }
10581 }
10582
10583 #undef FLD
10584 }
10585   NEXT (vpc);
10586
10587   CASE (sem, INSN_ANDQ) : /* andq $i,$Rd */
10588 {
10589   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10590   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10591 #define FLD(f) abuf->fields.sfmt_andq.f
10592   int UNUSED written = 0;
10593   IADDR UNUSED pc = abuf->addr;
10594   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10595
10596 {
10597   SI tmp_tmpd;
10598   tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), FLD (f_s6));
10599   {
10600     SI opval = tmp_tmpd;
10601     SET_H_GR (FLD (f_operand2), opval);
10602     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10603   }
10604 {
10605   {
10606     BI opval = LTSI (tmp_tmpd, 0);
10607     CPU (h_nbit) = opval;
10608     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10609   }
10610   {
10611     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10612     CPU (h_zbit) = opval;
10613     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10614   }
10615 SET_H_CBIT_MOVE (0);
10616 SET_H_VBIT_MOVE (0);
10617 {
10618   {
10619     BI opval = 0;
10620     CPU (h_xbit) = opval;
10621     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10622   }
10623   {
10624     BI opval = 0;
10625     SET_H_INSN_PREFIXED_P (opval);
10626     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10627   }
10628 }
10629 }
10630 }
10631
10632 #undef FLD
10633 }
10634   NEXT (vpc);
10635
10636   CASE (sem, INSN_ORR_B_R) : /* orr.b $Rs,$Rd */
10637 {
10638   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10639   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10640 #define FLD(f) abuf->fields.sfmt_addc_m.f
10641   int UNUSED written = 0;
10642   IADDR UNUSED pc = abuf->addr;
10643   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10644
10645 {
10646   QI tmp_tmpd;
10647   tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10648 {
10649   SI tmp_oldregval;
10650   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
10651   {
10652     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10653     SET_H_GR (FLD (f_operand2), opval);
10654     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10655   }
10656 }
10657 {
10658   {
10659     BI opval = LTQI (tmp_tmpd, 0);
10660     CPU (h_nbit) = opval;
10661     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10662   }
10663   {
10664     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10665     CPU (h_zbit) = opval;
10666     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10667   }
10668 SET_H_CBIT_MOVE (0);
10669 SET_H_VBIT_MOVE (0);
10670 {
10671   {
10672     BI opval = 0;
10673     CPU (h_xbit) = opval;
10674     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10675   }
10676   {
10677     BI opval = 0;
10678     SET_H_INSN_PREFIXED_P (opval);
10679     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10680   }
10681 }
10682 }
10683 }
10684
10685 #undef FLD
10686 }
10687   NEXT (vpc);
10688
10689   CASE (sem, INSN_ORR_W_R) : /* orr.w $Rs,$Rd */
10690 {
10691   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10692   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10693 #define FLD(f) abuf->fields.sfmt_addc_m.f
10694   int UNUSED written = 0;
10695   IADDR UNUSED pc = abuf->addr;
10696   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10697
10698 {
10699   HI tmp_tmpd;
10700   tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10701 {
10702   SI tmp_oldregval;
10703   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
10704   {
10705     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10706     SET_H_GR (FLD (f_operand2), opval);
10707     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10708   }
10709 }
10710 {
10711   {
10712     BI opval = LTHI (tmp_tmpd, 0);
10713     CPU (h_nbit) = opval;
10714     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10715   }
10716   {
10717     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10718     CPU (h_zbit) = opval;
10719     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10720   }
10721 SET_H_CBIT_MOVE (0);
10722 SET_H_VBIT_MOVE (0);
10723 {
10724   {
10725     BI opval = 0;
10726     CPU (h_xbit) = opval;
10727     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10728   }
10729   {
10730     BI opval = 0;
10731     SET_H_INSN_PREFIXED_P (opval);
10732     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10733   }
10734 }
10735 }
10736 }
10737
10738 #undef FLD
10739 }
10740   NEXT (vpc);
10741
10742   CASE (sem, INSN_ORR_D_R) : /* orr.d $Rs,$Rd */
10743 {
10744   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10745   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10746 #define FLD(f) abuf->fields.sfmt_addc_m.f
10747   int UNUSED written = 0;
10748   IADDR UNUSED pc = abuf->addr;
10749   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10750
10751 {
10752   SI tmp_tmpd;
10753   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
10754   {
10755     SI opval = tmp_tmpd;
10756     SET_H_GR (FLD (f_operand2), opval);
10757     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10758   }
10759 {
10760   {
10761     BI opval = LTSI (tmp_tmpd, 0);
10762     CPU (h_nbit) = opval;
10763     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10764   }
10765   {
10766     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10767     CPU (h_zbit) = opval;
10768     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10769   }
10770 SET_H_CBIT_MOVE (0);
10771 SET_H_VBIT_MOVE (0);
10772 {
10773   {
10774     BI opval = 0;
10775     CPU (h_xbit) = opval;
10776     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10777   }
10778   {
10779     BI opval = 0;
10780     SET_H_INSN_PREFIXED_P (opval);
10781     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10782   }
10783 }
10784 }
10785 }
10786
10787 #undef FLD
10788 }
10789   NEXT (vpc);
10790
10791   CASE (sem, INSN_OR_M_B_M) : /* or-m.b [${Rs}${inc}],${Rd} */
10792 {
10793   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10794   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10795 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10796   int UNUSED written = 0;
10797   IADDR UNUSED pc = abuf->addr;
10798   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10799
10800 {
10801   QI tmp_tmpd;
10802   tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10803   QI tmp_tmp_mem;
10804   BI tmp_postinc;
10805   tmp_postinc = FLD (f_memmode);
10806 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
10807 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
10808 ; if (NEBI (tmp_postinc, 0)) {
10809 {
10810 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10811   tmp_addr = ADDSI (tmp_addr, 1);
10812 }
10813   {
10814     SI opval = tmp_addr;
10815     SET_H_GR (FLD (f_operand1), opval);
10816     written |= (1 << 11);
10817     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10818   }
10819 }
10820 }
10821 ; tmp_tmp_mem; }));
10822 {
10823   SI tmp_oldregval;
10824   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
10825   {
10826     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
10827     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10828     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10829   }
10830 }
10831 {
10832   {
10833     BI opval = LTQI (tmp_tmpd, 0);
10834     CPU (h_nbit) = opval;
10835     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10836   }
10837   {
10838     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10839     CPU (h_zbit) = opval;
10840     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10841   }
10842 SET_H_CBIT_MOVE (0);
10843 SET_H_VBIT_MOVE (0);
10844 {
10845   {
10846     BI opval = 0;
10847     CPU (h_xbit) = opval;
10848     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10849   }
10850   {
10851     BI opval = 0;
10852     SET_H_INSN_PREFIXED_P (opval);
10853     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10854   }
10855 }
10856 }
10857 }
10858
10859   abuf->written = written;
10860 #undef FLD
10861 }
10862   NEXT (vpc);
10863
10864   CASE (sem, INSN_OR_M_W_M) : /* or-m.w [${Rs}${inc}],${Rd} */
10865 {
10866   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10867   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10868 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10869   int UNUSED written = 0;
10870   IADDR UNUSED pc = abuf->addr;
10871   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10872
10873 {
10874   HI tmp_tmpd;
10875   tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10876   HI tmp_tmp_mem;
10877   BI tmp_postinc;
10878   tmp_postinc = FLD (f_memmode);
10879 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
10880 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
10881 ; if (NEBI (tmp_postinc, 0)) {
10882 {
10883 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10884   tmp_addr = ADDSI (tmp_addr, 2);
10885 }
10886   {
10887     SI opval = tmp_addr;
10888     SET_H_GR (FLD (f_operand1), opval);
10889     written |= (1 << 11);
10890     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10891   }
10892 }
10893 }
10894 ; tmp_tmp_mem; }));
10895 {
10896   SI tmp_oldregval;
10897   tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
10898   {
10899     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
10900     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10901     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10902   }
10903 }
10904 {
10905   {
10906     BI opval = LTHI (tmp_tmpd, 0);
10907     CPU (h_nbit) = opval;
10908     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10909   }
10910   {
10911     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10912     CPU (h_zbit) = opval;
10913     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10914   }
10915 SET_H_CBIT_MOVE (0);
10916 SET_H_VBIT_MOVE (0);
10917 {
10918   {
10919     BI opval = 0;
10920     CPU (h_xbit) = opval;
10921     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10922   }
10923   {
10924     BI opval = 0;
10925     SET_H_INSN_PREFIXED_P (opval);
10926     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10927   }
10928 }
10929 }
10930 }
10931
10932   abuf->written = written;
10933 #undef FLD
10934 }
10935   NEXT (vpc);
10936
10937   CASE (sem, INSN_OR_M_D_M) : /* or-m.d [${Rs}${inc}],${Rd} */
10938 {
10939   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
10940   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
10941 #define FLD(f) abuf->fields.sfmt_add_m_b_m.f
10942   int UNUSED written = 0;
10943   IADDR UNUSED pc = abuf->addr;
10944   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
10945
10946 {
10947   SI tmp_tmpd;
10948   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), ({   SI tmp_addr;
10949   SI tmp_tmp_mem;
10950   BI tmp_postinc;
10951   tmp_postinc = FLD (f_memmode);
10952 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
10953 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
10954 ; if (NEBI (tmp_postinc, 0)) {
10955 {
10956 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
10957   tmp_addr = ADDSI (tmp_addr, 4);
10958 }
10959   {
10960     SI opval = tmp_addr;
10961     SET_H_GR (FLD (f_operand1), opval);
10962     written |= (1 << 10);
10963     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10964   }
10965 }
10966 }
10967 ; tmp_tmp_mem; }));
10968   {
10969     SI opval = tmp_tmpd;
10970     SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
10971     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
10972   }
10973 {
10974   {
10975     BI opval = LTSI (tmp_tmpd, 0);
10976     CPU (h_nbit) = opval;
10977     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
10978   }
10979   {
10980     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
10981     CPU (h_zbit) = opval;
10982     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
10983   }
10984 SET_H_CBIT_MOVE (0);
10985 SET_H_VBIT_MOVE (0);
10986 {
10987   {
10988     BI opval = 0;
10989     CPU (h_xbit) = opval;
10990     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
10991   }
10992   {
10993     BI opval = 0;
10994     SET_H_INSN_PREFIXED_P (opval);
10995     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
10996   }
10997 }
10998 }
10999 }
11000
11001   abuf->written = written;
11002 #undef FLD
11003 }
11004   NEXT (vpc);
11005
11006   CASE (sem, INSN_ORCBR) : /* or.b ${sconst8}],${Rd} */
11007 {
11008   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11009   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11010 #define FLD(f) abuf->fields.sfmt_addcbr.f
11011   int UNUSED written = 0;
11012   IADDR UNUSED pc = abuf->addr;
11013   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
11014
11015 {
11016   QI tmp_tmpd;
11017   tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__byte));
11018 {
11019   SI tmp_oldregval;
11020   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
11021   {
11022     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
11023     SET_H_GR (FLD (f_operand2), opval);
11024     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11025   }
11026 }
11027 {
11028   {
11029     BI opval = LTQI (tmp_tmpd, 0);
11030     CPU (h_nbit) = opval;
11031     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11032   }
11033   {
11034     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11035     CPU (h_zbit) = opval;
11036     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11037   }
11038 SET_H_CBIT_MOVE (0);
11039 SET_H_VBIT_MOVE (0);
11040 {
11041   {
11042     BI opval = 0;
11043     CPU (h_xbit) = opval;
11044     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11045   }
11046   {
11047     BI opval = 0;
11048     SET_H_INSN_PREFIXED_P (opval);
11049     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11050   }
11051 }
11052 }
11053 }
11054
11055 #undef FLD
11056 }
11057   NEXT (vpc);
11058
11059   CASE (sem, INSN_ORCWR) : /* or.w ${sconst16}],${Rd} */
11060 {
11061   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11062   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11063 #define FLD(f) abuf->fields.sfmt_addcwr.f
11064   int UNUSED written = 0;
11065   IADDR UNUSED pc = abuf->addr;
11066   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
11067
11068 {
11069   HI tmp_tmpd;
11070   tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__word));
11071 {
11072   SI tmp_oldregval;
11073   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
11074   {
11075     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
11076     SET_H_GR (FLD (f_operand2), opval);
11077     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11078   }
11079 }
11080 {
11081   {
11082     BI opval = LTHI (tmp_tmpd, 0);
11083     CPU (h_nbit) = opval;
11084     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11085   }
11086   {
11087     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11088     CPU (h_zbit) = opval;
11089     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11090   }
11091 SET_H_CBIT_MOVE (0);
11092 SET_H_VBIT_MOVE (0);
11093 {
11094   {
11095     BI opval = 0;
11096     CPU (h_xbit) = opval;
11097     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11098   }
11099   {
11100     BI opval = 0;
11101     SET_H_INSN_PREFIXED_P (opval);
11102     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11103   }
11104 }
11105 }
11106 }
11107
11108 #undef FLD
11109 }
11110   NEXT (vpc);
11111
11112   CASE (sem, INSN_ORCDR) : /* or.d ${const32}],${Rd} */
11113 {
11114   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11115   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11116 #define FLD(f) abuf->fields.sfmt_addcdr.f
11117   int UNUSED written = 0;
11118   IADDR UNUSED pc = abuf->addr;
11119   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
11120
11121 {
11122   SI tmp_tmpd;
11123   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
11124   {
11125     SI opval = tmp_tmpd;
11126     SET_H_GR (FLD (f_operand2), opval);
11127     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11128   }
11129 {
11130   {
11131     BI opval = LTSI (tmp_tmpd, 0);
11132     CPU (h_nbit) = opval;
11133     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11134   }
11135   {
11136     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11137     CPU (h_zbit) = opval;
11138     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11139   }
11140 SET_H_CBIT_MOVE (0);
11141 SET_H_VBIT_MOVE (0);
11142 {
11143   {
11144     BI opval = 0;
11145     CPU (h_xbit) = opval;
11146     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11147   }
11148   {
11149     BI opval = 0;
11150     SET_H_INSN_PREFIXED_P (opval);
11151     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11152   }
11153 }
11154 }
11155 }
11156
11157 #undef FLD
11158 }
11159   NEXT (vpc);
11160
11161   CASE (sem, INSN_ORQ) : /* orq $i,$Rd */
11162 {
11163   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11164   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11165 #define FLD(f) abuf->fields.sfmt_andq.f
11166   int UNUSED written = 0;
11167   IADDR UNUSED pc = abuf->addr;
11168   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11169
11170 {
11171   SI tmp_tmpd;
11172   tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), FLD (f_s6));
11173   {
11174     SI opval = tmp_tmpd;
11175     SET_H_GR (FLD (f_operand2), opval);
11176     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11177   }
11178 {
11179   {
11180     BI opval = LTSI (tmp_tmpd, 0);
11181     CPU (h_nbit) = opval;
11182     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11183   }
11184   {
11185     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11186     CPU (h_zbit) = opval;
11187     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11188   }
11189 SET_H_CBIT_MOVE (0);
11190 SET_H_VBIT_MOVE (0);
11191 {
11192   {
11193     BI opval = 0;
11194     CPU (h_xbit) = opval;
11195     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11196   }
11197   {
11198     BI opval = 0;
11199     SET_H_INSN_PREFIXED_P (opval);
11200     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11201   }
11202 }
11203 }
11204 }
11205
11206 #undef FLD
11207 }
11208   NEXT (vpc);
11209
11210   CASE (sem, INSN_XOR) : /* xor $Rs,$Rd */
11211 {
11212   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11213   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11214 #define FLD(f) abuf->fields.sfmt_muls_b.f
11215   int UNUSED written = 0;
11216   IADDR UNUSED pc = abuf->addr;
11217   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11218
11219 {
11220   SI tmp_tmpd;
11221   tmp_tmpd = XORSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
11222   {
11223     SI opval = tmp_tmpd;
11224     SET_H_GR (FLD (f_operand2), opval);
11225     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11226   }
11227 {
11228   {
11229     BI opval = LTSI (tmp_tmpd, 0);
11230     CPU (h_nbit) = opval;
11231     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11232   }
11233   {
11234     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11235     CPU (h_zbit) = opval;
11236     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11237   }
11238 SET_H_CBIT_MOVE (0);
11239 SET_H_VBIT_MOVE (0);
11240 {
11241   {
11242     BI opval = 0;
11243     CPU (h_xbit) = opval;
11244     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11245   }
11246   {
11247     BI opval = 0;
11248     SET_H_INSN_PREFIXED_P (opval);
11249     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11250   }
11251 }
11252 }
11253 }
11254
11255 #undef FLD
11256 }
11257   NEXT (vpc);
11258
11259   CASE (sem, INSN_SWAP) : /* swap${swapoption} ${Rs} */
11260 {
11261   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11262   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11263 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
11264   int UNUSED written = 0;
11265   IADDR UNUSED pc = abuf->addr;
11266   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11267
11268 {
11269   SI tmp_tmps;
11270   SI tmp_tmpd;
11271   tmp_tmps = GET_H_GR (FLD (f_operand1));
11272   tmp_tmpd = ({   SI tmp_tmpcode;
11273   SI tmp_tmpval;
11274   SI tmp_tmpres;
11275   tmp_tmpcode = FLD (f_operand2);
11276 ;   tmp_tmpval = tmp_tmps;
11277 ; if (EQSI (tmp_tmpcode, 0)) {
11278   tmp_tmpres = (cgen_rtx_error (current_cpu, "SWAP without swap modifier isn't implemented"), 0);
11279 }
11280  else if (EQSI (tmp_tmpcode, 1)) {
11281   tmp_tmpres = ({   SI tmp_tmpr;
11282   tmp_tmpr = tmp_tmpval;
11283 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11284 }
11285  else if (EQSI (tmp_tmpcode, 2)) {
11286   tmp_tmpres = ({   SI tmp_tmpb;
11287   tmp_tmpb = tmp_tmpval;
11288 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11289 }
11290  else if (EQSI (tmp_tmpcode, 3)) {
11291   tmp_tmpres = ({   SI tmp_tmpr;
11292   tmp_tmpr = ({   SI tmp_tmpb;
11293   tmp_tmpb = tmp_tmpval;
11294 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11295 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11296 }
11297  else if (EQSI (tmp_tmpcode, 4)) {
11298   tmp_tmpres = ({   SI tmp_tmpb;
11299   tmp_tmpb = tmp_tmpval;
11300 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11301 }
11302  else if (EQSI (tmp_tmpcode, 5)) {
11303   tmp_tmpres = ({   SI tmp_tmpr;
11304   tmp_tmpr = ({   SI tmp_tmpb;
11305   tmp_tmpb = tmp_tmpval;
11306 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11307 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11308 }
11309  else if (EQSI (tmp_tmpcode, 6)) {
11310   tmp_tmpres = ({   SI tmp_tmpb;
11311   tmp_tmpb = ({   SI tmp_tmpb;
11312   tmp_tmpb = tmp_tmpval;
11313 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11314 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11315 }
11316  else if (EQSI (tmp_tmpcode, 7)) {
11317   tmp_tmpres = ({   SI tmp_tmpr;
11318   tmp_tmpr = ({   SI tmp_tmpb;
11319   tmp_tmpb = ({   SI tmp_tmpb;
11320   tmp_tmpb = tmp_tmpval;
11321 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11322 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11323 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11324 }
11325  else if (EQSI (tmp_tmpcode, 8)) {
11326   tmp_tmpres = INVSI (tmp_tmpval);
11327 }
11328  else if (EQSI (tmp_tmpcode, 9)) {
11329   tmp_tmpres = ({   SI tmp_tmpr;
11330   tmp_tmpr = INVSI (tmp_tmpval);
11331 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11332 }
11333  else if (EQSI (tmp_tmpcode, 10)) {
11334   tmp_tmpres = ({   SI tmp_tmpb;
11335   tmp_tmpb = INVSI (tmp_tmpval);
11336 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11337 }
11338  else if (EQSI (tmp_tmpcode, 11)) {
11339   tmp_tmpres = ({   SI tmp_tmpr;
11340   tmp_tmpr = ({   SI tmp_tmpb;
11341   tmp_tmpb = INVSI (tmp_tmpval);
11342 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11343 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11344 }
11345  else if (EQSI (tmp_tmpcode, 12)) {
11346   tmp_tmpres = ({   SI tmp_tmpb;
11347   tmp_tmpb = INVSI (tmp_tmpval);
11348 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11349 }
11350  else if (EQSI (tmp_tmpcode, 13)) {
11351   tmp_tmpres = ({   SI tmp_tmpr;
11352   tmp_tmpr = ({   SI tmp_tmpb;
11353   tmp_tmpb = INVSI (tmp_tmpval);
11354 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11355 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11356 }
11357  else if (EQSI (tmp_tmpcode, 14)) {
11358   tmp_tmpres = ({   SI tmp_tmpb;
11359   tmp_tmpb = ({   SI tmp_tmpb;
11360   tmp_tmpb = INVSI (tmp_tmpval);
11361 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11362 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11363 }
11364  else if (EQSI (tmp_tmpcode, 15)) {
11365   tmp_tmpres = ({   SI tmp_tmpr;
11366   tmp_tmpr = ({   SI tmp_tmpb;
11367   tmp_tmpb = ({   SI tmp_tmpb;
11368   tmp_tmpb = INVSI (tmp_tmpval);
11369 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
11370 ; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
11371 ; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
11372 }
11373 ; tmp_tmpres; });
11374   {
11375     SI opval = tmp_tmpd;
11376     SET_H_GR (FLD (f_operand1), opval);
11377     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11378   }
11379 {
11380   {
11381     BI opval = LTSI (tmp_tmpd, 0);
11382     CPU (h_nbit) = opval;
11383     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11384   }
11385   {
11386     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11387     CPU (h_zbit) = opval;
11388     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11389   }
11390 SET_H_CBIT_MOVE (0);
11391 SET_H_VBIT_MOVE (0);
11392 {
11393   {
11394     BI opval = 0;
11395     CPU (h_xbit) = opval;
11396     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11397   }
11398   {
11399     BI opval = 0;
11400     SET_H_INSN_PREFIXED_P (opval);
11401     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11402   }
11403 }
11404 }
11405 }
11406
11407 #undef FLD
11408 }
11409   NEXT (vpc);
11410
11411   CASE (sem, INSN_ASRR_B_R) : /* asrr.b $Rs,$Rd */
11412 {
11413   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11414   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11415 #define FLD(f) abuf->fields.sfmt_addc_m.f
11416   int UNUSED written = 0;
11417   IADDR UNUSED pc = abuf->addr;
11418   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11419
11420 {
11421   QI tmp_tmpd;
11422   SI tmp_cnt1;
11423   SI tmp_cnt2;
11424   tmp_cnt1 = GET_H_GR (FLD (f_operand1));
11425   tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
11426   tmp_tmpd = SRASI (EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
11427 {
11428   SI tmp_oldregval;
11429   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
11430   {
11431     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
11432     SET_H_GR (FLD (f_operand2), opval);
11433     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11434   }
11435 }
11436 {
11437   {
11438     BI opval = LTQI (tmp_tmpd, 0);
11439     CPU (h_nbit) = opval;
11440     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11441   }
11442   {
11443     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11444     CPU (h_zbit) = opval;
11445     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11446   }
11447 SET_H_CBIT_MOVE (0);
11448 SET_H_VBIT_MOVE (0);
11449 {
11450   {
11451     BI opval = 0;
11452     CPU (h_xbit) = opval;
11453     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11454   }
11455   {
11456     BI opval = 0;
11457     SET_H_INSN_PREFIXED_P (opval);
11458     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11459   }
11460 }
11461 }
11462 }
11463
11464 #undef FLD
11465 }
11466   NEXT (vpc);
11467
11468   CASE (sem, INSN_ASRR_W_R) : /* asrr.w $Rs,$Rd */
11469 {
11470   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11471   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11472 #define FLD(f) abuf->fields.sfmt_addc_m.f
11473   int UNUSED written = 0;
11474   IADDR UNUSED pc = abuf->addr;
11475   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11476
11477 {
11478   HI tmp_tmpd;
11479   SI tmp_cnt1;
11480   SI tmp_cnt2;
11481   tmp_cnt1 = GET_H_GR (FLD (f_operand1));
11482   tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
11483   tmp_tmpd = SRASI (EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
11484 {
11485   SI tmp_oldregval;
11486   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
11487   {
11488     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
11489     SET_H_GR (FLD (f_operand2), opval);
11490     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11491   }
11492 }
11493 {
11494   {
11495     BI opval = LTHI (tmp_tmpd, 0);
11496     CPU (h_nbit) = opval;
11497     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11498   }
11499   {
11500     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11501     CPU (h_zbit) = opval;
11502     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11503   }
11504 SET_H_CBIT_MOVE (0);
11505 SET_H_VBIT_MOVE (0);
11506 {
11507   {
11508     BI opval = 0;
11509     CPU (h_xbit) = opval;
11510     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11511   }
11512   {
11513     BI opval = 0;
11514     SET_H_INSN_PREFIXED_P (opval);
11515     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11516   }
11517 }
11518 }
11519 }
11520
11521 #undef FLD
11522 }
11523   NEXT (vpc);
11524
11525   CASE (sem, INSN_ASRR_D_R) : /* asrr.d $Rs,$Rd */
11526 {
11527   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11528   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11529 #define FLD(f) abuf->fields.sfmt_addc_m.f
11530   int UNUSED written = 0;
11531   IADDR UNUSED pc = abuf->addr;
11532   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11533
11534 {
11535   SI tmp_tmpd;
11536   SI tmp_cnt1;
11537   SI tmp_cnt2;
11538   tmp_cnt1 = GET_H_GR (FLD (f_operand1));
11539   tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
11540   tmp_tmpd = SRASI (EXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
11541   {
11542     SI opval = tmp_tmpd;
11543     SET_H_GR (FLD (f_operand2), opval);
11544     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11545   }
11546 {
11547   {
11548     BI opval = LTSI (tmp_tmpd, 0);
11549     CPU (h_nbit) = opval;
11550     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11551   }
11552   {
11553     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11554     CPU (h_zbit) = opval;
11555     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11556   }
11557 SET_H_CBIT_MOVE (0);
11558 SET_H_VBIT_MOVE (0);
11559 {
11560   {
11561     BI opval = 0;
11562     CPU (h_xbit) = opval;
11563     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11564   }
11565   {
11566     BI opval = 0;
11567     SET_H_INSN_PREFIXED_P (opval);
11568     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11569   }
11570 }
11571 }
11572 }
11573
11574 #undef FLD
11575 }
11576   NEXT (vpc);
11577
11578   CASE (sem, INSN_ASRQ) : /* asrq $c,${Rd} */
11579 {
11580   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11581   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11582 #define FLD(f) abuf->fields.sfmt_asrq.f
11583   int UNUSED written = 0;
11584   IADDR UNUSED pc = abuf->addr;
11585   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11586
11587 {
11588   SI tmp_tmpd;
11589   tmp_tmpd = SRASI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
11590   {
11591     SI opval = tmp_tmpd;
11592     SET_H_GR (FLD (f_operand2), opval);
11593     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11594   }
11595 {
11596   {
11597     BI opval = LTSI (tmp_tmpd, 0);
11598     CPU (h_nbit) = opval;
11599     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11600   }
11601   {
11602     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11603     CPU (h_zbit) = opval;
11604     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11605   }
11606 SET_H_CBIT_MOVE (0);
11607 SET_H_VBIT_MOVE (0);
11608 {
11609   {
11610     BI opval = 0;
11611     CPU (h_xbit) = opval;
11612     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11613   }
11614   {
11615     BI opval = 0;
11616     SET_H_INSN_PREFIXED_P (opval);
11617     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11618   }
11619 }
11620 }
11621 }
11622
11623 #undef FLD
11624 }
11625   NEXT (vpc);
11626
11627   CASE (sem, INSN_LSRR_B_R) : /* lsrr.b $Rs,$Rd */
11628 {
11629   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11630   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11631 #define FLD(f) abuf->fields.sfmt_addc_m.f
11632   int UNUSED written = 0;
11633   IADDR UNUSED pc = abuf->addr;
11634   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11635
11636 {
11637   SI tmp_tmpd;
11638   SI tmp_cnt;
11639   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11640   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11641 {
11642   SI tmp_oldregval;
11643   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
11644   {
11645     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
11646     SET_H_GR (FLD (f_operand2), opval);
11647     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11648   }
11649 }
11650 {
11651   {
11652     BI opval = LTQI (tmp_tmpd, 0);
11653     CPU (h_nbit) = opval;
11654     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11655   }
11656   {
11657     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11658     CPU (h_zbit) = opval;
11659     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11660   }
11661 SET_H_CBIT_MOVE (0);
11662 SET_H_VBIT_MOVE (0);
11663 {
11664   {
11665     BI opval = 0;
11666     CPU (h_xbit) = opval;
11667     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11668   }
11669   {
11670     BI opval = 0;
11671     SET_H_INSN_PREFIXED_P (opval);
11672     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11673   }
11674 }
11675 }
11676 }
11677
11678 #undef FLD
11679 }
11680   NEXT (vpc);
11681
11682   CASE (sem, INSN_LSRR_W_R) : /* lsrr.w $Rs,$Rd */
11683 {
11684   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11685   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11686 #define FLD(f) abuf->fields.sfmt_addc_m.f
11687   int UNUSED written = 0;
11688   IADDR UNUSED pc = abuf->addr;
11689   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11690
11691 {
11692   SI tmp_tmpd;
11693   SI tmp_cnt;
11694   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11695   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11696 {
11697   SI tmp_oldregval;
11698   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
11699   {
11700     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
11701     SET_H_GR (FLD (f_operand2), opval);
11702     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11703   }
11704 }
11705 {
11706   {
11707     BI opval = LTHI (tmp_tmpd, 0);
11708     CPU (h_nbit) = opval;
11709     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11710   }
11711   {
11712     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11713     CPU (h_zbit) = opval;
11714     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11715   }
11716 SET_H_CBIT_MOVE (0);
11717 SET_H_VBIT_MOVE (0);
11718 {
11719   {
11720     BI opval = 0;
11721     CPU (h_xbit) = opval;
11722     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11723   }
11724   {
11725     BI opval = 0;
11726     SET_H_INSN_PREFIXED_P (opval);
11727     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11728   }
11729 }
11730 }
11731 }
11732
11733 #undef FLD
11734 }
11735   NEXT (vpc);
11736
11737   CASE (sem, INSN_LSRR_D_R) : /* lsrr.d $Rs,$Rd */
11738 {
11739   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11740   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11741 #define FLD(f) abuf->fields.sfmt_addc_m.f
11742   int UNUSED written = 0;
11743   IADDR UNUSED pc = abuf->addr;
11744   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11745
11746 {
11747   SI tmp_tmpd;
11748   SI tmp_cnt;
11749   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11750   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11751   {
11752     SI opval = tmp_tmpd;
11753     SET_H_GR (FLD (f_operand2), opval);
11754     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11755   }
11756 {
11757   {
11758     BI opval = LTSI (tmp_tmpd, 0);
11759     CPU (h_nbit) = opval;
11760     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11761   }
11762   {
11763     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11764     CPU (h_zbit) = opval;
11765     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11766   }
11767 SET_H_CBIT_MOVE (0);
11768 SET_H_VBIT_MOVE (0);
11769 {
11770   {
11771     BI opval = 0;
11772     CPU (h_xbit) = opval;
11773     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11774   }
11775   {
11776     BI opval = 0;
11777     SET_H_INSN_PREFIXED_P (opval);
11778     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11779   }
11780 }
11781 }
11782 }
11783
11784 #undef FLD
11785 }
11786   NEXT (vpc);
11787
11788   CASE (sem, INSN_LSRQ) : /* lsrq $c,${Rd} */
11789 {
11790   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11791   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11792 #define FLD(f) abuf->fields.sfmt_asrq.f
11793   int UNUSED written = 0;
11794   IADDR UNUSED pc = abuf->addr;
11795   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11796
11797 {
11798   SI tmp_tmpd;
11799   tmp_tmpd = SRLSI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
11800   {
11801     SI opval = tmp_tmpd;
11802     SET_H_GR (FLD (f_operand2), opval);
11803     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11804   }
11805 {
11806   {
11807     BI opval = LTSI (tmp_tmpd, 0);
11808     CPU (h_nbit) = opval;
11809     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11810   }
11811   {
11812     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11813     CPU (h_zbit) = opval;
11814     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11815   }
11816 SET_H_CBIT_MOVE (0);
11817 SET_H_VBIT_MOVE (0);
11818 {
11819   {
11820     BI opval = 0;
11821     CPU (h_xbit) = opval;
11822     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11823   }
11824   {
11825     BI opval = 0;
11826     SET_H_INSN_PREFIXED_P (opval);
11827     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11828   }
11829 }
11830 }
11831 }
11832
11833 #undef FLD
11834 }
11835   NEXT (vpc);
11836
11837   CASE (sem, INSN_LSLR_B_R) : /* lslr.b $Rs,$Rd */
11838 {
11839   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11840   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11841 #define FLD(f) abuf->fields.sfmt_addc_m.f
11842   int UNUSED written = 0;
11843   IADDR UNUSED pc = abuf->addr;
11844   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11845
11846 {
11847   SI tmp_tmpd;
11848   SI tmp_cnt;
11849   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11850   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11851 {
11852   SI tmp_oldregval;
11853   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
11854   {
11855     SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
11856     SET_H_GR (FLD (f_operand2), opval);
11857     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11858   }
11859 }
11860 {
11861   {
11862     BI opval = LTQI (tmp_tmpd, 0);
11863     CPU (h_nbit) = opval;
11864     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11865   }
11866   {
11867     BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11868     CPU (h_zbit) = opval;
11869     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11870   }
11871 SET_H_CBIT_MOVE (0);
11872 SET_H_VBIT_MOVE (0);
11873 {
11874   {
11875     BI opval = 0;
11876     CPU (h_xbit) = opval;
11877     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11878   }
11879   {
11880     BI opval = 0;
11881     SET_H_INSN_PREFIXED_P (opval);
11882     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11883   }
11884 }
11885 }
11886 }
11887
11888 #undef FLD
11889 }
11890   NEXT (vpc);
11891
11892   CASE (sem, INSN_LSLR_W_R) : /* lslr.w $Rs,$Rd */
11893 {
11894   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11895   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11896 #define FLD(f) abuf->fields.sfmt_addc_m.f
11897   int UNUSED written = 0;
11898   IADDR UNUSED pc = abuf->addr;
11899   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11900
11901 {
11902   SI tmp_tmpd;
11903   SI tmp_cnt;
11904   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11905   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11906 {
11907   SI tmp_oldregval;
11908   tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
11909   {
11910     SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
11911     SET_H_GR (FLD (f_operand2), opval);
11912     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11913   }
11914 }
11915 {
11916   {
11917     BI opval = LTHI (tmp_tmpd, 0);
11918     CPU (h_nbit) = opval;
11919     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11920   }
11921   {
11922     BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11923     CPU (h_zbit) = opval;
11924     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11925   }
11926 SET_H_CBIT_MOVE (0);
11927 SET_H_VBIT_MOVE (0);
11928 {
11929   {
11930     BI opval = 0;
11931     CPU (h_xbit) = opval;
11932     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11933   }
11934   {
11935     BI opval = 0;
11936     SET_H_INSN_PREFIXED_P (opval);
11937     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11938   }
11939 }
11940 }
11941 }
11942
11943 #undef FLD
11944 }
11945   NEXT (vpc);
11946
11947   CASE (sem, INSN_LSLR_D_R) : /* lslr.d $Rs,$Rd */
11948 {
11949   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
11950   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
11951 #define FLD(f) abuf->fields.sfmt_addc_m.f
11952   int UNUSED written = 0;
11953   IADDR UNUSED pc = abuf->addr;
11954   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
11955
11956 {
11957   SI tmp_tmpd;
11958   SI tmp_cnt;
11959   tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
11960   tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
11961   {
11962     SI opval = tmp_tmpd;
11963     SET_H_GR (FLD (f_operand2), opval);
11964     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
11965   }
11966 {
11967   {
11968     BI opval = LTSI (tmp_tmpd, 0);
11969     CPU (h_nbit) = opval;
11970     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
11971   }
11972   {
11973     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
11974     CPU (h_zbit) = opval;
11975     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
11976   }
11977 SET_H_CBIT_MOVE (0);
11978 SET_H_VBIT_MOVE (0);
11979 {
11980   {
11981     BI opval = 0;
11982     CPU (h_xbit) = opval;
11983     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
11984   }
11985   {
11986     BI opval = 0;
11987     SET_H_INSN_PREFIXED_P (opval);
11988     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
11989   }
11990 }
11991 }
11992 }
11993
11994 #undef FLD
11995 }
11996   NEXT (vpc);
11997
11998   CASE (sem, INSN_LSLQ) : /* lslq $c,${Rd} */
11999 {
12000   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12001   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12002 #define FLD(f) abuf->fields.sfmt_asrq.f
12003   int UNUSED written = 0;
12004   IADDR UNUSED pc = abuf->addr;
12005   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12006
12007 {
12008   SI tmp_tmpd;
12009   tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
12010   {
12011     SI opval = tmp_tmpd;
12012     SET_H_GR (FLD (f_operand2), opval);
12013     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
12014   }
12015 {
12016   {
12017     BI opval = LTSI (tmp_tmpd, 0);
12018     CPU (h_nbit) = opval;
12019     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12020   }
12021   {
12022     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12023     CPU (h_zbit) = opval;
12024     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12025   }
12026 SET_H_CBIT_MOVE (0);
12027 SET_H_VBIT_MOVE (0);
12028 {
12029   {
12030     BI opval = 0;
12031     CPU (h_xbit) = opval;
12032     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12033   }
12034   {
12035     BI opval = 0;
12036     SET_H_INSN_PREFIXED_P (opval);
12037     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12038   }
12039 }
12040 }
12041 }
12042
12043 #undef FLD
12044 }
12045   NEXT (vpc);
12046
12047   CASE (sem, INSN_BTST) : /* $Rs,$Rd */
12048 {
12049   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12050   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12051 #define FLD(f) abuf->fields.sfmt_muls_b.f
12052   int UNUSED written = 0;
12053   IADDR UNUSED pc = abuf->addr;
12054   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12055
12056 {
12057   SI tmp_tmpd;
12058   SI tmp_cnt;
12059   tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), SUBSI (31, ANDSI (GET_H_GR (FLD (f_operand1)), 31)));
12060 {
12061   {
12062     BI opval = LTSI (tmp_tmpd, 0);
12063     CPU (h_nbit) = opval;
12064     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12065   }
12066   {
12067     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12068     CPU (h_zbit) = opval;
12069     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12070   }
12071 SET_H_CBIT_MOVE (0);
12072 SET_H_VBIT_MOVE (0);
12073 {
12074   {
12075     BI opval = 0;
12076     CPU (h_xbit) = opval;
12077     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12078   }
12079   {
12080     BI opval = 0;
12081     SET_H_INSN_PREFIXED_P (opval);
12082     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12083   }
12084 }
12085 }
12086 }
12087
12088 #undef FLD
12089 }
12090   NEXT (vpc);
12091
12092   CASE (sem, INSN_BTSTQ) : /* btstq $c,${Rd} */
12093 {
12094   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12095   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12096 #define FLD(f) abuf->fields.sfmt_asrq.f
12097   int UNUSED written = 0;
12098   IADDR UNUSED pc = abuf->addr;
12099   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12100
12101 {
12102   SI tmp_tmpd;
12103   tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), SUBSI (31, FLD (f_u5)));
12104 {
12105   {
12106     BI opval = LTSI (tmp_tmpd, 0);
12107     CPU (h_nbit) = opval;
12108     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12109   }
12110   {
12111     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
12112     CPU (h_zbit) = opval;
12113     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12114   }
12115 SET_H_CBIT_MOVE (0);
12116 SET_H_VBIT_MOVE (0);
12117 {
12118   {
12119     BI opval = 0;
12120     CPU (h_xbit) = opval;
12121     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12122   }
12123   {
12124     BI opval = 0;
12125     SET_H_INSN_PREFIXED_P (opval);
12126     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12127   }
12128 }
12129 }
12130 }
12131
12132 #undef FLD
12133 }
12134   NEXT (vpc);
12135
12136   CASE (sem, INSN_SETF) : /* setf ${list-of-flags} */
12137 {
12138   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12139   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12140 #define FLD(f) abuf->fields.sfmt_setf.f
12141   int UNUSED written = 0;
12142   IADDR UNUSED pc = abuf->addr;
12143   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12144
12145 {
12146   SI tmp_tmp;
12147   tmp_tmp = FLD (f_dstsrc);
12148 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 0)), 0)) {
12149   {
12150     BI opval = 1;
12151     CPU (h_cbit) = opval;
12152     written |= (1 << 1);
12153     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
12154   }
12155 }
12156 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 1)), 0)) {
12157   {
12158     BI opval = 1;
12159     CPU (h_vbit) = opval;
12160     written |= (1 << 7);
12161     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
12162   }
12163 }
12164 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 2)), 0)) {
12165   {
12166     BI opval = 1;
12167     CPU (h_zbit) = opval;
12168     written |= (1 << 9);
12169     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12170   }
12171 }
12172 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 3)), 0)) {
12173   {
12174     BI opval = 1;
12175     CPU (h_nbit) = opval;
12176     written |= (1 << 3);
12177     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12178   }
12179 }
12180 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
12181   {
12182     BI opval = 1;
12183     CPU (h_xbit) = opval;
12184     written |= (1 << 8);
12185     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12186   }
12187 }
12188 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 5)), 0)) {
12189   {
12190     BI opval = 1;
12191     SET_H_IBIT (opval);
12192     written |= (1 << 2);
12193     TRACE_RESULT (current_cpu, abuf, "ibit", 'x', opval);
12194   }
12195 }
12196 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 6)), 0)) {
12197   {
12198     BI opval = 1;
12199     SET_H_UBIT (opval);
12200     written |= (1 << 6);
12201     TRACE_RESULT (current_cpu, abuf, "ubit", 'x', opval);
12202   }
12203 }
12204 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 7)), 0)) {
12205   {
12206     BI opval = 1;
12207     CPU (h_pbit) = opval;
12208     written |= (1 << 4);
12209     TRACE_RESULT (current_cpu, abuf, "pbit", 'x', opval);
12210   }
12211 }
12212   {
12213     BI opval = 0;
12214     SET_H_INSN_PREFIXED_P (opval);
12215     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12216   }
12217 if (EQSI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
12218   {
12219     BI opval = 0;
12220     CPU (h_xbit) = opval;
12221     written |= (1 << 8);
12222     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12223   }
12224 }
12225 }
12226
12227   abuf->written = written;
12228 #undef FLD
12229 }
12230   NEXT (vpc);
12231
12232   CASE (sem, INSN_CLEARF) : /* clearf ${list-of-flags} */
12233 {
12234   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12235   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12236 #define FLD(f) abuf->fields.sfmt_setf.f
12237   int UNUSED written = 0;
12238   IADDR UNUSED pc = abuf->addr;
12239   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12240
12241 {
12242   SI tmp_tmp;
12243   tmp_tmp = FLD (f_dstsrc);
12244 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 0)), 0)) {
12245   {
12246     BI opval = 0;
12247     CPU (h_cbit) = opval;
12248     written |= (1 << 1);
12249     TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
12250   }
12251 }
12252 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 1)), 0)) {
12253   {
12254     BI opval = 0;
12255     CPU (h_vbit) = opval;
12256     written |= (1 << 7);
12257     TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
12258   }
12259 }
12260 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 2)), 0)) {
12261   {
12262     BI opval = 0;
12263     CPU (h_zbit) = opval;
12264     written |= (1 << 9);
12265     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
12266   }
12267 }
12268 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 3)), 0)) {
12269   {
12270     BI opval = 0;
12271     CPU (h_nbit) = opval;
12272     written |= (1 << 3);
12273     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
12274   }
12275 }
12276 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
12277   {
12278     BI opval = 0;
12279     CPU (h_xbit) = opval;
12280     written |= (1 << 8);
12281     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12282   }
12283 }
12284 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 5)), 0)) {
12285   {
12286     BI opval = 0;
12287     SET_H_IBIT (opval);
12288     written |= (1 << 2);
12289     TRACE_RESULT (current_cpu, abuf, "ibit", 'x', opval);
12290   }
12291 }
12292 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 6)), 0)) {
12293   {
12294     BI opval = 0;
12295     SET_H_UBIT (opval);
12296     written |= (1 << 6);
12297     TRACE_RESULT (current_cpu, abuf, "ubit", 'x', opval);
12298   }
12299 }
12300 if (NESI (ANDSI (tmp_tmp, SLLSI (1, 7)), 0)) {
12301   {
12302     BI opval = 0;
12303     CPU (h_pbit) = opval;
12304     written |= (1 << 4);
12305     TRACE_RESULT (current_cpu, abuf, "pbit", 'x', opval);
12306   }
12307 }
12308 {
12309   {
12310     BI opval = 0;
12311     CPU (h_xbit) = opval;
12312     written |= (1 << 8);
12313     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12314   }
12315   {
12316     BI opval = 0;
12317     SET_H_INSN_PREFIXED_P (opval);
12318     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12319   }
12320 }
12321 }
12322
12323   abuf->written = written;
12324 #undef FLD
12325 }
12326   NEXT (vpc);
12327
12328   CASE (sem, INSN_RFE) : /* rfe */
12329 {
12330   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12331   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12332 #define FLD(f) abuf->fields.sfmt_rfe.f
12333   int UNUSED written = 0;
12334   IADDR UNUSED pc = abuf->addr;
12335   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12336
12337 {
12338   USI tmp_oldccs;
12339   USI tmp_samebits;
12340   USI tmp_shiftbits;
12341   USI tmp_keepmask;
12342   BI tmp_p1;
12343   tmp_oldccs = GET_H_SR (((UINT) 13));
12344   tmp_keepmask = 0xc0000000;
12345   tmp_samebits = ANDSI (tmp_oldccs, tmp_keepmask);
12346   tmp_shiftbits = ANDSI (SRLSI (ANDSI (tmp_oldccs, 1073609728), 10), INVSI (tmp_keepmask));
12347   tmp_p1 = NESI (0, ANDSI (tmp_oldccs, 131072));
12348   {
12349     SI opval = ORSI (ORSI (tmp_samebits, tmp_shiftbits), ((ANDBI (CPU (h_rbit), NOTBI (tmp_p1))) ? (0) : (128)));
12350     SET_H_SR (((UINT) 13), opval);
12351     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12352   }
12353 }
12354
12355 #undef FLD
12356 }
12357   NEXT (vpc);
12358
12359   CASE (sem, INSN_SFE) : /* sfe */
12360 {
12361   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12362   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12363 #define FLD(f) abuf->fields.sfmt_rfe.f
12364   int UNUSED written = 0;
12365   IADDR UNUSED pc = abuf->addr;
12366   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12367
12368 {
12369   SI tmp_oldccs;
12370   SI tmp_savemask;
12371   tmp_savemask = 0xc0000000;
12372   tmp_oldccs = GET_H_SR (((UINT) 13));
12373   {
12374     SI opval = ORSI (ANDSI (tmp_savemask, tmp_oldccs), ANDSI (INVSI (tmp_savemask), SLLSI (tmp_oldccs, 10)));
12375     SET_H_SR (((UINT) 13), opval);
12376     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12377   }
12378 }
12379
12380 #undef FLD
12381 }
12382   NEXT (vpc);
12383
12384   CASE (sem, INSN_RFG) : /* rfg */
12385 {
12386   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12387   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12388 #define FLD(f) abuf->fields.fmt_empty.f
12389   int UNUSED written = 0;
12390   IADDR UNUSED pc = abuf->addr;
12391   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12392
12393 crisv32f_rfg_handler (current_cpu, pc);
12394
12395 #undef FLD
12396 }
12397   NEXT (vpc);
12398
12399   CASE (sem, INSN_RFN) : /* rfn */
12400 {
12401   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12402   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12403 #define FLD(f) abuf->fields.sfmt_rfe.f
12404   int UNUSED written = 0;
12405   IADDR UNUSED pc = abuf->addr;
12406   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12407
12408 {
12409 {
12410   USI tmp_oldccs;
12411   USI tmp_samebits;
12412   USI tmp_shiftbits;
12413   USI tmp_keepmask;
12414   BI tmp_p1;
12415   tmp_oldccs = GET_H_SR (((UINT) 13));
12416   tmp_keepmask = 0xc0000000;
12417   tmp_samebits = ANDSI (tmp_oldccs, tmp_keepmask);
12418   tmp_shiftbits = ANDSI (SRLSI (ANDSI (tmp_oldccs, 1073609728), 10), INVSI (tmp_keepmask));
12419   tmp_p1 = NESI (0, ANDSI (tmp_oldccs, 131072));
12420   {
12421     SI opval = ORSI (ORSI (tmp_samebits, tmp_shiftbits), ((ANDBI (CPU (h_rbit), NOTBI (tmp_p1))) ? (0) : (128)));
12422     SET_H_SR (((UINT) 13), opval);
12423     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12424   }
12425 }
12426   {
12427     BI opval = 1;
12428     SET_H_MBIT (opval);
12429     TRACE_RESULT (current_cpu, abuf, "mbit", 'x', opval);
12430   }
12431 }
12432
12433 #undef FLD
12434 }
12435   NEXT (vpc);
12436
12437   CASE (sem, INSN_HALT) : /* halt */
12438 {
12439   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12440   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12441 #define FLD(f) abuf->fields.fmt_empty.f
12442   int UNUSED written = 0;
12443   IADDR UNUSED pc = abuf->addr;
12444   SEM_BRANCH_INIT
12445   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12446
12447   {
12448     USI opval = crisv32f_halt_handler (current_cpu, pc);
12449     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
12450     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12451   }
12452
12453   SEM_BRANCH_FINI (vpc);
12454 #undef FLD
12455 }
12456   NEXT (vpc);
12457
12458   CASE (sem, INSN_BCC_B) : /* b${cc} ${o-pcrel} */
12459 {
12460   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12461   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12462 #define FLD(f) abuf->fields.sfmt_bcc_b.f
12463   int UNUSED written = 0;
12464   IADDR UNUSED pc = abuf->addr;
12465   SEM_BRANCH_INIT
12466   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12467
12468 {
12469   BI tmp_truthval;
12470   tmp_truthval = ({   SI tmp_tmpcond;
12471   BI tmp_condres;
12472   tmp_tmpcond = FLD (f_operand2);
12473 ; if (EQSI (tmp_tmpcond, 0)) {
12474   tmp_condres = NOTBI (CPU (h_cbit));
12475 }
12476  else if (EQSI (tmp_tmpcond, 1)) {
12477   tmp_condres = CPU (h_cbit);
12478 }
12479  else if (EQSI (tmp_tmpcond, 2)) {
12480   tmp_condres = NOTBI (CPU (h_zbit));
12481 }
12482  else if (EQSI (tmp_tmpcond, 3)) {
12483   tmp_condres = CPU (h_zbit);
12484 }
12485  else if (EQSI (tmp_tmpcond, 4)) {
12486   tmp_condres = NOTBI (CPU (h_vbit));
12487 }
12488  else if (EQSI (tmp_tmpcond, 5)) {
12489   tmp_condres = CPU (h_vbit);
12490 }
12491  else if (EQSI (tmp_tmpcond, 6)) {
12492   tmp_condres = NOTBI (CPU (h_nbit));
12493 }
12494  else if (EQSI (tmp_tmpcond, 7)) {
12495   tmp_condres = CPU (h_nbit);
12496 }
12497  else if (EQSI (tmp_tmpcond, 8)) {
12498   tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
12499 }
12500  else if (EQSI (tmp_tmpcond, 9)) {
12501   tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
12502 }
12503  else if (EQSI (tmp_tmpcond, 10)) {
12504   tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
12505 }
12506  else if (EQSI (tmp_tmpcond, 11)) {
12507   tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
12508 }
12509  else if (EQSI (tmp_tmpcond, 12)) {
12510   tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
12511 }
12512  else if (EQSI (tmp_tmpcond, 13)) {
12513   tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
12514 }
12515  else if (EQSI (tmp_tmpcond, 14)) {
12516   tmp_condres = 1;
12517 }
12518  else if (EQSI (tmp_tmpcond, 15)) {
12519   tmp_condres = CPU (h_pbit);
12520 }
12521 ; tmp_condres; });
12522 crisv32f_branch_taken (current_cpu, pc, FLD (i_o_pcrel), tmp_truthval);
12523 {
12524   {
12525     BI opval = 0;
12526     CPU (h_xbit) = opval;
12527     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12528   }
12529   {
12530     BI opval = 0;
12531     SET_H_INSN_PREFIXED_P (opval);
12532     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12533   }
12534 }
12535 if (tmp_truthval) {
12536 {
12537   {
12538     USI opval = FLD (i_o_pcrel);
12539     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12540     written |= (1 << 8);
12541     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12542   }
12543 }
12544 }
12545 }
12546
12547   abuf->written = written;
12548   SEM_BRANCH_FINI (vpc);
12549 #undef FLD
12550 }
12551   NEXT (vpc);
12552
12553   CASE (sem, INSN_BA_B) : /* ba ${o-pcrel} */
12554 {
12555   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12556   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12557 #define FLD(f) abuf->fields.sfmt_bcc_b.f
12558   int UNUSED written = 0;
12559   IADDR UNUSED pc = abuf->addr;
12560   SEM_BRANCH_INIT
12561   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12562
12563 {
12564 {
12565   {
12566     BI opval = 0;
12567     CPU (h_xbit) = opval;
12568     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12569   }
12570   {
12571     BI opval = 0;
12572     SET_H_INSN_PREFIXED_P (opval);
12573     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12574   }
12575 }
12576 {
12577   {
12578     USI opval = FLD (i_o_pcrel);
12579     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12580     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12581   }
12582 }
12583 }
12584
12585   SEM_BRANCH_FINI (vpc);
12586 #undef FLD
12587 }
12588   NEXT (vpc);
12589
12590   CASE (sem, INSN_BCC_W) : /* b${cc} ${o-word-pcrel} */
12591 {
12592   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12593   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12594 #define FLD(f) abuf->fields.sfmt_bcc_w.f
12595   int UNUSED written = 0;
12596   IADDR UNUSED pc = abuf->addr;
12597   SEM_BRANCH_INIT
12598   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
12599
12600 {
12601   BI tmp_truthval;
12602   tmp_truthval = ({   SI tmp_tmpcond;
12603   BI tmp_condres;
12604   tmp_tmpcond = FLD (f_operand2);
12605 ; if (EQSI (tmp_tmpcond, 0)) {
12606   tmp_condres = NOTBI (CPU (h_cbit));
12607 }
12608  else if (EQSI (tmp_tmpcond, 1)) {
12609   tmp_condres = CPU (h_cbit);
12610 }
12611  else if (EQSI (tmp_tmpcond, 2)) {
12612   tmp_condres = NOTBI (CPU (h_zbit));
12613 }
12614  else if (EQSI (tmp_tmpcond, 3)) {
12615   tmp_condres = CPU (h_zbit);
12616 }
12617  else if (EQSI (tmp_tmpcond, 4)) {
12618   tmp_condres = NOTBI (CPU (h_vbit));
12619 }
12620  else if (EQSI (tmp_tmpcond, 5)) {
12621   tmp_condres = CPU (h_vbit);
12622 }
12623  else if (EQSI (tmp_tmpcond, 6)) {
12624   tmp_condres = NOTBI (CPU (h_nbit));
12625 }
12626  else if (EQSI (tmp_tmpcond, 7)) {
12627   tmp_condres = CPU (h_nbit);
12628 }
12629  else if (EQSI (tmp_tmpcond, 8)) {
12630   tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
12631 }
12632  else if (EQSI (tmp_tmpcond, 9)) {
12633   tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
12634 }
12635  else if (EQSI (tmp_tmpcond, 10)) {
12636   tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
12637 }
12638  else if (EQSI (tmp_tmpcond, 11)) {
12639   tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
12640 }
12641  else if (EQSI (tmp_tmpcond, 12)) {
12642   tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
12643 }
12644  else if (EQSI (tmp_tmpcond, 13)) {
12645   tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
12646 }
12647  else if (EQSI (tmp_tmpcond, 14)) {
12648   tmp_condres = 1;
12649 }
12650  else if (EQSI (tmp_tmpcond, 15)) {
12651   tmp_condres = CPU (h_pbit);
12652 }
12653 ; tmp_condres; });
12654 crisv32f_branch_taken (current_cpu, pc, FLD (i_o_word_pcrel), tmp_truthval);
12655 {
12656   {
12657     BI opval = 0;
12658     CPU (h_xbit) = opval;
12659     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12660   }
12661   {
12662     BI opval = 0;
12663     SET_H_INSN_PREFIXED_P (opval);
12664     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12665   }
12666 }
12667 if (tmp_truthval) {
12668 {
12669   {
12670     USI opval = FLD (i_o_word_pcrel);
12671     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12672     written |= (1 << 8);
12673     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12674   }
12675 }
12676 }
12677 }
12678
12679   abuf->written = written;
12680   SEM_BRANCH_FINI (vpc);
12681 #undef FLD
12682 }
12683   NEXT (vpc);
12684
12685   CASE (sem, INSN_BA_W) : /* ba ${o-word-pcrel} */
12686 {
12687   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12688   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12689 #define FLD(f) abuf->fields.sfmt_bcc_w.f
12690   int UNUSED written = 0;
12691   IADDR UNUSED pc = abuf->addr;
12692   SEM_BRANCH_INIT
12693   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
12694
12695 {
12696 {
12697   {
12698     BI opval = 0;
12699     CPU (h_xbit) = opval;
12700     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12701   }
12702   {
12703     BI opval = 0;
12704     SET_H_INSN_PREFIXED_P (opval);
12705     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12706   }
12707 }
12708 {
12709   {
12710     USI opval = FLD (i_o_word_pcrel);
12711     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12712     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12713   }
12714 }
12715 }
12716
12717   SEM_BRANCH_FINI (vpc);
12718 #undef FLD
12719 }
12720   NEXT (vpc);
12721
12722   CASE (sem, INSN_JAS_R) : /* jas ${Rs},${Pd} */
12723 {
12724   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12725   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12726 #define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
12727   int UNUSED written = 0;
12728   IADDR UNUSED pc = abuf->addr;
12729   SEM_BRANCH_INIT
12730   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12731
12732 {
12733 {
12734   {
12735     BI opval = 0;
12736     CPU (h_xbit) = opval;
12737     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12738   }
12739   {
12740     BI opval = 0;
12741     SET_H_INSN_PREFIXED_P (opval);
12742     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12743   }
12744 }
12745 if (ANDIF (EQSI (FLD (f_operand1), 1), EQSI (FLD (f_operand2), 11))) {
12746 cris_flush_simulator_decode_cache (current_cpu, pc);
12747 }
12748 {
12749 {
12750   {
12751     SI opval = ADDSI (pc, 4);
12752     SET_H_SR (FLD (f_operand2), opval);
12753     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12754   }
12755   {
12756     USI opval = GET_H_GR (FLD (f_operand1));
12757     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
12758     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12759   }
12760 }
12761 }
12762 }
12763
12764   SEM_BRANCH_FINI (vpc);
12765 #undef FLD
12766 }
12767   NEXT (vpc);
12768
12769   CASE (sem, INSN_JAS_C) : /* jas ${const32},${Pd} */
12770 {
12771   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12772   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12773 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
12774   int UNUSED written = 0;
12775   IADDR UNUSED pc = abuf->addr;
12776   SEM_BRANCH_INIT
12777   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
12778
12779 {
12780 {
12781   {
12782     BI opval = 0;
12783     CPU (h_xbit) = opval;
12784     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12785   }
12786   {
12787     BI opval = 0;
12788     SET_H_INSN_PREFIXED_P (opval);
12789     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12790   }
12791 }
12792 {
12793 {
12794   {
12795     SI opval = ADDSI (pc, 8);
12796     SET_H_SR (FLD (f_operand2), opval);
12797     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12798   }
12799   {
12800     USI opval = FLD (f_indir_pc__dword);
12801     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12802     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12803   }
12804 }
12805 }
12806 }
12807
12808   SEM_BRANCH_FINI (vpc);
12809 #undef FLD
12810 }
12811   NEXT (vpc);
12812
12813   CASE (sem, INSN_JUMP_P) : /* jump ${Ps} */
12814 {
12815   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12816   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12817 #define FLD(f) abuf->fields.sfmt_mcp.f
12818   int UNUSED written = 0;
12819   IADDR UNUSED pc = abuf->addr;
12820   SEM_BRANCH_INIT
12821   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12822
12823 {
12824 {
12825   {
12826     BI opval = 0;
12827     CPU (h_xbit) = opval;
12828     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12829   }
12830   {
12831     BI opval = 0;
12832     SET_H_INSN_PREFIXED_P (opval);
12833     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12834   }
12835 }
12836 {
12837   {
12838     USI opval = GET_H_SR (FLD (f_operand2));
12839     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
12840     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12841   }
12842 }
12843 }
12844
12845   SEM_BRANCH_FINI (vpc);
12846 #undef FLD
12847 }
12848   NEXT (vpc);
12849
12850   CASE (sem, INSN_BAS_C) : /* bas ${const32},${Pd} */
12851 {
12852   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12853   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12854 #define FLD(f) abuf->fields.sfmt_bas_c.f
12855   int UNUSED written = 0;
12856   IADDR UNUSED pc = abuf->addr;
12857   SEM_BRANCH_INIT
12858   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
12859
12860 {
12861 {
12862   {
12863     BI opval = 0;
12864     CPU (h_xbit) = opval;
12865     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12866   }
12867   {
12868     BI opval = 0;
12869     SET_H_INSN_PREFIXED_P (opval);
12870     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12871   }
12872 }
12873 {
12874 {
12875   {
12876     SI opval = ADDSI (pc, 8);
12877     SET_H_SR (FLD (f_operand2), opval);
12878     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12879   }
12880   {
12881     USI opval = FLD (i_const32_pcrel);
12882     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
12883     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12884   }
12885 }
12886 }
12887 }
12888
12889   SEM_BRANCH_FINI (vpc);
12890 #undef FLD
12891 }
12892   NEXT (vpc);
12893
12894   CASE (sem, INSN_JASC_R) : /* jasc ${Rs},${Pd} */
12895 {
12896   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12897   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12898 #define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
12899   int UNUSED written = 0;
12900   IADDR UNUSED pc = abuf->addr;
12901   SEM_BRANCH_INIT
12902   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
12903
12904 {
12905 {
12906   {
12907     BI opval = 0;
12908     CPU (h_xbit) = opval;
12909     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12910   }
12911   {
12912     BI opval = 0;
12913     SET_H_INSN_PREFIXED_P (opval);
12914     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12915   }
12916 }
12917 {
12918 {
12919   {
12920     SI opval = ADDSI (pc, 8);
12921     SET_H_SR (FLD (f_operand2), opval);
12922     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12923   }
12924   {
12925     USI opval = GET_H_GR (FLD (f_operand1));
12926     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
12927     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12928   }
12929 }
12930 }
12931 }
12932
12933   SEM_BRANCH_FINI (vpc);
12934 #undef FLD
12935 }
12936   NEXT (vpc);
12937
12938   CASE (sem, INSN_JASC_C) : /* jasc ${const32},${Pd} */
12939 {
12940   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12941   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12942 #define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
12943   int UNUSED written = 0;
12944   IADDR UNUSED pc = abuf->addr;
12945   SEM_BRANCH_INIT
12946   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
12947
12948 {
12949 {
12950   {
12951     BI opval = 0;
12952     CPU (h_xbit) = opval;
12953     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12954   }
12955   {
12956     BI opval = 0;
12957     SET_H_INSN_PREFIXED_P (opval);
12958     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
12959   }
12960 }
12961 {
12962 {
12963   {
12964     SI opval = ADDSI (pc, 12);
12965     SET_H_SR (FLD (f_operand2), opval);
12966     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
12967   }
12968   {
12969     USI opval = FLD (f_indir_pc__dword);
12970     SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
12971     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
12972   }
12973 }
12974 }
12975 }
12976
12977   SEM_BRANCH_FINI (vpc);
12978 #undef FLD
12979 }
12980   NEXT (vpc);
12981
12982   CASE (sem, INSN_BASC_C) : /* basc ${const32},${Pd} */
12983 {
12984   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
12985   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
12986 #define FLD(f) abuf->fields.sfmt_bas_c.f
12987   int UNUSED written = 0;
12988   IADDR UNUSED pc = abuf->addr;
12989   SEM_BRANCH_INIT
12990   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
12991
12992 {
12993 {
12994   {
12995     BI opval = 0;
12996     CPU (h_xbit) = opval;
12997     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
12998   }
12999   {
13000     BI opval = 0;
13001     SET_H_INSN_PREFIXED_P (opval);
13002     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13003   }
13004 }
13005 {
13006 {
13007   {
13008     SI opval = ADDSI (pc, 12);
13009     SET_H_SR (FLD (f_operand2), opval);
13010     TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
13011   }
13012   {
13013     USI opval = FLD (i_const32_pcrel);
13014     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
13015     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
13016   }
13017 }
13018 }
13019 }
13020
13021   SEM_BRANCH_FINI (vpc);
13022 #undef FLD
13023 }
13024   NEXT (vpc);
13025
13026   CASE (sem, INSN_BREAK) : /* break $n */
13027 {
13028   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13029   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13030 #define FLD(f) abuf->fields.sfmt_break.f
13031   int UNUSED written = 0;
13032   IADDR UNUSED pc = abuf->addr;
13033   SEM_BRANCH_INIT
13034   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13035
13036 {
13037 {
13038   {
13039     BI opval = 0;
13040     CPU (h_xbit) = opval;
13041     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13042   }
13043   {
13044     BI opval = 0;
13045     SET_H_INSN_PREFIXED_P (opval);
13046     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13047   }
13048 }
13049   {
13050     USI opval = crisv32f_break_handler (current_cpu, FLD (f_u4), pc);
13051     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
13052     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
13053   }
13054 }
13055
13056   SEM_BRANCH_FINI (vpc);
13057 #undef FLD
13058 }
13059   NEXT (vpc);
13060
13061   CASE (sem, INSN_BOUND_R_B_R) : /* bound-r.b ${Rs},${Rd} */
13062 {
13063   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13064   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13065 #define FLD(f) abuf->fields.sfmt_muls_b.f
13066   int UNUSED written = 0;
13067   IADDR UNUSED pc = abuf->addr;
13068   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13069
13070 {
13071   SI tmp_tmpopd;
13072   SI tmp_tmpops;
13073   SI tmp_newval;
13074   tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
13075   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13076   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13077   {
13078     SI opval = tmp_newval;
13079     SET_H_GR (FLD (f_operand2), opval);
13080     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13081   }
13082 {
13083   {
13084     BI opval = LTSI (tmp_newval, 0);
13085     CPU (h_nbit) = opval;
13086     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13087   }
13088   {
13089     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13090     CPU (h_zbit) = opval;
13091     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13092   }
13093 SET_H_CBIT_MOVE (0);
13094 SET_H_VBIT_MOVE (0);
13095 {
13096   {
13097     BI opval = 0;
13098     CPU (h_xbit) = opval;
13099     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13100   }
13101   {
13102     BI opval = 0;
13103     SET_H_INSN_PREFIXED_P (opval);
13104     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13105   }
13106 }
13107 }
13108 }
13109
13110 #undef FLD
13111 }
13112   NEXT (vpc);
13113
13114   CASE (sem, INSN_BOUND_R_W_R) : /* bound-r.w ${Rs},${Rd} */
13115 {
13116   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13117   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13118 #define FLD(f) abuf->fields.sfmt_muls_b.f
13119   int UNUSED written = 0;
13120   IADDR UNUSED pc = abuf->addr;
13121   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13122
13123 {
13124   SI tmp_tmpopd;
13125   SI tmp_tmpops;
13126   SI tmp_newval;
13127   tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
13128   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13129   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13130   {
13131     SI opval = tmp_newval;
13132     SET_H_GR (FLD (f_operand2), opval);
13133     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13134   }
13135 {
13136   {
13137     BI opval = LTSI (tmp_newval, 0);
13138     CPU (h_nbit) = opval;
13139     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13140   }
13141   {
13142     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13143     CPU (h_zbit) = opval;
13144     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13145   }
13146 SET_H_CBIT_MOVE (0);
13147 SET_H_VBIT_MOVE (0);
13148 {
13149   {
13150     BI opval = 0;
13151     CPU (h_xbit) = opval;
13152     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13153   }
13154   {
13155     BI opval = 0;
13156     SET_H_INSN_PREFIXED_P (opval);
13157     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13158   }
13159 }
13160 }
13161 }
13162
13163 #undef FLD
13164 }
13165   NEXT (vpc);
13166
13167   CASE (sem, INSN_BOUND_R_D_R) : /* bound-r.d ${Rs},${Rd} */
13168 {
13169   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13170   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13171 #define FLD(f) abuf->fields.sfmt_muls_b.f
13172   int UNUSED written = 0;
13173   IADDR UNUSED pc = abuf->addr;
13174   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13175
13176 {
13177   SI tmp_tmpopd;
13178   SI tmp_tmpops;
13179   SI tmp_newval;
13180   tmp_tmpops = TRUNCSISI (GET_H_GR (FLD (f_operand1)));
13181   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13182   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13183   {
13184     SI opval = tmp_newval;
13185     SET_H_GR (FLD (f_operand2), opval);
13186     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13187   }
13188 {
13189   {
13190     BI opval = LTSI (tmp_newval, 0);
13191     CPU (h_nbit) = opval;
13192     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13193   }
13194   {
13195     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13196     CPU (h_zbit) = opval;
13197     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13198   }
13199 SET_H_CBIT_MOVE (0);
13200 SET_H_VBIT_MOVE (0);
13201 {
13202   {
13203     BI opval = 0;
13204     CPU (h_xbit) = opval;
13205     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13206   }
13207   {
13208     BI opval = 0;
13209     SET_H_INSN_PREFIXED_P (opval);
13210     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13211   }
13212 }
13213 }
13214 }
13215
13216 #undef FLD
13217 }
13218   NEXT (vpc);
13219
13220   CASE (sem, INSN_BOUND_CB) : /* bound.b [PC+],${Rd} */
13221 {
13222   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13223   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13224 #define FLD(f) abuf->fields.sfmt_bound_cb.f
13225   int UNUSED written = 0;
13226   IADDR UNUSED pc = abuf->addr;
13227   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
13228
13229 {
13230   SI tmp_tmpopd;
13231   SI tmp_tmpops;
13232   SI tmp_newval;
13233   tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
13234   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13235   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13236   {
13237     SI opval = tmp_newval;
13238     SET_H_GR (FLD (f_operand2), opval);
13239     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13240   }
13241 {
13242   {
13243     BI opval = LTSI (tmp_newval, 0);
13244     CPU (h_nbit) = opval;
13245     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13246   }
13247   {
13248     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13249     CPU (h_zbit) = opval;
13250     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13251   }
13252 SET_H_CBIT_MOVE (0);
13253 SET_H_VBIT_MOVE (0);
13254 {
13255   {
13256     BI opval = 0;
13257     CPU (h_xbit) = opval;
13258     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13259   }
13260   {
13261     BI opval = 0;
13262     SET_H_INSN_PREFIXED_P (opval);
13263     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13264   }
13265 }
13266 }
13267 }
13268
13269 #undef FLD
13270 }
13271   NEXT (vpc);
13272
13273   CASE (sem, INSN_BOUND_CW) : /* bound.w [PC+],${Rd} */
13274 {
13275   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13276   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13277 #define FLD(f) abuf->fields.sfmt_bound_cw.f
13278   int UNUSED written = 0;
13279   IADDR UNUSED pc = abuf->addr;
13280   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
13281
13282 {
13283   SI tmp_tmpopd;
13284   SI tmp_tmpops;
13285   SI tmp_newval;
13286   tmp_tmpops = ZEXTSISI (FLD (f_indir_pc__word));
13287   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13288   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13289   {
13290     SI opval = tmp_newval;
13291     SET_H_GR (FLD (f_operand2), opval);
13292     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13293   }
13294 {
13295   {
13296     BI opval = LTSI (tmp_newval, 0);
13297     CPU (h_nbit) = opval;
13298     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13299   }
13300   {
13301     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13302     CPU (h_zbit) = opval;
13303     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13304   }
13305 SET_H_CBIT_MOVE (0);
13306 SET_H_VBIT_MOVE (0);
13307 {
13308   {
13309     BI opval = 0;
13310     CPU (h_xbit) = opval;
13311     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13312   }
13313   {
13314     BI opval = 0;
13315     SET_H_INSN_PREFIXED_P (opval);
13316     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13317   }
13318 }
13319 }
13320 }
13321
13322 #undef FLD
13323 }
13324   NEXT (vpc);
13325
13326   CASE (sem, INSN_BOUND_CD) : /* bound.d [PC+],${Rd} */
13327 {
13328   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13329   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13330 #define FLD(f) abuf->fields.sfmt_bound_cd.f
13331   int UNUSED written = 0;
13332   IADDR UNUSED pc = abuf->addr;
13333   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
13334
13335 {
13336   SI tmp_tmpopd;
13337   SI tmp_tmpops;
13338   SI tmp_newval;
13339   tmp_tmpops = FLD (f_indir_pc__dword);
13340   tmp_tmpopd = GET_H_GR (FLD (f_operand2));
13341   tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
13342   {
13343     SI opval = tmp_newval;
13344     SET_H_GR (FLD (f_operand2), opval);
13345     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13346   }
13347 {
13348   {
13349     BI opval = LTSI (tmp_newval, 0);
13350     CPU (h_nbit) = opval;
13351     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13352   }
13353   {
13354     BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13355     CPU (h_zbit) = opval;
13356     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13357   }
13358 SET_H_CBIT_MOVE (0);
13359 SET_H_VBIT_MOVE (0);
13360 {
13361   {
13362     BI opval = 0;
13363     CPU (h_xbit) = opval;
13364     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13365   }
13366   {
13367     BI opval = 0;
13368     SET_H_INSN_PREFIXED_P (opval);
13369     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13370   }
13371 }
13372 }
13373 }
13374
13375 #undef FLD
13376 }
13377   NEXT (vpc);
13378
13379   CASE (sem, INSN_SCC) : /* s${cc} ${Rd-sfield} */
13380 {
13381   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13382   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13383 #define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
13384   int UNUSED written = 0;
13385   IADDR UNUSED pc = abuf->addr;
13386   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13387
13388 {
13389   BI tmp_truthval;
13390   tmp_truthval = ({   SI tmp_tmpcond;
13391   BI tmp_condres;
13392   tmp_tmpcond = FLD (f_operand2);
13393 ; if (EQSI (tmp_tmpcond, 0)) {
13394   tmp_condres = NOTBI (CPU (h_cbit));
13395 }
13396  else if (EQSI (tmp_tmpcond, 1)) {
13397   tmp_condres = CPU (h_cbit);
13398 }
13399  else if (EQSI (tmp_tmpcond, 2)) {
13400   tmp_condres = NOTBI (CPU (h_zbit));
13401 }
13402  else if (EQSI (tmp_tmpcond, 3)) {
13403   tmp_condres = CPU (h_zbit);
13404 }
13405  else if (EQSI (tmp_tmpcond, 4)) {
13406   tmp_condres = NOTBI (CPU (h_vbit));
13407 }
13408  else if (EQSI (tmp_tmpcond, 5)) {
13409   tmp_condres = CPU (h_vbit);
13410 }
13411  else if (EQSI (tmp_tmpcond, 6)) {
13412   tmp_condres = NOTBI (CPU (h_nbit));
13413 }
13414  else if (EQSI (tmp_tmpcond, 7)) {
13415   tmp_condres = CPU (h_nbit);
13416 }
13417  else if (EQSI (tmp_tmpcond, 8)) {
13418   tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
13419 }
13420  else if (EQSI (tmp_tmpcond, 9)) {
13421   tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
13422 }
13423  else if (EQSI (tmp_tmpcond, 10)) {
13424   tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
13425 }
13426  else if (EQSI (tmp_tmpcond, 11)) {
13427   tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
13428 }
13429  else if (EQSI (tmp_tmpcond, 12)) {
13430   tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
13431 }
13432  else if (EQSI (tmp_tmpcond, 13)) {
13433   tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
13434 }
13435  else if (EQSI (tmp_tmpcond, 14)) {
13436   tmp_condres = 1;
13437 }
13438  else if (EQSI (tmp_tmpcond, 15)) {
13439   tmp_condres = CPU (h_pbit);
13440 }
13441 ; tmp_condres; });
13442   {
13443     SI opval = ZEXTBISI (tmp_truthval);
13444     SET_H_GR (FLD (f_operand1), opval);
13445     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13446   }
13447 {
13448   {
13449     BI opval = 0;
13450     CPU (h_xbit) = opval;
13451     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13452   }
13453   {
13454     BI opval = 0;
13455     SET_H_INSN_PREFIXED_P (opval);
13456     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13457   }
13458 }
13459 }
13460
13461 #undef FLD
13462 }
13463   NEXT (vpc);
13464
13465   CASE (sem, INSN_LZ) : /* lz ${Rs},${Rd} */
13466 {
13467   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13468   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13469 #define FLD(f) abuf->fields.sfmt_muls_b.f
13470   int UNUSED written = 0;
13471   IADDR UNUSED pc = abuf->addr;
13472   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13473
13474 {
13475   SI tmp_tmpd;
13476   SI tmp_tmp;
13477   tmp_tmp = GET_H_GR (FLD (f_operand1));
13478   tmp_tmpd = 0;
13479 {
13480 if (GESI (tmp_tmp, 0)) {
13481 {
13482   tmp_tmp = SLLSI (tmp_tmp, 1);
13483   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13484 }
13485 }
13486 if (GESI (tmp_tmp, 0)) {
13487 {
13488   tmp_tmp = SLLSI (tmp_tmp, 1);
13489   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13490 }
13491 }
13492 if (GESI (tmp_tmp, 0)) {
13493 {
13494   tmp_tmp = SLLSI (tmp_tmp, 1);
13495   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13496 }
13497 }
13498 if (GESI (tmp_tmp, 0)) {
13499 {
13500   tmp_tmp = SLLSI (tmp_tmp, 1);
13501   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13502 }
13503 }
13504 if (GESI (tmp_tmp, 0)) {
13505 {
13506   tmp_tmp = SLLSI (tmp_tmp, 1);
13507   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13508 }
13509 }
13510 if (GESI (tmp_tmp, 0)) {
13511 {
13512   tmp_tmp = SLLSI (tmp_tmp, 1);
13513   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13514 }
13515 }
13516 if (GESI (tmp_tmp, 0)) {
13517 {
13518   tmp_tmp = SLLSI (tmp_tmp, 1);
13519   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13520 }
13521 }
13522 if (GESI (tmp_tmp, 0)) {
13523 {
13524   tmp_tmp = SLLSI (tmp_tmp, 1);
13525   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13526 }
13527 }
13528 if (GESI (tmp_tmp, 0)) {
13529 {
13530   tmp_tmp = SLLSI (tmp_tmp, 1);
13531   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13532 }
13533 }
13534 if (GESI (tmp_tmp, 0)) {
13535 {
13536   tmp_tmp = SLLSI (tmp_tmp, 1);
13537   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13538 }
13539 }
13540 if (GESI (tmp_tmp, 0)) {
13541 {
13542   tmp_tmp = SLLSI (tmp_tmp, 1);
13543   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13544 }
13545 }
13546 if (GESI (tmp_tmp, 0)) {
13547 {
13548   tmp_tmp = SLLSI (tmp_tmp, 1);
13549   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13550 }
13551 }
13552 if (GESI (tmp_tmp, 0)) {
13553 {
13554   tmp_tmp = SLLSI (tmp_tmp, 1);
13555   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13556 }
13557 }
13558 if (GESI (tmp_tmp, 0)) {
13559 {
13560   tmp_tmp = SLLSI (tmp_tmp, 1);
13561   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13562 }
13563 }
13564 if (GESI (tmp_tmp, 0)) {
13565 {
13566   tmp_tmp = SLLSI (tmp_tmp, 1);
13567   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13568 }
13569 }
13570 if (GESI (tmp_tmp, 0)) {
13571 {
13572   tmp_tmp = SLLSI (tmp_tmp, 1);
13573   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13574 }
13575 }
13576 if (GESI (tmp_tmp, 0)) {
13577 {
13578   tmp_tmp = SLLSI (tmp_tmp, 1);
13579   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13580 }
13581 }
13582 if (GESI (tmp_tmp, 0)) {
13583 {
13584   tmp_tmp = SLLSI (tmp_tmp, 1);
13585   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13586 }
13587 }
13588 if (GESI (tmp_tmp, 0)) {
13589 {
13590   tmp_tmp = SLLSI (tmp_tmp, 1);
13591   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13592 }
13593 }
13594 if (GESI (tmp_tmp, 0)) {
13595 {
13596   tmp_tmp = SLLSI (tmp_tmp, 1);
13597   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13598 }
13599 }
13600 if (GESI (tmp_tmp, 0)) {
13601 {
13602   tmp_tmp = SLLSI (tmp_tmp, 1);
13603   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13604 }
13605 }
13606 if (GESI (tmp_tmp, 0)) {
13607 {
13608   tmp_tmp = SLLSI (tmp_tmp, 1);
13609   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13610 }
13611 }
13612 if (GESI (tmp_tmp, 0)) {
13613 {
13614   tmp_tmp = SLLSI (tmp_tmp, 1);
13615   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13616 }
13617 }
13618 if (GESI (tmp_tmp, 0)) {
13619 {
13620   tmp_tmp = SLLSI (tmp_tmp, 1);
13621   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13622 }
13623 }
13624 if (GESI (tmp_tmp, 0)) {
13625 {
13626   tmp_tmp = SLLSI (tmp_tmp, 1);
13627   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13628 }
13629 }
13630 if (GESI (tmp_tmp, 0)) {
13631 {
13632   tmp_tmp = SLLSI (tmp_tmp, 1);
13633   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13634 }
13635 }
13636 if (GESI (tmp_tmp, 0)) {
13637 {
13638   tmp_tmp = SLLSI (tmp_tmp, 1);
13639   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13640 }
13641 }
13642 if (GESI (tmp_tmp, 0)) {
13643 {
13644   tmp_tmp = SLLSI (tmp_tmp, 1);
13645   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13646 }
13647 }
13648 if (GESI (tmp_tmp, 0)) {
13649 {
13650   tmp_tmp = SLLSI (tmp_tmp, 1);
13651   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13652 }
13653 }
13654 if (GESI (tmp_tmp, 0)) {
13655 {
13656   tmp_tmp = SLLSI (tmp_tmp, 1);
13657   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13658 }
13659 }
13660 if (GESI (tmp_tmp, 0)) {
13661 {
13662   tmp_tmp = SLLSI (tmp_tmp, 1);
13663   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13664 }
13665 }
13666 if (GESI (tmp_tmp, 0)) {
13667 {
13668   tmp_tmp = SLLSI (tmp_tmp, 1);
13669   tmp_tmpd = ADDSI (tmp_tmpd, 1);
13670 }
13671 }
13672 }
13673   {
13674     SI opval = tmp_tmpd;
13675     SET_H_GR (FLD (f_operand2), opval);
13676     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13677   }
13678 {
13679   {
13680     BI opval = LTSI (tmp_tmpd, 0);
13681     CPU (h_nbit) = opval;
13682     TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
13683   }
13684   {
13685     BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
13686     CPU (h_zbit) = opval;
13687     TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
13688   }
13689 SET_H_CBIT_MOVE (0);
13690 SET_H_VBIT_MOVE (0);
13691 {
13692   {
13693     BI opval = 0;
13694     CPU (h_xbit) = opval;
13695     TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
13696   }
13697   {
13698     BI opval = 0;
13699     SET_H_INSN_PREFIXED_P (opval);
13700     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13701   }
13702 }
13703 }
13704 }
13705
13706 #undef FLD
13707 }
13708   NEXT (vpc);
13709
13710   CASE (sem, INSN_ADDOQ) : /* addoq $o,$Rs,ACR */
13711 {
13712   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13713   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13714 #define FLD(f) abuf->fields.sfmt_addoq.f
13715   int UNUSED written = 0;
13716   IADDR UNUSED pc = abuf->addr;
13717   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13718
13719 {
13720   {
13721     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), FLD (f_s8));
13722     SET_H_PREFIXREG_V32 (opval);
13723     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13724   }
13725   {
13726     BI opval = 1;
13727     SET_H_INSN_PREFIXED_P (opval);
13728     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13729   }
13730 }
13731
13732 #undef FLD
13733 }
13734   NEXT (vpc);
13735
13736   CASE (sem, INSN_ADDO_M_B_M) : /* addo-m.b [${Rs}${inc}],$Rd,ACR */
13737 {
13738   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13739   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13740 #define FLD(f) abuf->fields.sfmt_addc_m.f
13741   int UNUSED written = 0;
13742   IADDR UNUSED pc = abuf->addr;
13743   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13744
13745 {
13746   QI tmp_tmps;
13747   tmp_tmps = ({   SI tmp_addr;
13748   QI tmp_tmp_mem;
13749   BI tmp_postinc;
13750   tmp_postinc = FLD (f_memmode);
13751 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
13752 ;   tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
13753 ; if (NEBI (tmp_postinc, 0)) {
13754 {
13755 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13756   tmp_addr = ADDSI (tmp_addr, 1);
13757 }
13758   {
13759     SI opval = tmp_addr;
13760     SET_H_GR (FLD (f_operand1), opval);
13761     written |= (1 << 6);
13762     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13763   }
13764 }
13765 }
13766 ; tmp_tmp_mem; });
13767   {
13768     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTQISI (tmp_tmps));
13769     SET_H_PREFIXREG_V32 (opval);
13770     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13771   }
13772   {
13773     BI opval = 1;
13774     SET_H_INSN_PREFIXED_P (opval);
13775     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13776   }
13777 }
13778
13779   abuf->written = written;
13780 #undef FLD
13781 }
13782   NEXT (vpc);
13783
13784   CASE (sem, INSN_ADDO_M_W_M) : /* addo-m.w [${Rs}${inc}],$Rd,ACR */
13785 {
13786   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13787   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13788 #define FLD(f) abuf->fields.sfmt_addc_m.f
13789   int UNUSED written = 0;
13790   IADDR UNUSED pc = abuf->addr;
13791   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13792
13793 {
13794   HI tmp_tmps;
13795   tmp_tmps = ({   SI tmp_addr;
13796   HI tmp_tmp_mem;
13797   BI tmp_postinc;
13798   tmp_postinc = FLD (f_memmode);
13799 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
13800 ;   tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
13801 ; if (NEBI (tmp_postinc, 0)) {
13802 {
13803 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13804   tmp_addr = ADDSI (tmp_addr, 2);
13805 }
13806   {
13807     SI opval = tmp_addr;
13808     SET_H_GR (FLD (f_operand1), opval);
13809     written |= (1 << 6);
13810     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13811   }
13812 }
13813 }
13814 ; tmp_tmp_mem; });
13815   {
13816     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTHISI (tmp_tmps));
13817     SET_H_PREFIXREG_V32 (opval);
13818     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13819   }
13820   {
13821     BI opval = 1;
13822     SET_H_INSN_PREFIXED_P (opval);
13823     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13824   }
13825 }
13826
13827   abuf->written = written;
13828 #undef FLD
13829 }
13830   NEXT (vpc);
13831
13832   CASE (sem, INSN_ADDO_M_D_M) : /* addo-m.d [${Rs}${inc}],$Rd,ACR */
13833 {
13834   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13835   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13836 #define FLD(f) abuf->fields.sfmt_addc_m.f
13837   int UNUSED written = 0;
13838   IADDR UNUSED pc = abuf->addr;
13839   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13840
13841 {
13842   SI tmp_tmps;
13843   tmp_tmps = ({   SI tmp_addr;
13844   SI tmp_tmp_mem;
13845   BI tmp_postinc;
13846   tmp_postinc = FLD (f_memmode);
13847 ;   tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
13848 ;   tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
13849 ; if (NEBI (tmp_postinc, 0)) {
13850 {
13851 if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
13852   tmp_addr = ADDSI (tmp_addr, 4);
13853 }
13854   {
13855     SI opval = tmp_addr;
13856     SET_H_GR (FLD (f_operand1), opval);
13857     written |= (1 << 6);
13858     TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
13859   }
13860 }
13861 }
13862 ; tmp_tmp_mem; });
13863   {
13864     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), tmp_tmps);
13865     SET_H_PREFIXREG_V32 (opval);
13866     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13867   }
13868   {
13869     BI opval = 1;
13870     SET_H_INSN_PREFIXED_P (opval);
13871     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13872   }
13873 }
13874
13875   abuf->written = written;
13876 #undef FLD
13877 }
13878   NEXT (vpc);
13879
13880   CASE (sem, INSN_ADDO_CB) : /* addo.b [PC+],$Rd,ACR */
13881 {
13882   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13883   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13884 #define FLD(f) abuf->fields.sfmt_bound_cb.f
13885   int UNUSED written = 0;
13886   IADDR UNUSED pc = abuf->addr;
13887   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
13888
13889 {
13890   {
13891     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte))));
13892     SET_H_PREFIXREG_V32 (opval);
13893     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13894   }
13895   {
13896     BI opval = 1;
13897     SET_H_INSN_PREFIXED_P (opval);
13898     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13899   }
13900 }
13901
13902 #undef FLD
13903 }
13904   NEXT (vpc);
13905
13906   CASE (sem, INSN_ADDO_CW) : /* addo.w [PC+],$Rd,ACR */
13907 {
13908   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13909   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13910 #define FLD(f) abuf->fields.sfmt_bound_cw.f
13911   int UNUSED written = 0;
13912   IADDR UNUSED pc = abuf->addr;
13913   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
13914
13915 {
13916   {
13917     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word))));
13918     SET_H_PREFIXREG_V32 (opval);
13919     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13920   }
13921   {
13922     BI opval = 1;
13923     SET_H_INSN_PREFIXED_P (opval);
13924     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13925   }
13926 }
13927
13928 #undef FLD
13929 }
13930   NEXT (vpc);
13931
13932   CASE (sem, INSN_ADDO_CD) : /* addo.d [PC+],$Rd,ACR */
13933 {
13934   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13935   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13936 #define FLD(f) abuf->fields.sfmt_bound_cd.f
13937   int UNUSED written = 0;
13938   IADDR UNUSED pc = abuf->addr;
13939   vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
13940
13941 {
13942   {
13943     SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
13944     SET_H_PREFIXREG_V32 (opval);
13945     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13946   }
13947   {
13948     BI opval = 1;
13949     SET_H_INSN_PREFIXED_P (opval);
13950     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13951   }
13952 }
13953
13954 #undef FLD
13955 }
13956   NEXT (vpc);
13957
13958   CASE (sem, INSN_ADDI_ACR_B_R) : /* addi-acr.b ${Rs-dfield}.m,${Rd-sfield},ACR */
13959 {
13960   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13961   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13962 #define FLD(f) abuf->fields.sfmt_muls_b.f
13963   int UNUSED written = 0;
13964   IADDR UNUSED pc = abuf->addr;
13965   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13966
13967 {
13968   {
13969     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 1));
13970     SET_H_PREFIXREG_V32 (opval);
13971     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13972   }
13973   {
13974     BI opval = 1;
13975     SET_H_INSN_PREFIXED_P (opval);
13976     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
13977   }
13978 }
13979
13980 #undef FLD
13981 }
13982   NEXT (vpc);
13983
13984   CASE (sem, INSN_ADDI_ACR_W_R) : /* addi-acr.w ${Rs-dfield}.m,${Rd-sfield},ACR */
13985 {
13986   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
13987   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
13988 #define FLD(f) abuf->fields.sfmt_muls_b.f
13989   int UNUSED written = 0;
13990   IADDR UNUSED pc = abuf->addr;
13991   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
13992
13993 {
13994   {
13995     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 2));
13996     SET_H_PREFIXREG_V32 (opval);
13997     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
13998   }
13999   {
14000     BI opval = 1;
14001     SET_H_INSN_PREFIXED_P (opval);
14002     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
14003   }
14004 }
14005
14006 #undef FLD
14007 }
14008   NEXT (vpc);
14009
14010   CASE (sem, INSN_ADDI_ACR_D_R) : /* addi-acr.d ${Rs-dfield}.m,${Rd-sfield},ACR */
14011 {
14012   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14013   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14014 #define FLD(f) abuf->fields.sfmt_muls_b.f
14015   int UNUSED written = 0;
14016   IADDR UNUSED pc = abuf->addr;
14017   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14018
14019 {
14020   {
14021     SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 4));
14022     SET_H_PREFIXREG_V32 (opval);
14023     TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
14024   }
14025   {
14026     BI opval = 1;
14027     SET_H_INSN_PREFIXED_P (opval);
14028     TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
14029   }
14030 }
14031
14032 #undef FLD
14033 }
14034   NEXT (vpc);
14035
14036   CASE (sem, INSN_FIDXI) : /* fidxi [$Rs] */
14037 {
14038   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14039   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14040 #define FLD(f) abuf->fields.sfmt_mcp.f
14041   int UNUSED written = 0;
14042   IADDR UNUSED pc = abuf->addr;
14043   SEM_BRANCH_INIT
14044   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14045
14046   {
14047     USI opval = crisv32f_fidxi_handler (current_cpu, pc, GET_H_GR (FLD (f_operand1)));
14048     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
14049     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
14050   }
14051
14052   SEM_BRANCH_FINI (vpc);
14053 #undef FLD
14054 }
14055   NEXT (vpc);
14056
14057   CASE (sem, INSN_FTAGI) : /* fidxi [$Rs] */
14058 {
14059   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14060   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14061 #define FLD(f) abuf->fields.sfmt_mcp.f
14062   int UNUSED written = 0;
14063   IADDR UNUSED pc = abuf->addr;
14064   SEM_BRANCH_INIT
14065   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14066
14067   {
14068     USI opval = crisv32f_ftagi_handler (current_cpu, pc, GET_H_GR (FLD (f_operand1)));
14069     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
14070     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
14071   }
14072
14073   SEM_BRANCH_FINI (vpc);
14074 #undef FLD
14075 }
14076   NEXT (vpc);
14077
14078   CASE (sem, INSN_FIDXD) : /* fidxd [$Rs] */
14079 {
14080   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14081   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14082 #define FLD(f) abuf->fields.sfmt_mcp.f
14083   int UNUSED written = 0;
14084   IADDR UNUSED pc = abuf->addr;
14085   SEM_BRANCH_INIT
14086   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14087
14088   {
14089     USI opval = crisv32f_fidxd_handler (current_cpu, pc, GET_H_GR (FLD (f_operand1)));
14090     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
14091     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
14092   }
14093
14094   SEM_BRANCH_FINI (vpc);
14095 #undef FLD
14096 }
14097   NEXT (vpc);
14098
14099   CASE (sem, INSN_FTAGD) : /* ftagd [$Rs] */
14100 {
14101   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
14102   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
14103 #define FLD(f) abuf->fields.sfmt_mcp.f
14104   int UNUSED written = 0;
14105   IADDR UNUSED pc = abuf->addr;
14106   SEM_BRANCH_INIT
14107   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
14108
14109   {
14110     USI opval = crisv32f_ftagd_handler (current_cpu, pc, GET_H_GR (FLD (f_operand1)));
14111     SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
14112     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
14113   }
14114
14115   SEM_BRANCH_FINI (vpc);
14116 #undef FLD
14117 }
14118   NEXT (vpc);
14119
14120
14121     }
14122   ENDSWITCH (sem) /* End of semantic switch.  */
14123
14124   /* At this point `vpc' contains the next insn to execute.  */
14125 }
14126
14127 #undef DEFINE_SWITCH
14128 #endif /* DEFINE_SWITCH */