9 #include "sys/syscall.h"
35 static void trace_input
PARAMS ((char *name
,
40 static void trace_output
PARAMS ((enum op_types result
));
42 #ifndef SIZE_INSTRUCTION
43 #define SIZE_INSTRUCTION 10
47 #define SIZE_OPERANDS 24
51 #define SIZE_VALUES 13
55 trace_input (name
, in1
, in2
, in3
)
69 if ((d10v_debug
& DEBUG_TRACE
) == 0)
72 switch (State
.ins_type
)
75 case INS_UNKNOWN
: type
= " ?"; break;
76 case INS_LEFT
: type
= " L"; break;
77 case INS_RIGHT
: type
= " R"; break;
78 case INS_LEFT_PARALLEL
: type
= "*L"; break;
79 case INS_RIGHT_PARALLEL
: type
= "*R"; break;
80 case INS_LONG
: type
= " B"; break;
83 (*d10v_callback
->printf_filtered
) (d10v_callback
,
86 SIZE_INSTRUCTION
, name
);
93 for (i
= 0; i
< 3; i
++)
104 sprintf (p
, "%sr%d", comma
, OP
[i
]);
112 sprintf (p
, "%scr%d", comma
, OP
[i
]);
118 case OP_ACCUM_OUTPUT
:
119 case OP_ACCUM_REVERSE
:
120 sprintf (p
, "%sa%d", comma
, OP
[i
]);
126 sprintf (p
, "%s%d", comma
, OP
[i
]);
132 sprintf (p
, "%s%d", comma
, SEXT4(OP
[i
]));
138 sprintf (p
, "%s%d", comma
, SEXT3(OP
[i
]));
144 sprintf (p
, "%s@r%d", comma
, OP
[i
]);
150 sprintf (p
, "%s@(%d,r%d)", comma
, (int16
)OP
[i
], OP
[i
+1]);
156 sprintf (p
, "%s@r%d+", comma
, OP
[i
]);
162 sprintf (p
, "%s@r%d-", comma
, OP
[i
]);
168 sprintf (p
, "%s@-r%d", comma
, OP
[i
]);
175 sprintf (p
, "%sf0", comma
);
178 sprintf (p
, "%sf1", comma
);
181 sprintf (p
, "%scarry", comma
);
189 if ((d10v_debug
& DEBUG_VALUES
) == 0)
193 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%s", buf
);
198 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%-*s", SIZE_OPERANDS
, buf
);
201 for (i
= 0; i
< 3; i
++)
207 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s", SIZE_VALUES
, "");
213 case OP_ACCUM_OUTPUT
:
214 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s", SIZE_VALUES
, "---");
222 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
223 (uint16
)State
.regs
[OP
[i
]]);
227 tmp
= (long)((((uint32
) State
.regs
[OP
[i
]]) << 16) | ((uint32
) State
.regs
[OP
[i
]+1]));
228 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.8lx", SIZE_VALUES
-10, "", tmp
);
233 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
234 (uint16
)State
.cregs
[OP
[i
]]);
238 case OP_ACCUM_REVERSE
:
239 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.2x%.8lx", SIZE_VALUES
-12, "",
240 ((int)(State
.a
[OP
[i
]] >> 32) & 0xff),
241 ((unsigned long)State
.a
[OP
[i
]]) & 0xffffffff);
245 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
250 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
251 (uint16
)SEXT4(OP
[i
]));
255 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
256 (uint16
)SEXT3(OP
[i
]));
261 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sF0 = %d", SIZE_VALUES
-6, "",
265 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sF1 = %d", SIZE_VALUES
-6, "",
269 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sC = %d", SIZE_VALUES
-5, "",
275 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
277 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
278 (uint16
)State
.regs
[OP
[++i
]]);
286 trace_output (result
)
287 enum op_types result
;
289 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
301 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
302 (uint16
)State
.regs
[OP
[0]],
303 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
308 tmp
= (long)((((uint32
) State
.regs
[OP
[0]]) << 16) | ((uint32
) State
.regs
[OP
[0]+1]));
309 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES
-10, "", tmp
,
310 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
315 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
316 (uint16
)State
.cregs
[OP
[0]],
317 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
321 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
322 (uint16
)State
.cregs
[OP
[1]],
323 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
327 case OP_ACCUM_OUTPUT
:
328 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES
-10, "",
329 ((int)(State
.a
[OP
[0]] >> 32) & 0xff),
330 ((unsigned long)State
.a
[OP
[0]]) & 0xffffffff,
331 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
334 case OP_ACCUM_REVERSE
:
335 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES
-10, "",
336 ((int)(State
.a
[OP
[1]] >> 32) & 0xff),
337 ((unsigned long)State
.a
[OP
[1]]) & 0xffffffff,
338 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
342 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES
, "",
343 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
350 #define trace_input(NAME, IN1, IN2, IN3)
351 #define trace_output(RESULT)
358 trace_input ("abs", OP_REG
, OP_VOID
, OP_VOID
);
360 if ((int16
)(State
.regs
[OP
[0]]) < 0)
362 State
.regs
[OP
[0]] = -(int16
)(State
.regs
[OP
[0]]);
367 trace_output (OP_REG
);
376 trace_input ("abs", OP_ACCUM
, OP_VOID
, OP_VOID
);
378 State
.a
[OP
[0]] = SEXT40(State
.a
[OP
[0]]);
380 if (State
.a
[OP
[0]] < 0 )
382 tmp
= -State
.a
[OP
[0]];
386 State
.a
[OP
[0]] = MAX32
;
387 else if (tmp
< MIN32
)
388 State
.a
[OP
[0]] = MIN32
;
390 State
.a
[OP
[0]] = tmp
& MASK40
;
393 State
.a
[OP
[0]] = tmp
& MASK40
;
398 trace_output (OP_ACCUM
);
405 uint16 tmp
= State
.regs
[OP
[0]];
406 trace_input ("add", OP_REG
, OP_REG
, OP_VOID
);
407 State
.regs
[OP
[0]] += State
.regs
[OP
[1]];
408 if ( tmp
> State
.regs
[OP
[0]])
412 trace_output (OP_REG
);
420 tmp
= SEXT40(State
.a
[OP
[0]]) + (SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1]);
422 trace_input ("add", OP_ACCUM
, OP_REG
, OP_VOID
);
426 State
.a
[OP
[0]] = MAX32
;
427 else if ( tmp
< MIN32
)
428 State
.a
[OP
[0]] = MIN32
;
430 State
.a
[OP
[0]] = tmp
& MASK40
;
433 State
.a
[OP
[0]] = tmp
& MASK40
;
434 trace_output (OP_ACCUM
);
442 tmp
= SEXT40(State
.a
[OP
[0]]) + SEXT40(State
.a
[OP
[1]]);
444 trace_input ("add", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
448 State
.a
[OP
[0]] = MAX32
;
449 else if ( tmp
< MIN32
)
450 State
.a
[OP
[0]] = MIN32
;
452 State
.a
[OP
[0]] = tmp
& MASK40
;
455 State
.a
[OP
[0]] = tmp
& MASK40
;
456 trace_output (OP_ACCUM
);
464 uint32 tmp1
= (State
.regs
[OP
[0]]) << 16 | State
.regs
[OP
[0]+1];
465 uint32 tmp2
= (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
467 trace_input ("add2w", OP_DREG
, OP_DREG
, OP_VOID
);
469 if ( (tmp
< tmp1
) || (tmp
< tmp2
) )
473 State
.regs
[OP
[0]] = tmp
>> 16;
474 State
.regs
[OP
[0]+1] = tmp
& 0xFFFF;
475 trace_output (OP_DREG
);
482 uint16 tmp
= State
.regs
[OP
[0]];
483 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] + OP
[2];
485 trace_input ("add3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
486 if ( tmp
> State
.regs
[OP
[0]])
490 trace_output (OP_REG
);
498 tmp
= SEXT40(State
.a
[OP
[2]]) + SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
500 trace_input ("addac3", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
501 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
502 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
503 trace_output (OP_DREG
);
511 tmp
= SEXT40(State
.a
[OP
[1]]) + SEXT40(State
.a
[OP
[2]]);
513 trace_input ("addac3", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
514 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
515 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
516 trace_output (OP_DREG
);
526 trace_input ("addac3s", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
527 tmp
= SEXT40(State
.a
[OP
[2]]) + SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
530 State
.regs
[OP
[0]] = 0x7fff;
531 State
.regs
[OP
[0]+1] = 0xffff;
534 else if (tmp
< MIN32
)
536 State
.regs
[OP
[0]] = 0x8000;
537 State
.regs
[OP
[0]+1] = 0;
542 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
543 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
546 trace_output (OP_DREG
);
556 trace_input ("addac3s", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
557 tmp
= SEXT40(State
.a
[OP
[1]]) + SEXT40(State
.a
[OP
[2]]);
560 State
.regs
[OP
[0]] = 0x7fff;
561 State
.regs
[OP
[0]+1] = 0xffff;
564 else if (tmp
< MIN32
)
566 State
.regs
[OP
[0]] = 0x8000;
567 State
.regs
[OP
[0]+1] = 0;
572 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
573 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
576 trace_output (OP_DREG
);
585 trace_input ("addi", OP_REG
, OP_CONSTANT16
, OP_VOID
);
586 State
.regs
[OP
[0]] += OP
[1];
587 trace_output (OP_REG
);
594 trace_input ("and", OP_REG
, OP_REG
, OP_VOID
);
595 State
.regs
[OP
[0]] &= State
.regs
[OP
[1]];
596 trace_output (OP_REG
);
603 trace_input ("and3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
604 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] & OP
[2];
605 trace_output (OP_REG
);
612 trace_input ("bclri", OP_REG
, OP_CONSTANT16
, OP_VOID
);
613 State
.regs
[OP
[0]] &= ~(0x8000 >> OP
[1]);
614 trace_output (OP_REG
);
621 trace_input ("bl.s", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
622 State
.regs
[13] = PC
+1;
624 trace_output (OP_VOID
);
631 trace_input ("bl.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
632 State
.regs
[13] = PC
+1;
634 trace_output (OP_VOID
);
641 trace_input ("bnoti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
642 State
.regs
[OP
[0]] ^= 0x8000 >> OP
[1];
643 trace_output (OP_REG
);
650 trace_input ("bra.s", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
652 trace_output (OP_VOID
);
659 trace_input ("bra.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
661 trace_output (OP_VOID
);
668 trace_input ("brf0f.s", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
671 trace_output (OP_FLAG
);
678 trace_input ("brf0f.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
681 trace_output (OP_FLAG
);
688 trace_input ("brf0t.s", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
691 trace_output (OP_FLAG
);
698 trace_input ("brf0t.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
701 trace_output (OP_FLAG
);
708 trace_input ("bseti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
709 State
.regs
[OP
[0]] |= 0x8000 >> OP
[1];
710 trace_output (OP_REG
);
717 trace_input ("btsti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
719 State
.F0
= (State
.regs
[OP
[0]] & (0x8000 >> OP
[1])) ? 1 : 0;
720 trace_output (OP_FLAG
);
727 trace_input ("clrac", OP_ACCUM_OUTPUT
, OP_VOID
, OP_VOID
);
729 trace_output (OP_ACCUM
);
736 trace_input ("cmp", OP_REG
, OP_REG
, OP_VOID
);
738 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)(State
.regs
[OP
[1]])) ? 1 : 0;
739 trace_output (OP_FLAG
);
746 trace_input ("cmp", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
748 State
.F0
= (SEXT40(State
.a
[OP
[0]]) < SEXT40(State
.a
[OP
[1]])) ? 1 : 0;
749 trace_output (OP_FLAG
);
756 trace_input ("cmpeq", OP_REG
, OP_REG
, OP_VOID
);
758 State
.F0
= (State
.regs
[OP
[0]] == State
.regs
[OP
[1]]) ? 1 : 0;
759 trace_output (OP_FLAG
);
766 trace_input ("cmpeq", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
768 State
.F0
= (State
.a
[OP
[0]] == State
.a
[OP
[1]]) ? 1 : 0;
769 trace_output (OP_FLAG
);
776 trace_input ("cmpeqi.s", OP_REG
, OP_CONSTANT16
, OP_VOID
);
778 State
.F0
= (State
.regs
[OP
[0]] == SEXT4(OP
[1])) ? 1 : 0;
779 trace_output (OP_FLAG
);
786 trace_input ("cmpeqi.l", OP_REG
, OP_CONSTANT16
, OP_VOID
);
788 State
.F0
= (State
.regs
[OP
[0]] == OP
[1]) ? 1 : 0;
789 trace_output (OP_FLAG
);
796 trace_input ("cmpi.s", OP_REG
, OP_CONSTANT4
, OP_VOID
);
798 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < SEXT4(OP
[1])) ? 1 : 0;
799 trace_output (OP_FLAG
);
806 trace_input ("cmpi.l", OP_REG
, OP_CONSTANT16
, OP_VOID
);
808 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)(OP
[1])) ? 1 : 0;
809 trace_output (OP_FLAG
);
816 trace_input ("cmpu", OP_REG
, OP_REG
, OP_VOID
);
818 State
.F0
= (State
.regs
[OP
[0]] < State
.regs
[OP
[1]]) ? 1 : 0;
819 trace_output (OP_FLAG
);
826 trace_input ("cmpui", OP_REG
, OP_CONSTANT16
, OP_VOID
);
828 State
.F0
= (State
.regs
[OP
[0]] < OP
[1]) ? 1 : 0;
829 trace_output (OP_FLAG
);
838 trace_input ("cpfg", OP_FLAG
, OP_VOID
, OP_VOID
);
852 trace_output (OP_FLAG
);
859 d10v_callback
->printf_filtered(d10v_callback
, "***** DBT ***** PC=%x\n",PC
);
860 State
.exception
= SIGTRAP
;
867 uint16 foo
, tmp
, tmpf
;
869 trace_input ("divs", OP_DREG
, OP_REG
, OP_VOID
);
870 foo
= (State
.regs
[OP
[0]] << 1) | (State
.regs
[OP
[0]+1] >> 15);
871 tmp
= (int16
)foo
- (int16
)(State
.regs
[OP
[1]]);
872 tmpf
= (foo
>= State
.regs
[OP
[1]]) ? 1 : 0;
873 State
.regs
[OP
[0]] = (tmpf
== 1) ? tmp
: foo
;
874 State
.regs
[OP
[0]+1] = (State
.regs
[OP
[0]+1] << 1) | tmpf
;
875 trace_output (OP_DREG
);
882 trace_input ("exef0f", OP_VOID
, OP_VOID
, OP_VOID
);
883 State
.exe
= (State
.F0
) ? 0 : 1;
884 trace_output (OP_FLAG
);
891 trace_input ("exef0t", OP_VOID
, OP_VOID
, OP_VOID
);
892 State
.exe
= State
.F0
;
893 trace_output (OP_FLAG
);
900 trace_input ("exef1f", OP_VOID
, OP_VOID
, OP_VOID
);
901 State
.exe
= (State
.F1
) ? 0 : 1;
902 trace_output (OP_FLAG
);
909 trace_input ("exef1t", OP_VOID
, OP_VOID
, OP_VOID
);
910 State
.exe
= State
.F1
;
911 trace_output (OP_FLAG
);
918 trace_input ("exefaf", OP_VOID
, OP_VOID
, OP_VOID
);
919 State
.exe
= (State
.F0
| State
.F1
) ? 0 : 1;
920 trace_output (OP_FLAG
);
927 trace_input ("exefat", OP_VOID
, OP_VOID
, OP_VOID
);
928 State
.exe
= (State
.F0
) ? 0 : (State
.F1
);
929 trace_output (OP_FLAG
);
936 trace_input ("exetaf", OP_VOID
, OP_VOID
, OP_VOID
);
937 State
.exe
= (State
.F1
) ? 0 : (State
.F0
);
938 trace_output (OP_FLAG
);
945 trace_input ("exetat", OP_VOID
, OP_VOID
, OP_VOID
);
946 State
.exe
= (State
.F0
) ? (State
.F1
) : 0;
947 trace_output (OP_FLAG
);
957 trace_input ("exp", OP_REG_OUTPUT
, OP_DREG
, OP_VOID
);
958 if (((int16
)State
.regs
[OP
[1]]) >= 0)
959 tmp
= (State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1];
961 tmp
= ~((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
968 State
.regs
[OP
[0]] = i
-1;
969 trace_output (OP_REG
);
974 State
.regs
[OP
[0]] = 16;
975 trace_output (OP_REG
);
985 trace_input ("exp", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
986 if (SEXT40(State
.a
[OP
[1]]) >= 0)
987 tmp
= State
.a
[OP
[1]];
989 tmp
= ~(State
.a
[OP
[1]]);
991 foo
= 0x4000000000LL
;
996 State
.regs
[OP
[0]] = i
-9;
997 trace_output (OP_REG
);
1002 State
.regs
[OP
[0]] = 16;
1003 trace_output (OP_REG
);
1010 trace_input ("jl", OP_REG
, OP_VOID
, OP_VOID
);
1011 State
.regs
[13] = PC
+1;
1012 PC
= State
.regs
[OP
[0]];
1013 trace_output (OP_VOID
);
1020 trace_input ("jmp", OP_REG
, OP_VOID
, OP_VOID
);
1021 PC
= State
.regs
[OP
[0]];
1022 trace_output (OP_VOID
);
1029 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1030 State
.regs
[OP
[0]] = RW (OP
[1] + State
.regs
[OP
[2]]);
1031 trace_output (OP_REG
);
1038 trace_input ("ld", OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1039 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1040 INC_ADDR(State
.regs
[OP
[1]],-2);
1041 trace_output (OP_REG
);
1048 trace_input ("ld", OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1049 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1050 INC_ADDR(State
.regs
[OP
[1]],2);
1051 trace_output (OP_REG
);
1058 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1059 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1060 trace_output (OP_REG
);
1067 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1068 State
.regs
[OP
[0]] = RW (OP
[1] + State
.regs
[OP
[2]]);
1069 State
.regs
[OP
[0]+1] = RW (OP
[1] + State
.regs
[OP
[2]] + 2);
1070 trace_output (OP_DREG
);
1077 trace_input ("ld2w", OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1078 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1079 State
.regs
[OP
[0]+1] = RW (State
.regs
[OP
[1]]+2);
1080 INC_ADDR(State
.regs
[OP
[1]],-4);
1081 trace_output (OP_DREG
);
1088 trace_input ("ld2w", OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1089 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1090 State
.regs
[OP
[0]+1] = RW (State
.regs
[OP
[1]]+2);
1091 INC_ADDR(State
.regs
[OP
[1]],4);
1092 trace_output (OP_REG
);
1099 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1100 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1101 State
.regs
[OP
[0]+1] = RW (State
.regs
[OP
[1]]+2);
1102 trace_output (OP_REG
);
1109 trace_input ("ldb", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1110 State
.regs
[OP
[0]] = RB (OP
[1] + State
.regs
[OP
[2]]);
1111 SEXT8 (State
.regs
[OP
[0]]);
1112 trace_output (OP_REG
);
1119 trace_input ("ldb", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1120 State
.regs
[OP
[0]] = RB (State
.regs
[OP
[1]]);
1121 SEXT8 (State
.regs
[OP
[0]]);
1122 trace_output (OP_REG
);
1129 trace_input ("ldi.s", OP_REG_OUTPUT
, OP_CONSTANT4
, OP_VOID
);
1130 State
.regs
[OP
[0]] = SEXT4(OP
[1]);
1131 trace_output (OP_REG
);
1138 trace_input ("ldi.s", OP_REG_OUTPUT
, OP_CONSTANT16
, OP_VOID
);
1139 State
.regs
[OP
[0]] = OP
[1];
1140 trace_output (OP_REG
);
1147 trace_input ("ldub", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1148 State
.regs
[OP
[0]] = RB (OP
[1] + State
.regs
[OP
[2]]);
1149 trace_output (OP_REG
);
1156 trace_input ("ldub", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1157 State
.regs
[OP
[0]] = RB (State
.regs
[OP
[1]]);
1158 trace_output (OP_REG
);
1167 trace_input ("mac", OP_ACCUM
, OP_REG
, OP_REG
);
1168 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1171 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1173 if (State
.ST
&& tmp
> MAX32
)
1176 tmp
+= SEXT40(State
.a
[OP
[0]]);
1180 State
.a
[OP
[0]] = MAX32
;
1181 else if (tmp
< MIN32
)
1182 State
.a
[OP
[0]] = MIN32
;
1184 State
.a
[OP
[0]] = tmp
& MASK40
;
1187 State
.a
[OP
[0]] = tmp
& MASK40
;
1188 trace_output (OP_ACCUM
);
1197 trace_input ("macsu", OP_ACCUM
, OP_REG
, OP_REG
);
1198 tmp
= SEXT40 ((int16
)State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1200 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1202 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) + tmp
) & MASK40
;
1203 trace_output (OP_ACCUM
);
1212 trace_input ("macu", OP_ACCUM
, OP_REG
, OP_REG
);
1213 tmp
= SEXT40 (State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1215 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1216 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) + tmp
) & MASK40
;
1217 trace_output (OP_ACCUM
);
1224 trace_input ("max", OP_REG
, OP_REG
, OP_VOID
);
1225 State
.F1
= State
.F0
;
1226 if (State
.regs
[OP
[1]] > State
.regs
[OP
[0]])
1228 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1233 trace_output (OP_REG
);
1242 trace_input ("max", OP_ACCUM
, OP_DREG
, OP_VOID
);
1243 State
.F1
= State
.F0
;
1244 tmp
= SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
1245 if (tmp
> SEXT40(State
.a
[OP
[0]]))
1247 State
.a
[OP
[0]] = tmp
& MASK40
;
1252 trace_output (OP_ACCUM
);
1259 trace_input ("max", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1260 State
.F1
= State
.F0
;
1261 if (SEXT40(State
.a
[OP
[1]]) > SEXT40(State
.a
[OP
[0]]))
1263 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1268 trace_output (OP_ACCUM
);
1276 trace_input ("min", OP_REG
, OP_REG
, OP_VOID
);
1277 State
.F1
= State
.F0
;
1278 if (State
.regs
[OP
[1]] < State
.regs
[OP
[0]])
1280 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1285 trace_output (OP_REG
);
1294 trace_input ("min", OP_ACCUM
, OP_DREG
, OP_VOID
);
1295 State
.F1
= State
.F0
;
1296 tmp
= SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
1297 if (tmp
< SEXT40(State
.a
[OP
[0]]))
1299 State
.a
[OP
[0]] = tmp
& MASK40
;
1304 trace_output (OP_ACCUM
);
1311 trace_input ("min", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1312 State
.F1
= State
.F0
;
1313 if (SEXT40(State
.a
[OP
[1]]) < SEXT40(State
.a
[OP
[0]]))
1315 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1320 trace_output (OP_ACCUM
);
1329 trace_input ("msb", OP_ACCUM
, OP_REG
, OP_REG
);
1330 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1333 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1335 if (State
.ST
&& tmp
> MAX32
)
1338 tmp
= SEXT40(State
.a
[OP
[0]]) - tmp
;
1342 State
.a
[OP
[0]] = MAX32
;
1343 else if (tmp
< MIN32
)
1344 State
.a
[OP
[0]] = MIN32
;
1346 State
.a
[OP
[0]] = tmp
& MASK40
;
1349 State
.a
[OP
[0]] = tmp
& MASK40
;
1350 trace_output (OP_ACCUM
);
1359 trace_input ("msbsu", OP_ACCUM
, OP_REG
, OP_REG
);
1360 tmp
= SEXT40 ((int16
)State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1362 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1364 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) - tmp
) & MASK40
;
1365 trace_output (OP_ACCUM
);
1374 trace_input ("msbu", OP_ACCUM
, OP_REG
, OP_REG
);
1375 tmp
= SEXT40 (State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1377 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1379 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) - tmp
) & MASK40
;
1380 trace_output (OP_ACCUM
);
1387 trace_input ("mul", OP_REG
, OP_REG
, OP_VOID
);
1388 State
.regs
[OP
[0]] *= State
.regs
[OP
[1]];
1389 trace_output (OP_REG
);
1398 trace_input ("mulx", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1399 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1402 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1404 if (State
.ST
&& tmp
> MAX32
)
1405 State
.a
[OP
[0]] = MAX32
;
1407 State
.a
[OP
[0]] = tmp
& MASK40
;
1408 trace_output (OP_ACCUM
);
1417 trace_input ("mulxsu", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1418 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * State
.regs
[OP
[2]]);
1423 State
.a
[OP
[0]] = tmp
& MASK40
;
1424 trace_output (OP_ACCUM
);
1433 trace_input ("mulxu", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1434 tmp
= SEXT40 (State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1439 State
.a
[OP
[0]] = tmp
& MASK40
;
1440 trace_output (OP_ACCUM
);
1447 trace_input ("mv", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1448 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1449 trace_output (OP_REG
);
1456 trace_input ("mv2w", OP_DREG_OUTPUT
, OP_DREG
, OP_VOID
);
1457 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1458 State
.regs
[OP
[0]+1] = State
.regs
[OP
[1]+1];
1459 trace_output (OP_DREG
);
1466 trace_input ("mv2wfac", OP_DREG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1467 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 16) & 0xffff;
1468 State
.regs
[OP
[0]+1] = State
.a
[OP
[1]] & 0xffff;
1469 trace_output (OP_DREG
);
1476 trace_input ("mv2wtac", OP_ACCUM_OUTPUT
, OP_DREG
, OP_VOID
);
1477 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]]) << 16 | State
.regs
[OP
[0]+1]) & MASK40
;
1478 trace_output (OP_ACCUM
);
1485 trace_input ("mvac", OP_ACCUM_OUTPUT
, OP_ACCUM
, OP_VOID
);
1486 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1487 trace_output (OP_ACCUM
);
1494 trace_input ("mvb", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1495 State
.regs
[OP
[0]] = SEXT8 (State
.regs
[OP
[1]] & 0xff);
1496 trace_output (OP_REG
);
1503 trace_input ("mf0f", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1505 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1506 trace_output (OP_REG
);
1513 trace_input ("mf0t", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1515 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1516 trace_output (OP_REG
);
1523 trace_input ("mvfacg", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1524 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 32) & 0xff;
1525 trace_output (OP_ACCUM
);
1532 trace_input ("mvfachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1533 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 16) & 0xffff;
1534 trace_output (OP_REG
);
1541 trace_input ("mvfaclo", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1542 State
.regs
[OP
[0]] = State
.a
[OP
[1]] & 0xffff;
1543 trace_output (OP_REG
);
1550 trace_input ("mvfc", OP_REG_OUTPUT
, OP_CR
, OP_VOID
);
1553 /* PSW is treated specially */
1555 if (State
.SM
) PSW
|= 0x8000;
1556 if (State
.EA
) PSW
|= 0x2000;
1557 if (State
.DB
) PSW
|= 0x1000;
1558 if (State
.IE
) PSW
|= 0x400;
1559 if (State
.RP
) PSW
|= 0x200;
1560 if (State
.MD
) PSW
|= 0x100;
1561 if (State
.FX
) PSW
|= 0x80;
1562 if (State
.ST
) PSW
|= 0x40;
1563 if (State
.F0
) PSW
|= 8;
1564 if (State
.F1
) PSW
|= 4;
1565 if (State
.C
) PSW
|= 1;
1567 State
.regs
[OP
[0]] = State
.cregs
[OP
[1]];
1568 trace_output (OP_REG
);
1575 trace_input ("mvtacg", OP_REG
, OP_ACCUM
, OP_VOID
);
1576 State
.a
[OP
[1]] &= MASK32
;
1577 State
.a
[OP
[1]] |= (int64
)(State
.regs
[OP
[0]] & 0xff) << 32;
1578 trace_output (OP_ACCUM_REVERSE
);
1587 trace_input ("mvtachi", OP_REG
, OP_ACCUM
, OP_VOID
);
1588 tmp
= State
.a
[OP
[1]] & 0xffff;
1589 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]]) << 16 | tmp
) & MASK40
;
1590 trace_output (OP_ACCUM_REVERSE
);
1597 trace_input ("mvtaclo", OP_REG
, OP_ACCUM
, OP_VOID
);
1598 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]])) & MASK40
;
1599 trace_output (OP_ACCUM_REVERSE
);
1606 trace_input ("mvtc", OP_REG
, OP_CR_OUTPUT
, OP_VOID
);
1607 State
.cregs
[OP
[1]] = State
.regs
[OP
[0]];
1610 /* PSW is treated specially */
1611 State
.SM
= (PSW
& 0x8000) ? 1 : 0;
1612 State
.EA
= (PSW
& 0x2000) ? 1 : 0;
1613 State
.DB
= (PSW
& 0x1000) ? 1 : 0;
1614 State
.IE
= (PSW
& 0x400) ? 1 : 0;
1615 State
.RP
= (PSW
& 0x200) ? 1 : 0;
1616 State
.MD
= (PSW
& 0x100) ? 1 : 0;
1617 State
.FX
= (PSW
& 0x80) ? 1 : 0;
1618 State
.ST
= (PSW
& 0x40) ? 1 : 0;
1619 State
.F0
= (PSW
& 8) ? 1 : 0;
1620 State
.F1
= (PSW
& 4) ? 1 : 0;
1622 if (State
.ST
&& !State
.FX
)
1624 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1625 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
1627 State
.exception
= SIGILL
;
1630 trace_output (OP_CR_REVERSE
);
1637 trace_input ("mvub", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1638 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] & 0xff;
1639 trace_output (OP_REG
);
1646 trace_input ("neg", OP_REG
, OP_VOID
, OP_VOID
);
1647 State
.regs
[OP
[0]] = 0 - State
.regs
[OP
[0]];
1648 trace_output (OP_REG
);
1657 trace_input ("neg", OP_ACCUM
, OP_VOID
, OP_VOID
);
1658 tmp
= -SEXT40(State
.a
[OP
[0]]);
1662 State
.a
[OP
[0]] = MAX32
;
1663 else if (tmp
< MIN32
)
1664 State
.a
[OP
[0]] = MIN32
;
1666 State
.a
[OP
[0]] = tmp
& MASK40
;
1669 State
.a
[OP
[0]] = tmp
& MASK40
;
1670 trace_output (OP_ACCUM
);
1678 trace_input ("nop", OP_VOID
, OP_VOID
, OP_VOID
);
1679 trace_output (OP_VOID
);
1681 if (State
.ins_type
== INS_LEFT
|| State
.ins_type
== INS_LEFT_PARALLEL
)
1691 trace_input ("not", OP_REG
, OP_VOID
, OP_VOID
);
1692 State
.regs
[OP
[0]] = ~(State
.regs
[OP
[0]]);
1693 trace_output (OP_REG
);
1700 trace_input ("or", OP_REG
, OP_REG
, OP_VOID
);
1701 State
.regs
[OP
[0]] |= State
.regs
[OP
[1]];
1702 trace_output (OP_REG
);
1709 trace_input ("or3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
1710 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] | OP
[2];
1711 trace_output (OP_REG
);
1719 int shift
= SEXT3 (OP
[2]);
1721 trace_input ("rac", OP_DREG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
1724 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1725 "ERROR at PC 0x%x: instruction only valid for A0\n",
1727 State
.exception
= SIGILL
;
1730 State
.F1
= State
.F0
;
1732 tmp
= ((State
.a
[0] << 16) | (State
.a
[1] & 0xffff)) << shift
;
1734 tmp
= ((State
.a
[0] << 16) | (State
.a
[1] & 0xffff)) >> -shift
;
1735 tmp
= ( SEXT60(tmp
) + 0x8000 ) >> 16;
1738 State
.regs
[OP
[0]] = 0x7fff;
1739 State
.regs
[OP
[0]+1] = 0xffff;
1742 else if (tmp
< MIN32
)
1744 State
.regs
[OP
[0]] = 0x8000;
1745 State
.regs
[OP
[0]+1] = 0;
1750 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
1751 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
1754 trace_output (OP_DREG
);
1762 int shift
= SEXT3 (OP
[2]);
1764 trace_input ("rachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
1765 State
.F1
= State
.F0
;
1767 tmp
= SEXT44 (State
.a
[1]) << shift
;
1769 tmp
= SEXT44 (State
.a
[1]) >> -shift
;
1774 State
.regs
[OP
[0]] = 0x7fff;
1777 else if (tmp
< 0xfff80000000LL
)
1779 State
.regs
[OP
[0]] = 0x8000;
1784 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
1787 trace_output (OP_REG
);
1794 trace_input ("rep", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1797 RPT_C
= State
.regs
[OP
[0]];
1801 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: rep with count=0 is illegal.\n");
1802 State
.exception
= SIGILL
;
1806 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: rep must include at least 4 instructions.\n");
1807 State
.exception
= SIGILL
;
1809 trace_output (OP_VOID
);
1816 trace_input ("repi", OP_CONSTANT16
, OP_CONSTANT16
, OP_VOID
);
1823 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: repi with count=0 is illegal.\n");
1824 State
.exception
= SIGILL
;
1828 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: repi must include at least 4 instructions.\n");
1829 State
.exception
= SIGILL
;
1831 trace_output (OP_VOID
);
1838 d10v_callback
->printf_filtered(d10v_callback
, "ERROR: rtd - NOT IMPLEMENTED\n");
1839 State
.exception
= SIGILL
;
1846 trace_input ("rte", OP_VOID
, OP_VOID
, OP_VOID
);
1849 trace_output (OP_VOID
);
1858 trace_input ("sadd", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1859 tmp
= SEXT40(State
.a
[OP
[0]]) + (SEXT40(State
.a
[OP
[1]]) >> 16);
1863 State
.a
[OP
[0]] = MAX32
;
1864 else if (tmp
< MIN32
)
1865 State
.a
[OP
[0]] = MIN32
;
1867 State
.a
[OP
[0]] = tmp
& MASK40
;
1870 State
.a
[OP
[0]] = tmp
& MASK40
;
1871 trace_output (OP_ACCUM
);
1878 trace_input ("setf0f", OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
1879 State
.regs
[OP
[0]] = (State
.F0
== 0) ? 1 : 0;
1880 trace_output (OP_REG
);
1887 trace_input ("setf0t", OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
1888 State
.regs
[OP
[0]] = (State
.F0
== 1) ? 1 : 0;
1889 trace_output (OP_REG
);
1896 trace_input ("sleep", OP_VOID
, OP_VOID
, OP_VOID
);
1898 trace_output (OP_VOID
);
1905 trace_input ("sll", OP_REG
, OP_REG
, OP_VOID
);
1906 State
.regs
[OP
[0]] <<= (State
.regs
[OP
[1]] & 0xf);
1907 trace_output (OP_REG
);
1915 trace_input ("sll", OP_ACCUM
, OP_REG
, OP_VOID
);
1916 if (State
.regs
[OP
[1]] & 31 <= 16)
1917 tmp
= SEXT40 (State
.a
[OP
[0]]) << (State
.regs
[OP
[1]] & 31);
1922 State
.a
[OP
[0]] = MAX32
;
1923 else if (tmp
< 0xffffff80000000LL
)
1924 State
.a
[OP
[0]] = MIN32
;
1926 State
.a
[OP
[0]] = tmp
& MASK40
;
1929 State
.a
[OP
[0]] = tmp
& MASK40
;
1930 trace_output (OP_ACCUM
);
1937 trace_input ("slli", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1938 State
.regs
[OP
[0]] <<= OP
[1];
1939 trace_output (OP_REG
);
1951 trace_input ("slli", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
1952 tmp
= SEXT40(State
.a
[OP
[0]]) << OP
[1];
1957 State
.a
[OP
[0]] = MAX32
;
1958 else if (tmp
< 0xffffff80000000LL
)
1959 State
.a
[OP
[0]] = MIN32
;
1961 State
.a
[OP
[0]] = tmp
& MASK40
;
1964 State
.a
[OP
[0]] = tmp
& MASK40
;
1965 trace_output (OP_ACCUM
);
1974 trace_input ("slx", OP_REG
, OP_FLAG
, OP_VOID
);
1975 State
.regs
[OP
[0]] = (State
.regs
[OP
[0]] << 1) | State
.F0
;
1976 trace_output (OP_REG
);
1983 trace_input ("sra", OP_REG
, OP_REG
, OP_VOID
);
1984 State
.regs
[OP
[0]] = ((int16
)(State
.regs
[OP
[0]])) >> (State
.regs
[OP
[1]] & 0xf);
1985 trace_output (OP_REG
);
1992 trace_input ("sra", OP_ACCUM
, OP_REG
, OP_VOID
);
1993 if (State
.regs
[OP
[1]] & 31 <= 16)
1994 State
.a
[OP
[0]] >>= (State
.regs
[OP
[1]] & 31);
1995 trace_output (OP_ACCUM
);
2002 trace_input ("srai", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2003 State
.regs
[OP
[0]] = ((int16
)(State
.regs
[OP
[0]])) >> OP
[1];
2004 trace_output (OP_REG
);
2014 trace_input ("srai", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2015 State
.a
[OP
[0]] >>= OP
[1];
2016 trace_output (OP_ACCUM
);
2023 trace_input ("srl", OP_REG
, OP_REG
, OP_VOID
);
2024 State
.regs
[OP
[0]] >>= (State
.regs
[OP
[1]] & 0xf);
2025 trace_output (OP_REG
);
2032 trace_input ("srl", OP_ACCUM
, OP_REG
, OP_VOID
);
2033 if (State
.regs
[OP
[1]] & 31 <= 16)
2034 State
.a
[OP
[0]] >>= (State
.regs
[OP
[1]] & 31);
2035 trace_output (OP_ACCUM
);
2042 trace_input ("srli", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2043 State
.regs
[OP
[0]] >>= OP
[1];
2044 trace_output (OP_REG
);
2054 trace_input ("srli", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2055 State
.a
[OP
[0]] >>= OP
[1];
2056 trace_output (OP_ACCUM
);
2065 trace_input ("srx", OP_REG
, OP_FLAG
, OP_VOID
);
2066 tmp
= State
.F0
<< 15;
2067 State
.regs
[OP
[0]] = (State
.regs
[OP
[0]] >> 1) | tmp
;
2068 trace_output (OP_REG
);
2075 trace_input ("st", OP_REG
, OP_MEMREF2
, OP_VOID
);
2076 SW (OP
[1] + State
.regs
[OP
[2]], State
.regs
[OP
[0]]);
2077 trace_output (OP_VOID
);
2084 trace_input ("st", OP_REG
, OP_MEMREF
, OP_VOID
);
2085 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2086 trace_output (OP_VOID
);
2093 trace_input ("st", OP_REG
, OP_PREDEC
, OP_VOID
);
2096 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2097 State
.exception
= SIGILL
;
2100 State
.regs
[OP
[1]] -= 2;
2101 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2102 trace_output (OP_VOID
);
2109 trace_input ("st", OP_REG
, OP_POSTINC
, OP_VOID
);
2110 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2111 INC_ADDR (State
.regs
[OP
[1]],2);
2112 trace_output (OP_VOID
);
2119 trace_input ("st", OP_REG
, OP_POSTDEC
, OP_VOID
);
2120 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2121 INC_ADDR (State
.regs
[OP
[1]],-2);
2122 trace_output (OP_VOID
);
2129 trace_input ("st2w", OP_DREG
, OP_MEMREF2
, OP_VOID
);
2130 SW (State
.regs
[OP
[2]]+OP
[1], State
.regs
[OP
[0]]);
2131 SW (State
.regs
[OP
[2]]+OP
[1]+2, State
.regs
[OP
[0]+1]);
2132 trace_output (OP_VOID
);
2139 trace_input ("st2w", OP_REG
, OP_MEMREF
, OP_VOID
);
2140 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2141 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2142 trace_output (OP_VOID
);
2149 trace_input ("st2w", OP_REG
, OP_PREDEC
, OP_VOID
);
2152 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2153 State
.exception
= SIGILL
;
2156 State
.regs
[OP
[1]] -= 4;
2157 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2158 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2159 trace_output (OP_VOID
);
2166 trace_input ("st2w", OP_REG
, OP_POSTDEC
, OP_VOID
);
2167 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2168 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2169 INC_ADDR (State
.regs
[OP
[1]],4);
2170 trace_output (OP_VOID
);
2177 trace_input ("st2w", OP_REG
, OP_POSTINC
, OP_VOID
);
2178 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2179 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2180 INC_ADDR (State
.regs
[OP
[1]],-4);
2181 trace_output (OP_VOID
);
2188 trace_input ("stb", OP_REG
, OP_MEMREF2
, OP_VOID
);
2189 SB (State
.regs
[OP
[2]]+OP
[1], State
.regs
[OP
[0]]);
2190 trace_output (OP_VOID
);
2197 trace_input ("stb", OP_REG
, OP_MEMREF
, OP_VOID
);
2198 SB (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2199 trace_output (OP_VOID
);
2206 trace_input ("stop", OP_VOID
, OP_VOID
, OP_VOID
);
2207 State
.exception
= SIGQUIT
;
2208 trace_output (OP_VOID
);
2217 trace_input ("sub", OP_REG
, OP_REG
, OP_VOID
);
2218 tmp
= (int16
)State
.regs
[OP
[0]]- (int16
)State
.regs
[OP
[1]];
2219 State
.C
= (tmp
& 0xffff0000) ? 1 : 0;
2220 State
.regs
[OP
[0]] = tmp
& 0xffff;
2221 trace_output (OP_REG
);
2230 trace_input ("sub", OP_ACCUM
, OP_DREG
, OP_VOID
);
2231 tmp
= SEXT40(State
.a
[OP
[0]]) - (SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1]);
2235 State
.a
[OP
[0]] = MAX32
;
2236 else if ( tmp
< MIN32
)
2237 State
.a
[OP
[0]] = MIN32
;
2239 State
.a
[OP
[0]] = tmp
& MASK40
;
2242 State
.a
[OP
[0]] = tmp
& MASK40
;
2244 trace_output (OP_ACCUM
);
2254 trace_input ("sub", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
2255 tmp
= SEXT40(State
.a
[OP
[0]]) - SEXT40(State
.a
[OP
[1]]);
2259 State
.a
[OP
[0]] = MAX32
;
2260 else if ( tmp
< MIN32
)
2261 State
.a
[OP
[0]] = MIN32
;
2263 State
.a
[OP
[0]] = tmp
& MASK40
;
2266 State
.a
[OP
[0]] = tmp
& MASK40
;
2268 trace_output (OP_ACCUM
);
2278 trace_input ("sub2w", OP_DREG
, OP_DREG
, OP_VOID
);
2279 a
= (int32
)((State
.regs
[OP
[0]] << 16) | State
.regs
[OP
[0]+1]);
2280 b
= (int32
)((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
2282 State
.C
= (tmp
& 0xffffffff00000000LL
) ? 1 : 0;
2283 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2284 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2285 trace_output (OP_DREG
);
2294 trace_input ("subac3", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
2295 tmp
= SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]) - SEXT40 (State
.a
[OP
[2]]);
2296 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2297 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2298 trace_output (OP_DREG
);
2307 trace_input ("subac3", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
2308 tmp
= SEXT40(State
.a
[OP
[1]]) - SEXT40(State
.a
[OP
[2]]);
2309 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2310 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2311 trace_output (OP_DREG
);
2320 trace_input ("subac3s", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
2321 State
.F1
= State
.F0
;
2322 tmp
= SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]) - SEXT40(State
.a
[OP
[2]]);
2325 State
.regs
[OP
[0]] = 0x7fff;
2326 State
.regs
[OP
[0]+1] = 0xffff;
2329 else if (tmp
< MIN32
)
2331 State
.regs
[OP
[0]] = 0x8000;
2332 State
.regs
[OP
[0]+1] = 0;
2337 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2338 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2341 trace_output (OP_DREG
);
2350 trace_input ("subac3s", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
2351 State
.F1
= State
.F0
;
2352 tmp
= SEXT40(State
.a
[OP
[1]]) - SEXT40(State
.a
[OP
[2]]);
2355 State
.regs
[OP
[0]] = 0x7fff;
2356 State
.regs
[OP
[0]+1] = 0xffff;
2359 else if (tmp
< MIN32
)
2361 State
.regs
[OP
[0]] = 0x8000;
2362 State
.regs
[OP
[0]+1] = 0;
2367 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2368 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2371 trace_output (OP_DREG
);
2382 trace_input ("subi", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2383 tmp
= (int16
)State
.regs
[OP
[0]] - OP
[1];
2384 State
.C
= (tmp
& 0xffff0000) ? 1 : 0;
2385 State
.regs
[OP
[0]] = tmp
& 0xffff;
2386 trace_output (OP_REG
);
2393 trace_input ("trap", OP_CONSTANT16
, OP_REG
, OP_VOID
);
2394 trace_output (OP_VOID
);
2399 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Unknown trap code %d\n", OP
[0]);
2400 State
.exception
= SIGILL
;
2403 /* Trap 0 is used for simulating low-level I/O */
2405 int save_errno
= errno
;
2408 /* Registers passed to trap 0 */
2410 #define FUNC State.regs[2] /* function number, return value */
2411 #define PARM1 State.regs[3] /* optional parm 1 */
2412 #define PARM2 State.regs[4] /* optional parm 2 */
2413 #define PARM3 State.regs[5] /* optional parm 3 */
2415 /* Registers set by trap 0 */
2417 #define RETVAL State.regs[2] /* return value */
2418 #define RETERR State.regs[3] /* return error code */
2420 /* Turn a pointer in a register into a pointer into real memory. */
2422 #define MEMPTR(x) ((char *)((x) + State.imem))
2426 #if !defined(__GO32__) && !defined(_WIN32)
2434 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
),
2435 (char **)MEMPTR (PARM3
));
2440 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
), NULL
);
2450 RETVAL
= pipe (host_fd
);
2451 SW (buf
, host_fd
[0]);
2452 buf
+= sizeof(uint16
);
2453 SW (buf
, host_fd
[1]);
2462 RETVAL
= wait (&status
);
2471 RETVAL
= d10v_callback
->read (d10v_callback
, PARM1
, MEMPTR (PARM2
),
2478 RETVAL
= (int)d10v_callback
->write_stdout (d10v_callback
,
2479 MEMPTR (PARM2
), PARM3
);
2481 RETVAL
= (int)d10v_callback
->write (d10v_callback
, PARM1
,
2482 MEMPTR (PARM2
), PARM3
);
2487 RETVAL
= d10v_callback
->lseek (d10v_callback
, PARM1
, PARM2
, PARM3
);
2492 RETVAL
= d10v_callback
->close (d10v_callback
, PARM1
);
2497 RETVAL
= d10v_callback
->open (d10v_callback
, MEMPTR (PARM1
), PARM2
);
2502 /* EXIT - caller can look in PARM1 to work out the
2504 State
.exception
= SIGQUIT
;
2510 /* stat system call */
2512 struct stat host_stat
;
2515 RETVAL
= stat (MEMPTR (PARM1
), &host_stat
);
2519 /* The hard-coded offsets and sizes were determined by using
2520 * the D10V compiler on a test program that used struct stat.
2522 SW (buf
, host_stat
.st_dev
);
2523 SW (buf
+2, host_stat
.st_ino
);
2524 SW (buf
+4, host_stat
.st_mode
);
2525 SW (buf
+6, host_stat
.st_nlink
);
2526 SW (buf
+8, host_stat
.st_uid
);
2527 SW (buf
+10, host_stat
.st_gid
);
2528 SW (buf
+12, host_stat
.st_rdev
);
2529 SLW (buf
+16, host_stat
.st_size
);
2530 SLW (buf
+20, host_stat
.st_atime
);
2531 SLW (buf
+28, host_stat
.st_mtime
);
2532 SLW (buf
+36, host_stat
.st_ctime
);
2539 RETVAL
= chown (MEMPTR (PARM1
), PARM2
, PARM3
);
2544 RETVAL
= chmod (MEMPTR (PARM1
), PARM2
);
2549 /* Cast the second argument to void *, to avoid type mismatch
2550 if a prototype is present. */
2551 RETVAL
= utime (MEMPTR (PARM1
), (void *) MEMPTR (PARM2
));
2563 /* Trap 1 prints a string */
2565 char *fstr
= State
.regs
[2] + State
.imem
;
2566 fputs (fstr
, stdout
);
2571 /* Trap 2 calls printf */
2573 char *fstr
= State
.regs
[2] + State
.imem
;
2574 (*d10v_callback
->printf_filtered
) (d10v_callback
, fstr
,
2575 (int16
)State
.regs
[3],
2576 (int16
)State
.regs
[4],
2577 (int16
)State
.regs
[5]);
2582 /* Trap 3 writes a character */
2583 putchar (State
.regs
[2]);
2592 trace_input ("tst0i", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2593 State
.F1
= State
.F0
;
2594 State
.F0
= (State
.regs
[OP
[0]] & OP
[1]) ? 1 : 0;
2595 trace_output (OP_FLAG
);
2602 trace_input ("tst1i", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2603 State
.F1
= State
.F0
;
2604 State
.F0
= (~(State
.regs
[OP
[0]]) & OP
[1]) ? 1 : 0;
2605 trace_output (OP_FLAG
);
2612 trace_input ("wait", OP_VOID
, OP_VOID
, OP_VOID
);
2614 trace_output (OP_VOID
);
2621 trace_input ("xor", OP_REG
, OP_REG
, OP_VOID
);
2622 State
.regs
[OP
[0]] ^= State
.regs
[OP
[1]];
2623 trace_output (OP_REG
);
2630 trace_input ("xor3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
2631 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] ^ OP
[2];
2632 trace_output (OP_REG
);